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439 lines
18 KiB
439 lines
18 KiB
#include <string.h>
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#include <stdlib.h>
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#include <stdint.h>
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#include <stdio.h>
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#include "spi.h"
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//#include "ad9779.h"
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//#include "cmd.h"
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#include "gpio.h"
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#include "dwt.h"
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#include "timer_list.h"
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#include "ad9361_api.h"
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#include "ad9361.h"
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uint8_t buf_rx[8] = {0}, buf_tx[8] = {0};
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int flag = 0;
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uint8_t reg_r = 0x00;
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AD9361_InitParam default_init_param = {
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/* Device selection */
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ID_AD9361, // dev_sel
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/* Identification number */
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0, //id_no
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/* Reference Clock */
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40000000UL, //reference_clk_rate
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/* Base Configuration */
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1, //two_rx_two_tx_mode_enable *** adi,2rx-2tx-mode-enable
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1, //one_rx_one_tx_mode_use_rx_num *** adi,1rx-1tx-mode-use-rx-num
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1, //one_rx_one_tx_mode_use_tx_num *** adi,1rx-1tx-mode-use-tx-num
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1, //frequency_division_duplex_mode_enable *** adi,frequency-division-duplex-mode-enable
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0, //frequency_division_duplex_independent_mode_enable *** adi,frequency-division-duplex-independent-mode-enable
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0, //tdd_use_dual_synth_mode_enable *** adi,tdd-use-dual-synth-mode-enable
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0, //tdd_skip_vco_cal_enable *** adi,tdd-skip-vco-cal-enable
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0, //tx_fastlock_delay_ns *** adi,tx-fastlock-delay-ns
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0, //rx_fastlock_delay_ns *** adi,rx-fastlock-delay-ns
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0, //rx_fastlock_pincontrol_enable *** adi,rx-fastlock-pincontrol-enable
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0, //tx_fastlock_pincontrol_enable *** adi,tx-fastlock-pincontrol-enable
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0, //external_rx_lo_enable *** adi,external-rx-lo-enable
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0, //external_tx_lo_enable *** adi,external-tx-lo-enable
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5, //dc_offset_tracking_update_event_mask *** adi,dc-offset-tracking-update-event-mask
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6, //dc_offset_attenuation_high_range *** adi,dc-offset-attenuation-high-range
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5, //dc_offset_attenuation_low_range *** adi,dc-offset-attenuation-low-range
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0x28, //dc_offset_count_high_range *** adi,dc-offset-count-high-range
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0x32, //dc_offset_count_low_range *** adi,dc-offset-count-low-range
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0, //split_gain_table_mode_enable *** adi,split-gain-table-mode-enable
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MAX_SYNTH_FREF, //trx_synthesizer_target_fref_overwrite_hz *** adi,trx-synthesizer-target-fref-overwrite-hz
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0, // qec_tracking_slow_mode_enable *** adi,qec-tracking-slow-mode-enable
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/* ENSM Control */
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0, //ensm_enable_pin_pulse_mode_enable *** adi,ensm-enable-pin-pulse-mode-enable
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0, //ensm_enable_txnrx_control_enable *** adi,ensm-enable-txnrx-control-enable
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/* LO Control */
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2000000000UL, //rx_synthesizer_frequency_hz *** adi,rx-synthesizer-frequency-hz
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2000000000UL, //tx_synthesizer_frequency_hz *** adi,tx-synthesizer-frequency-hz
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/* Rate & BW Control */
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{983040000, 245760000, 122880000, 61440000, 30720000, 30720000},//uint32_t rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies
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{983040000, 122880000, 122880000, 61440000, 30720000, 30720000},//uint32_t tx_path_clock_frequencies[6] *** adi,tx-path-clock-frequencies
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18000000,//rf_rx_bandwidth_hz *** adi,rf-rx-bandwidth-hz
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18000000,//rf_tx_bandwidth_hz *** adi,rf-tx-bandwidth-hz
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/* RF Port Control */
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0, //rx_rf_port_input_select *** adi,rx-rf-port-input-select
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0, //tx_rf_port_input_select *** adi,tx-rf-port-input-select
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/* TX Attenuation Control */
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10000, //tx_attenuation_mdB *** adi,tx-attenuation-mdB
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0, //update_tx_gain_in_alert_enable *** adi,update-tx-gain-in-alert-enable
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/* Reference Clock Control */
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0, //xo_disable_use_ext_refclk_enable *** adi,xo-disable-use-ext-refclk-enable
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{8, 5920}, //dcxo_coarse_and_fine_tune[2] *** adi,dcxo-coarse-and-fine-tune
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ADC_CLK_DIV_8, //clk_output_mode_select *** adi,clk-output-mode-select
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/* Gain Control */
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2, //gc_rx1_mode *** adi,gc-rx1-mode
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2, //gc_rx2_mode *** adi,gc-rx2-mode
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58, //gc_adc_large_overload_thresh *** adi,gc-adc-large-overload-thresh
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4, //gc_adc_ovr_sample_size *** adi,gc-adc-ovr-sample-size
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47, //gc_adc_small_overload_thresh *** adi,gc-adc-small-overload-thresh
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8192, //gc_dec_pow_measurement_duration *** adi,gc-dec-pow-measurement-duration
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0, //gc_dig_gain_enable *** adi,gc-dig-gain-enable
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800, //gc_lmt_overload_high_thresh *** adi,gc-lmt-overload-high-thresh
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704, //gc_lmt_overload_low_thresh *** adi,gc-lmt-overload-low-thresh
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24, //gc_low_power_thresh *** adi,gc-low-power-thresh
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15, //gc_max_dig_gain *** adi,gc-max-dig-gain
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/* Gain MGC Control */
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2, //mgc_dec_gain_step *** adi,mgc-dec-gain-step
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2, //mgc_inc_gain_step *** adi,mgc-inc-gain-step
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0, //mgc_rx1_ctrl_inp_enable *** adi,mgc-rx1-ctrl-inp-enable
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0, //mgc_rx2_ctrl_inp_enable *** adi,mgc-rx2-ctrl-inp-enable
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0, //mgc_split_table_ctrl_inp_gain_mode *** adi,mgc-split-table-ctrl-inp-gain-mode
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/* Gain AGC Control */
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10, //agc_adc_large_overload_exceed_counter *** adi,agc-adc-large-overload-exceed-counter
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2, //agc_adc_large_overload_inc_steps *** adi,agc-adc-large-overload-inc-steps
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0, //agc_adc_lmt_small_overload_prevent_gain_inc_enable *** adi,agc-adc-lmt-small-overload-prevent-gain-inc-enable
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10, //agc_adc_small_overload_exceed_counter *** adi,agc-adc-small-overload-exceed-counter
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4, //agc_dig_gain_step_size *** adi,agc-dig-gain-step-size
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3, //agc_dig_saturation_exceed_counter *** adi,agc-dig-saturation-exceed-counter
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1000, // agc_gain_update_interval_us *** adi,agc-gain-update-interval-us
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0, //agc_immed_gain_change_if_large_adc_overload_enable *** adi,agc-immed-gain-change-if-large-adc-overload-enable
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0, //agc_immed_gain_change_if_large_lmt_overload_enable *** adi,agc-immed-gain-change-if-large-lmt-overload-enable
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10, //agc_inner_thresh_high *** adi,agc-inner-thresh-high
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1, //agc_inner_thresh_high_dec_steps *** adi,agc-inner-thresh-high-dec-steps
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12, //agc_inner_thresh_low *** adi,agc-inner-thresh-low
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1, //agc_inner_thresh_low_inc_steps *** adi,agc-inner-thresh-low-inc-steps
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10, //agc_lmt_overload_large_exceed_counter *** adi,agc-lmt-overload-large-exceed-counter
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2, //agc_lmt_overload_large_inc_steps *** adi,agc-lmt-overload-large-inc-steps
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10, //agc_lmt_overload_small_exceed_counter *** adi,agc-lmt-overload-small-exceed-counter
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5, //agc_outer_thresh_high *** adi,agc-outer-thresh-high
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2, //agc_outer_thresh_high_dec_steps *** adi,agc-outer-thresh-high-dec-steps
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18, //agc_outer_thresh_low *** adi,agc-outer-thresh-low
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2, //agc_outer_thresh_low_inc_steps *** adi,agc-outer-thresh-low-inc-steps
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1, //agc_attack_delay_extra_margin_us; *** adi,agc-attack-delay-extra-margin-us
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0, //agc_sync_for_gain_counter_enable *** adi,agc-sync-for-gain-counter-enable
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/* Fast AGC */
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64, //fagc_dec_pow_measuremnt_duration *** adi,fagc-dec-pow-measurement-duration
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260, //fagc_state_wait_time_ns *** adi,fagc-state-wait-time-ns
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/* Fast AGC - Low Power */
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0, //fagc_allow_agc_gain_increase *** adi,fagc-allow-agc-gain-increase-enable
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5, //fagc_lp_thresh_increment_time *** adi,fagc-lp-thresh-increment-time
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1, //fagc_lp_thresh_increment_steps *** adi,fagc-lp-thresh-increment-steps
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/* Fast AGC - Lock Level */
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10, //fagc_lock_level *** adi,fagc-lock-level
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1, //fagc_lock_level_lmt_gain_increase_en *** adi,fagc-lock-level-lmt-gain-increase-enable
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5, //fagc_lock_level_gain_increase_upper_limit *** adi,fagc-lock-level-gain-increase-upper-limit
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/* Fast AGC - Peak Detectors and Final Settling */
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1, //fagc_lpf_final_settling_steps *** adi,fagc-lpf-final-settling-steps
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1, //fagc_lmt_final_settling_steps *** adi,fagc-lmt-final-settling-steps
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3, //fagc_final_overrange_count *** adi,fagc-final-overrange-count
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/* Fast AGC - Final Power Test */
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0, //fagc_gain_increase_after_gain_lock_en *** adi,fagc-gain-increase-after-gain-lock-enable
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/* Fast AGC - Unlocking the Gain */
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0, //fagc_gain_index_type_after_exit_rx_mode *** adi,fagc-gain-index-type-after-exit-rx-mode
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1, //fagc_use_last_lock_level_for_set_gain_en *** adi,fagc-use-last-lock-level-for-set-gain-enable
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1, //fagc_rst_gla_stronger_sig_thresh_exceeded_en *** adi,fagc-rst-gla-stronger-sig-thresh-exceeded-enable
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5, //fagc_optimized_gain_offset *** adi,fagc-optimized-gain-offset
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10, //fagc_rst_gla_stronger_sig_thresh_above_ll *** adi,fagc-rst-gla-stronger-sig-thresh-above-ll
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1, //fagc_rst_gla_engergy_lost_sig_thresh_exceeded_en *** adi,fagc-rst-gla-engergy-lost-sig-thresh-exceeded-enable
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1, //fagc_rst_gla_engergy_lost_goto_optim_gain_en *** adi,fagc-rst-gla-engergy-lost-goto-optim-gain-enable
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10, //fagc_rst_gla_engergy_lost_sig_thresh_below_ll *** adi,fagc-rst-gla-engergy-lost-sig-thresh-below-ll
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8, //fagc_energy_lost_stronger_sig_gain_lock_exit_cnt *** adi,fagc-energy-lost-stronger-sig-gain-lock-exit-cnt
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1, //fagc_rst_gla_large_adc_overload_en *** adi,fagc-rst-gla-large-adc-overload-enable
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1, //fagc_rst_gla_large_lmt_overload_en *** adi,fagc-rst-gla-large-lmt-overload-enable
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0, //fagc_rst_gla_en_agc_pulled_high_en *** adi,fagc-rst-gla-en-agc-pulled-high-enable
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0, //fagc_rst_gla_if_en_agc_pulled_high_mode *** adi,fagc-rst-gla-if-en-agc-pulled-high-mode
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64, //fagc_power_measurement_duration_in_state5 *** adi,fagc-power-measurement-duration-in-state5
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/* RSSI Control */
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1, //rssi_delay *** adi,rssi-delay
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1000, //rssi_duration *** adi,rssi-duration
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3, //rssi_restart_mode *** adi,rssi-restart-mode
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0, //rssi_unit_is_rx_samples_enable *** adi,rssi-unit-is-rx-samples-enable
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1, //rssi_wait *** adi,rssi-wait
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/* Aux ADC Control */
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256, //aux_adc_decimation *** adi,aux-adc-decimation
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40000000UL, //aux_adc_rate *** adi,aux-adc-rate
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/* AuxDAC Control */
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1, //aux_dac_manual_mode_enable *** adi,aux-dac-manual-mode-enable
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0, //aux_dac1_default_value_mV *** adi,aux-dac1-default-value-mV
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0, //aux_dac1_active_in_rx_enable *** adi,aux-dac1-active-in-rx-enable
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0, //aux_dac1_active_in_tx_enable *** adi,aux-dac1-active-in-tx-enable
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0, //aux_dac1_active_in_alert_enable *** adi,aux-dac1-active-in-alert-enable
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0, //aux_dac1_rx_delay_us *** adi,aux-dac1-rx-delay-us
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0, //aux_dac1_tx_delay_us *** adi,aux-dac1-tx-delay-us
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0, //aux_dac2_default_value_mV *** adi,aux-dac2-default-value-mV
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0, //aux_dac2_active_in_rx_enable *** adi,aux-dac2-active-in-rx-enable
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0, //aux_dac2_active_in_tx_enable *** adi,aux-dac2-active-in-tx-enable
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0, //aux_dac2_active_in_alert_enable *** adi,aux-dac2-active-in-alert-enable
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0, //aux_dac2_rx_delay_us *** adi,aux-dac2-rx-delay-us
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0, //aux_dac2_tx_delay_us *** adi,aux-dac2-tx-delay-us
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/* Temperature Sensor Control */
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256, //temp_sense_decimation *** adi,temp-sense-decimation
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1000, //temp_sense_measurement_interval_ms *** adi,temp-sense-measurement-interval-ms
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0xCE, //temp_sense_offset_signed *** adi,temp-sense-offset-signed
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1, //temp_sense_periodic_measurement_enable *** adi,temp-sense-periodic-measurement-enable
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/* Control Out Setup */
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0xFF, //ctrl_outs_enable_mask *** adi,ctrl-outs-enable-mask
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0, //ctrl_outs_index *** adi,ctrl-outs-index
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/* External LNA Control */
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0, //elna_settling_delay_ns *** adi,elna-settling-delay-ns
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0, //elna_gain_mdB *** adi,elna-gain-mdB
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0, //elna_bypass_loss_mdB *** adi,elna-bypass-loss-mdB
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0, //elna_rx1_gpo0_control_enable *** adi,elna-rx1-gpo0-control-enable
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0, //elna_rx2_gpo1_control_enable *** adi,elna-rx2-gpo1-control-enable
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0, //elna_gaintable_all_index_enable *** adi,elna-gaintable-all-index-enable
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/* Digital Interface Control */
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0, //digital_interface_tune_skip_mode *** adi,digital-interface-tune-skip-mode
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0, //digital_interface_tune_fir_disable *** adi,digital-interface-tune-fir-disable
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1, //pp_tx_swap_enable *** adi,pp-tx-swap-enable
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1, //pp_rx_swap_enable *** adi,pp-rx-swap-enable
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0, //tx_channel_swap_enable *** adi,tx-channel-swap-enable
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0, //rx_channel_swap_enable *** adi,rx-channel-swap-enable
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1, //rx_frame_pulse_mode_enable *** adi,rx-frame-pulse-mode-enable
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0, //two_t_two_r_timing_enable *** adi,2t2r-timing-enable
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0, //invert_data_bus_enable *** adi,invert-data-bus-enable
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0, //invert_data_clk_enable *** adi,invert-data-clk-enable
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0, //fdd_alt_word_order_enable *** adi,fdd-alt-word-order-enable
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0, //invert_rx_frame_enable *** adi,invert-rx-frame-enable
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0, //fdd_rx_rate_2tx_enable *** adi,fdd-rx-rate-2tx-enable
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0, //swap_ports_enable *** adi,swap-ports-enable
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0, //single_data_rate_enable *** adi,single-data-rate-enable
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1, //lvds_mode_enable *** adi,lvds-mode-enable
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0, //half_duplex_mode_enable *** adi,half-duplex-mode-enable
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0, //single_port_mode_enable *** adi,single-port-mode-enable
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0, //full_port_enable *** adi,full-port-enable
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0, //full_duplex_swap_bits_enable *** adi,full-duplex-swap-bits-enable
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0, //delay_rx_data *** adi,delay-rx-data
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0, //rx_data_clock_delay *** adi,rx-data-clock-delay
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4, //rx_data_delay *** adi,rx-data-delay
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7, //tx_fb_clock_delay *** adi,tx-fb-clock-delay
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0, //tx_data_delay *** adi,tx-data-delay
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150, //lvds_bias_mV *** adi,lvds-bias-mV
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1, //lvds_rx_onchip_termination_enable *** adi,lvds-rx-onchip-termination-enable
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0, //rx1rx2_phase_inversion_en *** adi,rx1-rx2-phase-inversion-enable
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0xFF, //lvds_invert1_control *** adi,lvds-invert1-control
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0x0F, //lvds_invert2_control *** adi,lvds-invert2-control
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/* GPO Control */
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0, //gpo0_inactive_state_high_enable *** adi,gpo0-inactive-state-high-enable
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0, //gpo1_inactive_state_high_enable *** adi,gpo1-inactive-state-high-enable
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0, //gpo2_inactive_state_high_enable *** adi,gpo2-inactive-state-high-enable
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0, //gpo3_inactive_state_high_enable *** adi,gpo3-inactive-state-high-enable
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0, //gpo0_slave_rx_enable *** adi,gpo0-slave-rx-enable
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0, //gpo0_slave_tx_enable *** adi,gpo0-slave-tx-enable
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0, //gpo1_slave_rx_enable *** adi,gpo1-slave-rx-enable
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0, //gpo1_slave_tx_enable *** adi,gpo1-slave-tx-enable
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0, //gpo2_slave_rx_enable *** adi,gpo2-slave-rx-enable
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0, //gpo2_slave_tx_enable *** adi,gpo2-slave-tx-enable
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0, //gpo3_slave_rx_enable *** adi,gpo3-slave-rx-enable
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0, //gpo3_slave_tx_enable *** adi,gpo3-slave-tx-enable
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0, //gpo0_rx_delay_us *** adi,gpo0-rx-delay-us
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0, //gpo0_tx_delay_us *** adi,gpo0-tx-delay-us
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0, //gpo1_rx_delay_us *** adi,gpo1-rx-delay-us
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0, //gpo1_tx_delay_us *** adi,gpo1-tx-delay-us
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0, //gpo2_rx_delay_us *** adi,gpo2-rx-delay-us
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0, //gpo2_tx_delay_us *** adi,gpo2-tx-delay-us
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0, //gpo3_rx_delay_us *** adi,gpo3-rx-delay-us
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0, //gpo3_tx_delay_us *** adi,gpo3-tx-delay-us
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/* Tx Monitor Control */
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37000, //low_high_gain_threshold_mdB *** adi,txmon-low-high-thresh
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0, //low_gain_dB *** adi,txmon-low-gain
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24, //high_gain_dB *** adi,txmon-high-gain
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0, //tx_mon_track_en *** adi,txmon-dc-tracking-enable
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0, //one_shot_mode_en *** adi,txmon-one-shot-mode-enable
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511, //tx_mon_delay *** adi,txmon-delay
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8192, //tx_mon_duration *** adi,txmon-duration
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2, //tx1_mon_front_end_gain *** adi,txmon-1-front-end-gain
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2, //tx2_mon_front_end_gain *** adi,txmon-2-front-end-gain
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48, //tx1_mon_lo_cm *** adi,txmon-1-lo-cm
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48, //tx2_mon_lo_cm *** adi,txmon-2-lo-cm
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/* GPIO definitions */
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-1, //gpio_resetb *** reset-gpios
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/* MCS Sync */
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-1, //gpio_sync *** sync-gpios
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-1, //gpio_cal_sw1 *** cal-sw1-gpios
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-1, //gpio_cal_sw2 *** cal-sw2-gpios
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/* External LO clocks */
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NULL, //(*ad9361_rfpll_ext_recalc_rate)()
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NULL, //(*ad9361_rfpll_ext_round_rate)()
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NULL //(*ad9361_rfpll_ext_set_rate)()
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};
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void ad_spi_init()
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{
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gpio_init(PI9, GPIO_INPUT);
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gpio_init(PI10, GPIO_OUTPUT);
|
|
gpio_init(PD1, GPIO_OUTPUT);
|
|
//gpio_set(PI9);
|
|
gpio_set(PI10);
|
|
gpio_set(PD1);
|
|
spi_setup(&spi1, PB12, SPI_MODE_3, 1000000);
|
|
}
|
|
|
|
|
|
#if 0
|
|
void ad9779_write(uint8_t reg, uint8_t data)
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_3);
|
|
buf_tx[1] = data;
|
|
gpio_clear(PI9);
|
|
gpio_clear(PI10);
|
|
dwt_wait_ms(10);
|
|
|
|
buf_tx[0] = 0x00 | reg;
|
|
|
|
spi_transfer(&spi1, buf_tx, NULL, 2);
|
|
printf("reg = 0x%x data = 0x%x\r\n", buf_tx[0],buf_tx[1]);
|
|
}
|
|
|
|
|
|
uint8_t ad9779_read(uint8_t reg)
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_3);
|
|
buf_tx[1] = 0xFF;
|
|
gpio_clear(PI9);
|
|
gpio_clear(PI10);
|
|
dwt_wait_ms(10);
|
|
|
|
buf_tx[0] = 0x80 | reg;
|
|
|
|
//spi_txrx(&spi1, buf_tx[0]);
|
|
//buf_rx[1] = spi_txrx(&spi1, buf_tx[1]);
|
|
spi_transfer(&spi1, buf_tx, buf_rx, 2);
|
|
|
|
gpio_set(PI9);
|
|
gpio_set(PI10);
|
|
|
|
//printf("reg = 0x%x data = 0x%x data_tx = %x\r\n", buf_tx[0],buf_rx[1],buf_rx[0]);
|
|
|
|
return buf_rx[1];
|
|
}
|
|
#endif
|
|
|
|
void axi_write(uint16_t reg, uint32_t data)
|
|
{
|
|
if(!gpio_read(PI9))
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_0);
|
|
uint8_t /*__reg[2],*/ __data[8];
|
|
gpio_set(PI10);
|
|
|
|
__data[0] = (reg >> 8) & 0xff;
|
|
__data[1] = reg & 0xff;
|
|
|
|
__data[2] = (data >> 24) & 0xff;
|
|
__data[3] = (data >> 16) & 0xff;
|
|
__data[4] = (data >> 8) & 0xff;
|
|
__data[5] = data & 0xff;
|
|
|
|
for(int i=0; i<6; i++){
|
|
printf("data = %x \r\n",__data[i]);
|
|
}
|
|
spi_transfer(&spi1, __data, NULL, 6);
|
|
printf("axi write \r\n");
|
|
|
|
gpio_set(PI10);
|
|
}
|
|
}
|
|
|
|
|
|
uint32_t axi_read(uint16_t reg)
|
|
{
|
|
uint8_t __tx[8] = {0}, __rx[8] = {1};
|
|
uint32_t __data = 0;
|
|
if(!gpio_read(PI9))
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_0);
|
|
gpio_set(PI10);
|
|
|
|
__tx[0] = ((reg >> 8) & 0xff) | 0x80;
|
|
__tx[1] = reg & 0xff;
|
|
|
|
__tx[2] = 0xff;
|
|
__tx[3] = 0xff;
|
|
__tx[4] = 0xff;
|
|
__tx[5] = 0xff;
|
|
|
|
spi_transfer(&spi1, __tx, __rx, 6);
|
|
|
|
gpio_set(PI10);
|
|
|
|
for(int i=0; i<6; i++)
|
|
{
|
|
__data = __data << 8;
|
|
__data = __data | __rx[i+2];
|
|
printf("axi read data = %x\r\n",__rx[i+2]);
|
|
}
|
|
}
|
|
return __data;
|
|
}
|
|
|
|
/*
|
|
void AD9361_init()
|
|
{
|
|
struct ad9361_rf_phy *rx_phy;
|
|
uint32_t ensm_mode;
|
|
|
|
default_init_param.gpio_sync = -1;
|
|
default_init_param.gpio_cal_sw1 = -1;
|
|
default_init_param.gpio_cal_sw2 = -1;
|
|
default_init_param.rx_data_delay = 1;
|
|
|
|
default_init_param.dev_sel = ID_AD9361;
|
|
|
|
axi_write(0x1010, 0x0);
|
|
dwt_wait_ms(10);
|
|
axi_write(0x1010, 0x1);
|
|
dwt_wait_ms(10);
|
|
|
|
}
|
|
|
|
int ad9361_reset()
|
|
{
|
|
axi_write(0x1010, 0x0);
|
|
dwt_wait_ms(10);
|
|
axi_write(0x1010, 0x1);
|
|
dwt_wait_ms(10);
|
|
}
|
|
*/
|
|
|
|
uint8_t ad9361_read(uint16_t reg)
|
|
{
|
|
if(!gpio_read(PI9))
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_1);
|
|
|
|
buf_tx[0] = (reg >> 8) & 0x03;
|
|
buf_tx[1] = reg & 0xff;
|
|
buf_tx[2] = 0xFF;
|
|
gpio_clear(PI10);
|
|
dwt_wait_ms(50);
|
|
|
|
spi_transfer(&spi1, buf_tx, buf_rx, 3);
|
|
|
|
dwt_wait_ms(50);
|
|
|
|
gpio_set(PI10);
|
|
|
|
printf("reg = 0x%x data = 0x%x\r\n", buf_tx[1],buf_rx[2]);
|
|
}
|
|
|
|
return buf_rx[2];
|
|
}
|
|
|
|
uint8_t ad9361_write(uint16_t reg, uint8_t data)
|
|
{
|
|
if(!gpio_read(PI9))
|
|
{
|
|
spi_set_mode(&spi1, SPI_MODE_1);
|
|
|
|
buf_tx[0] = ((reg >> 8) & 0x03) | 0x80;
|
|
buf_tx[1] = reg & 0xff;
|
|
buf_tx[2] = data;
|
|
gpio_clear(PI10);
|
|
dwt_wait_ms(10);
|
|
|
|
spi_transfer(&spi1, buf_tx, buf_rx, 3);
|
|
|
|
gpio_set(PI10);
|
|
|
|
printf("reg = 0x%x data = 0x%x\r\n", buf_tx[1],data);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|