|
|
|
|
[Normal]
|
|
|
|
|
synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
|
|
|
|
|
_vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
|
|
|
|
|
_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,
|
|
|
|
|
_EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
|
|
|
|
|
_EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
|
|
|
|
|
_EdfPerDesignOptTiming=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
|
|
|
|
|
_EdfOutputPreFile=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfMapLogic=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
|
|
|
|
|
_EdfInsertIO=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
|
|
|
|
|
_EdfOutNetForm=lc4k_pvlg, Verilog.TASKLSVlog, 0, None
|
|
|
|
|
_EdfNumCritPath=lc4k_pvlg, Verilog.TASKLSVlog, 0, 3
|
|
|
|
|
_EdfUnconsClk=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
|
|
|
|
|
_EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
|
|
|
|
|
_EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
|
|
|
|
|
[synthesis-type]
|
|
|
|
|
tool=Synplify
|
|
|
|
|
[STRATEGY-LIST]
|
|
|
|
|
Normal=True, 1595388407
|
|
|
|
|
[TOUCHED-REPORT]
|
|
|
|
|
Design.bl5File=1595811534
|
