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148 lines
2.4 KiB
148 lines
2.4 KiB
4 years ago
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[Device]
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Family = lc4k;
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PartNumber = LC4128V-10T100I;
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Package = 100TQFP;
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PartType = LC4128V;
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Speed = -10;
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Operating_condition = IND;
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Status = Production;
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EN_PinGLB = yes;
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EN_PinMacrocell = yes;
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[Revision]
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Parent = lc4k128v.lci;
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DATE = 07/22/2020;
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TIME = 19:02:52;
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Source_Format = Pure_Verilog_HDL;
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Synthesis = Synplify;
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[Ignore Assignments]
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[Clear Assignments]
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[Backannotate Assignments]
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[Global Constraints]
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[Location Assignments]
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layer = OFF;
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ft_por = Pin, 94, -, A, 6;
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gpio0_a1 = Pin, 92, -, A, 2;
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pwr_0v8_en = Pin, 41, -, E, 0;
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pwr_1v2_en = Pin, 42, -, E, 2;
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pwr_1v8_en = Pin, 43, -, E, 4;
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pwr_2v5_en = Pin, 44, -, E, 6;
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pwr_3v3_en = Pin, 47, -, E, 8;
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rst_done_led = Pin, 56, -, F, 6;
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ft_pwr_ctl0 = Pin, 97, -, A, 8;
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ft_pwr_ctl1 = Pin, 98, -, A, 10;
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pcierst_0_ = Pin, 48, -, E, 10;
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pcierst_1_ = Pin, 49, -, E, 12;
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pcierst_2_ = Pin, 50, -, E, 14;
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pcierst_3_ = Pin, 53, -, F, 0;
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pcierst_4_ = Pin, 54, -, F, 2;
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cpld_clk_33M = Pin, 88, -, -, -;
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[Group Assignments]
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layer = OFF;
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[Resource Reservations]
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layer = OFF;
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[Fitter Report Format]
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[Power]
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[Source Constraint Option]
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[Fast Bypass]
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[OSM Bypass]
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[Input Registers]
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[Netlist/Delay Format]
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NetList = VERILOG;
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[IO Types]
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layer = OFF;
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[Pullup]
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[Slewrate]
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[Region]
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[Timing Constraints]
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layer = OFF;
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[HSI Attributes]
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[Input Delay]
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[opt global constraints list]
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[Explorer User Settings]
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[Pin attributes list]
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[global constraints list]
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[Global Constraints Process Update]
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[pin lock limitation]
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[LOCATION ASSIGNMENTS LIST]
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[RESOURCE RESERVATIONS LIST]
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[individual constraints list]
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[Attributes list setting]
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[Timing Analyzer]
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[PLL Assignments]
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[Dual Function Macrocell]
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[Explorer Results]
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[VHDL synplify constraints]
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[VHDL spectrum constraints]
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[verilog synplify constraints]
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[verilog spectrum constraints]
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[VHDL synplify constraints list]
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[VHDL spectrum constraints list]
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[verilog synplify constraints list]
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[verilog spectrum constraints list]
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[ORP Bypass]
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[Register Powerup]
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RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en,
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rst_done_led, pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, pcierst_4_;
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[Constraint Version]
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version = 1.0;
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[ORP ASSIGNMENTS]
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layer = OFF;
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[Node attribute]
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layer = OFF;
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[SYMBOL/MODULE attribute]
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layer = OFF;
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[Nodal Constraints]
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layer = OFF;
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