diff --git a/ft2004.sty b/ft2004.sty index 5f20fa1..b1dd68a 100644 --- a/ft2004.sty +++ b/ft2004.sty @@ -17,9 +17,9 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False -[synthesis-type] -tool=Synplify [STRATEGY-LIST] Normal=True, 1595388407 [TOUCHED-REPORT] Design.bl5File=1595811534 +[synthesis-type] +tool=Synplify diff --git a/src/ft2004_top.v b/src/ft2004_top.v index 210ed64..2c5b30f 100644 --- a/src/ft2004_top.v +++ b/src/ft2004_top.v @@ -5,30 +5,32 @@ ////////////////////////////////////////////////////////////////////////////////// module top( - input clk_33m, //88, 33M, 30NS - input por_rst, //73 active low - input sys_rst_in, //72 active low - input ft_pwr_ctl0, //97 - input ft_pwr_ctl1, //98 - - output reg pwr_0v8_en, //41 - output reg pwr_1v2_en, //42 - output reg pwr_1v8_en, //43 - output reg pwr_2v5_en, //44 - output reg pwr_3v3_en, //47 - output reg [3:0] pcierst, //bit0: 48~49~50~53 bit4 active low - output reg nvme_rst_n, //54 active low - output reg ft_por, //94 - output reg gpio0_a1, //92 - - output reg run_led_n, //56 - + input clk_33m, //88, 33M, 30NS + input por_rst, //73 active low + input sys_rst_in, //72 active low + input ft_pwr_ctl0, //97 + input ft_pwr_ctl1, //98 + + output reg pwr_0v8_en, //41 + output reg pwr_1v2_en, //42 + output reg pwr_1v8_en, //43 + output pwr_2v5_en, //44 + output reg pwr_3v3_en, //47 + output [3:0] pcierst, //bit0: 48~49~50~53 bit4 active low + + + output reg nvme_rst_n, //54 active low + output reg ft_por, //94 + output reg gpio0_a1, //92 + + output reg run_led_n, //56 + // can0 input ft_can_txd0, // 3, 1.8v output ft_can_rxd0, // 4, 1.8v input can_rx0, // 58, 3.3v output can_tx0, // 59, 3.3v - + // spi0 input ft_spi0_sck, // 5, 1.8v output ft_spi0_so, // 6, 1.8v @@ -42,17 +44,17 @@ module top( input ft_spi1_csn3, // 22, 1.8v output spi0_csn3, // 65, 3.3v output spi1_csn3, // 64, 3.3v - + // i2c3 input ft_i2c_scl3, // 10, 1.8v inout ft_i2c_sda3, // 11, 1.8v output i2c_scl3, // 60, 3.3v inout i2c_sda3, // 61, 3.3v - + // gpio0 input ft_gpio0_a3, // 99, 1.8v reserved input ft_gpio1_a3, // 20, 1.8v reserved - + inout ft_gpio1_a4, // 19, 1.8v inout ft_gpio0_a5, // 17, 1.8v inout ft_gpio0_a6, // 16, 1.8v @@ -68,7 +70,7 @@ module top( inout gpio0_a2, // 84, 3.3v inout gpio1_b7, // 81, 3.3v inout gpio0_b6, // 80, 3.3v - inout gpio0_b7 // 79, 3.3v + inout gpio0_b7 // 79, 3.3v ); // can0 1.8v <-> 3.3v @@ -140,7 +142,7 @@ always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0) // time domain crossing. reg [3:0] ctr_cnt_q, cmd_b, cmd_q, cmd_val; always @(posedge clk_33m) begin - ctr_cnt_q <= ctr_cnt; + ctr_cnt_q <= ctr_cnt; cmd_b <= ctr_cnt_q; cmd_q <= cmd_b; @@ -159,10 +161,10 @@ key_delay #(.debound(10'd50)) reset_key( reg power_on = 1'b0; -localparam CPU_STATE_IDLE = 2'b00, +localparam CPU_STATE_IDLE = 2'b00, CPU_STATE_RUN = 2'b01, CPU_STATE_RST = 2'b10; - + reg [1:0] state = CPU_STATE_IDLE; // cpu state transition always @(posedge clk_33m) @@ -219,23 +221,22 @@ always @(posedge clk_1k) begin 12'd1: pwr_3v3_en <= 1'b1; 12'd100: begin pwr_1v2_en <= 1'b1; - pwr_2v5_en <= 1'b1; + //pwr_2v5_en <= 1'b1; end 12'd130: pwr_0v8_en <= 1'b1; 12'd160: pwr_1v8_en <= 1'b1; 12'd270: begin - pcierst <= 4'hf; nvme_rst_n <= 1'b1; end 12'd290: begin ft_por <= 1; - power_on <= 1; + power_on <= 1; end + endcase end else begin case (mills_count) 12'd10: begin - pcierst <= 4'h0; nvme_rst_n <= 1'b0; ft_por <= 1'b0; end @@ -243,13 +244,17 @@ always @(posedge clk_1k) begin 12'd140: pwr_0v8_en <= 1'b0; 12'd160: begin pwr_1v2_en <= 1'b0; - pwr_2v5_en <= 1'b0; + // pwr_2v5_en <= 1'b0; end 12'd310: pwr_3v3_en <= 1'b0; 12'd1000: power_on <= 1'b0; + endcase end end +assign pwr_2v5_en = pwr_1v2_en; +assign pcierst = {4{nvme_rst_n}}; + endmodule diff --git a/src/key_delay.v b/src/key_delay.v index e948c13..81411db 100644 --- a/src/key_delay.v +++ b/src/key_delay.v @@ -1,19 +1,19 @@ -module key_delay #(parameter debound = 10'd30) ( - input keypin ,// switch pin - input clk_1K ,// 1ms period - output reg keyout // if key on out 1 -); - reg [9:0] keystate = 0; - - always @(posedge clk_1K) - if (!keypin) - keystate = keystate + 1'b1; - else - keystate = 0; - - always @(posedge clk_1K) - if (keystate >= debound) - keyout = 1; // default 30ms key on, if have 30 times 1, can ensure key on, and output 1 - else - keyout = 0; -endmodule +module key_delay #(parameter debound = 10'd30) ( + input keypin ,// switch pin + input clk_1K ,// 1ms period + output reg keyout // if key on out 1 +); + reg [9:0] keystate = 0; + + always @(posedge clk_1K) + if (!keypin) + keystate = keystate + 1'b1; + else + keystate = 0; + + always @(posedge clk_1K) + if (keystate >= debound) + keyout = 1; // default 30ms key on, if have 30 times 1, can ensure key on, and output 1 + else + keyout = 0; +endmodule