fix warnings

Signed-off-by: surenyi <surenyi82@163.com>

ft2004.sty

@@ -17,9 +17,9 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
-[synthesis-type]
-tool=Synplify
 [STRATEGY-LIST]
 Normal=True, 1595388407
 [TOUCHED-REPORT]
 Design.bl5File=1595811534
+[synthesis-type]
+tool=Synplify

src/ft2004_top.v

@@ -5,23 +5,25 @@
 
 //////////////////////////////////////////////////////////////////////////////////
 module top(
-    input clk_33m,             //88, 33M, 30NS
-    input por_rst,             //73 active low
-    input sys_rst_in,          //72 active low
-    input ft_pwr_ctl0,         //97
-    input ft_pwr_ctl1,         //98
-
-    output reg pwr_0v8_en,     //41
-    output reg pwr_1v2_en,     //42
-    output reg pwr_1v8_en,     //43
-    output reg pwr_2v5_en,     //44
-    output reg pwr_3v3_en,     //47
-    output reg [3:0] pcierst,  //bit0: 48~49~50~53 bit4 active low
-    output reg nvme_rst_n,     //54 active low
-    output reg ft_por,	       //94
-    output reg gpio0_a1,       //92
-    
-    output reg run_led_n,      //56
+    input clk_33m,          //88, 33M, 30NS
+    input por_rst,          //73 active low
+    input sys_rst_in,       //72 active low
+    input ft_pwr_ctl0,      //97
+    input ft_pwr_ctl1,      //98
+
+    output reg pwr_0v8_en,  //41
+    output reg pwr_1v2_en,  //42
+    output reg pwr_1v8_en,  //43
+    output     pwr_2v5_en,  //44
+    output reg pwr_3v3_en,  //47
+    output [3:0] pcierst,  //bit0: 48~49~50~53 bit4 active low
+
+
+    output reg nvme_rst_n, //54 active low
+    output reg ft_por,	   //94
+    output reg gpio0_a1,   //92
+
+    output reg run_led_n,  //56
 
     // can0
     input  ft_can_txd0,    // 3, 1.8v
@@ -140,7 +142,7 @@ always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0)
 // time domain crossing.
 reg [3:0] ctr_cnt_q, cmd_b, cmd_q, cmd_val;
 always @(posedge clk_33m) begin
-	ctr_cnt_q <= ctr_cnt;
+    ctr_cnt_q <= ctr_cnt;
     cmd_b     <= ctr_cnt_q;
     cmd_q     <= cmd_b;
 
@@ -219,23 +221,22 @@ always @(posedge clk_1k) begin
             12'd1:  pwr_3v3_en <= 1'b1;
             12'd100: begin
                 pwr_1v2_en   <= 1'b1;
-                pwr_2v5_en   <= 1'b1;
+                //pwr_2v5_en   <= 1'b1;
             end
             12'd130: pwr_0v8_en  <= 1'b1;
             12'd160: pwr_1v8_en  <= 1'b1;
             12'd270: begin
-                pcierst     <= 4'hf;
                 nvme_rst_n  <= 1'b1;
             end
             12'd290: begin
                 ft_por   <= 1;
                 power_on <= 1;
             end
+
         endcase
     end else begin
         case (mills_count)
             12'd10: begin
-                pcierst     <= 4'h0;
                 nvme_rst_n  <= 1'b0;
                 ft_por      <= 1'b0;
             end
@@ -243,13 +244,17 @@ always @(posedge clk_1k) begin
             12'd140: pwr_0v8_en <= 1'b0;
             12'd160: begin
                 pwr_1v2_en <= 1'b0;
-                pwr_2v5_en <= 1'b0;
+               // pwr_2v5_en <= 1'b0;
             end
             12'd310: pwr_3v3_en <= 1'b0;
             12'd1000: power_on  <= 1'b0;
+
         endcase
     end
 end
 
+assign   pwr_2v5_en = pwr_1v2_en;
+assign   pcierst    = {4{nvme_rst_n}};
+
 endmodule