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update src/ft2004_top.v 

Signed-off-by: surenyi <surenyi82@163.com>
master
surenyi 4 years ago
parent
986670605b
commit
1ea1c97432
4 changed files with 86 additions and 52 deletions
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  1. 8
      ft2004.lci
  2. 8
      ft2004.lct
  3. 8
      ft2004.sty
  4. 114
      src/ft2004_top.v

8
ft2004.lci
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = No;
[Revision]
Parent = lc4k128v.lci;
DATE = 07/23/2020;
TIME = 17:33:57;
DATE = 07/24/2020;
TIME = 12:01:05;
Source_Format = Pure_Verilog_HDL;
Synthesis = Synplify;
@ -80,6 +80,9 @@ gpio0_b7 = Pin, 79, -, H, 12;
gpio1_a4 = Pin, 71, -, G, 4;
gpio1_b7 = Pin, 81, -, H, 8;
por_rst = Pin, 73, -, -, -;
sys_rst_in = Pin, 72, -, G, 2;
ft_gpio0_a3 = Pin, 99, -, A, 12;
ft_gpio1_a3 = Pin, 20, -, C, 5;
[Group Assignments]
layer = OFF;
@ -135,6 +138,7 @@ gpio0_b7 = LVCMOS33, PIN, 1, -;
gpio1_a4 = LVCMOS33, PIN, 1, -;
gpio1_b7 = LVCMOS33, PIN, 1, -;
por_rst = LVCMOS33, PIN, 1, -;
sys_rst_in = LVCMOS33, PIN, 1, -;
[Pullup]

8
ft2004.lct
View File

@ -12,8 +12,8 @@ EN_PinMacrocell = No;
[Revision]
Parent = lc4k128v.lci;
DATE = 07/23/2020;
TIME = 17:33:57;
DATE = 07/24/2020;
TIME = 12:01:05;
Source_Format = Pure_Verilog_HDL;
Synthesis = Synplify;
@ -80,6 +80,9 @@ gpio0_b7 = Pin, 79, -, H, 12;
gpio1_a4 = Pin, 71, -, G, 4;
gpio1_b7 = Pin, 81, -, H, 8;
por_rst = Pin, 73, -, -, -;
sys_rst_in = Pin, 72, -, G, 2;
ft_gpio0_a3 = Pin, 99, -, A, 12;
ft_gpio1_a3 = Pin, 20, -, C, 5;
[Group Assignments]
layer = OFF;
@ -135,6 +138,7 @@ gpio0_b7 = LVCMOS33, PIN, 1, -;
gpio1_a4 = LVCMOS33, PIN, 1, -;
gpio1_b7 = LVCMOS33, PIN, 1, -;
por_rst = LVCMOS33, PIN, 1, -;
sys_rst_in = LVCMOS33, PIN, 1, -;
[Pullup]

8
ft2004.sty
View File

@ -2,7 +2,7 @@
synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,
_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,
_EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
_EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
@ -17,9 +17,7 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
_EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
[synthesis-type]
tool=Synplify
[STRATEGY-LIST]
Normal=True, 1595388407
[TOUCHED-REPORT]
Design.bl5File=1595496837
[synthesis-type]
tool=Synplify

114
src/ft2004_top.v
View File

@ -7,7 +7,7 @@
module top(
input clk_33m, //88, 33M, 30NS
input por_rst, //73 active low
input sys_rst_in, //72 active low
input ft_pwr_ctl0, //97
input ft_pwr_ctl1, //98
@ -50,6 +50,9 @@ module top(
inout i2c_sda3, // 61, 3.3v
// gpio0
input ft_gpio0_a3, // 99, 1.8v reserved
input ft_gpio1_a3, // 20, 1.8v reserved
inout ft_gpio1_a4, // 19, 1.8v
inout ft_gpio0_a5, // 17, 1.8v
inout ft_gpio0_a6, // 16, 1.8v
@ -84,16 +87,21 @@ assign spi1_csn3 = ft_spi1_csn3;
// XXX: sda line maybe work incorrectly.
// need to be fixed ?
assign i2c_scl3 = ft_i2c_scl3;
// XXX: sda line can't work as bidirectiono
assign i2c_sda3 = ft_i2c_sda3;
// gpio 1.8v <-> 3.3v
// XXX: inout maybe errors, it only works one direction,
// need to be fixed ?
assign ft_gpio0_a2 = ft_gpio0_a3 == 1'b1 ? gpio0_a2 : 1'bZ;
assign gpio0_a2 = ft_gpio0_a3 == 1'b0 ? ft_gpio0_a2 : 1'bZ;
assign ft_gpio0_a4 = ft_gpio1_a3 == 1'b1 ? gpio0_a4 : 1'bZ;
assign gpio0_a4 = ft_gpio1_a3 == 1'b0 ? ft_gpio0_a4 : 1'bZ;
assign gpio1_a4 = ft_gpio1_a4;
assign gpio0_a5 = ft_gpio0_a5;
assign gpio0_a6 = ft_gpio0_a6;
assign gpio0_a4 = ft_gpio0_a4;
assign ft_gpio0_a2 = gpio0_a2;
assign gpio1_b7 = ft_gpio1_b7;
assign gpio0_b6 = ft_gpio0_b6;
assign gpio0_b7 = ft_gpio0_b7;
@ -101,23 +109,27 @@ assign gpio0_b7 = ft_gpio0_b7;
reg clk_1k = 1'b0;
// divide to 1K clock
reg [15:0] unit_1ms_count = 16'd0;
reg [14:0] unit_1ms_count = 15'd0;
always @(posedge clk_33m)
if (unit_1ms_count == 16499) begin
if (unit_1ms_count == 15'd16499) begin
clk_1k <= ~clk_1k;
unit_1ms_count <= 0;
end else
unit_1ms_count <= unit_1ms_count + 1'b1;
// 16bits 1ms timer
reg tim_en = 1'b0;
reg [15:0] msclk_count;
// 12bits 1ms timer
reg tim_en = 1'b0;
reg tim_run = 1'b0;
reg [11:0] msclk_count;
always @(posedge clk_1k) begin
if (!tim_en)
msclk_count <= 16'd0;
else
if (!tim_en) begin
msclk_count <= 12'd0;
tim_run <= 1'b0;
end else begin
msclk_count <= msclk_count + 1'd1;
tim_run <= 1'b1;
end
end
// sample PWR_CTR1 clock ticks.
@ -128,67 +140,83 @@ always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0)
else
pr_count <= pr_count + 1'b1;
reg [3:0] cycle_a, cycle_b, cmd_val;
always @(posedge clk_1k) begin
reg [3:0] cmd_val_b, cmd_val;
always @(posedge clk_33m) begin
if (cpu_state == CPU_STATE_RUN) begin
cycle_a <= pr_count;
cycle_b <= cycle_a;
cmd_val <= cycle_b;
cmd_val_b <= pr_count;
cmd_val <= cmd_val_b;
end else begin
cycle_a <= 4'h0;
cycle_b <= 4'h0;
cmd_val <= 4'h0;
cmd_val_b <= 4'h0;
cmd_val <= 4'h0;
end
end
// reset key detection
wire rst_key;
key_delay reset_key(
.keypin(por_rst),
.keypin(por_rst & sys_rst_in),
.clk_1K(clk_1k),
.keyout(rst_key));
reg power_on = 1'b0;
localparam CPU_STATE_IDLE = 0, CPU_STATE_PWR = 1, CPU_STATE_RUN = 2, CPU_STATE_RST = 3;
reg [3:0] cpu_state = CPU_STATE_IDLE;
always @(posedge clk_1k) begin
localparam CPU_STATE_IDLE = 0, CPU_STATE_PRE_PWR = 1, CPU_STATE_PWR = 2, CPU_STATE_POST_PWR = 3,
CPU_STATE_RUN = 4, CPU_STATE_PRE_RST = 5, CPU_STATE_RST = 6, CPU_STATE_POST_RST = 7;
reg [2:0] cpu_state = CPU_STATE_IDLE;
always @(posedge clk_33m) begin
case (cpu_state)
CPU_STATE_IDLE: begin
tim_en <= 1'b1;
gpio0_a1 <= 1'b0;
run_led_n <= 1'b1;
cpu_state <= CPU_STATE_PWR;
cpu_state <= CPU_STATE_PRE_PWR;
end
CPU_STATE_PRE_PWR: begin
if (tim_run) cpu_state <= CPU_STATE_PWR;
end
CPU_STATE_PWR: begin
if (power_on) begin
tim_en <= 0;
cpu_state <= CPU_STATE_RUN;
cpu_state <= CPU_STATE_POST_PWR;
end
end
CPU_STATE_POST_PWR: begin
if (!tim_run) cpu_state <= CPU_STATE_RUN;
end
CPU_STATE_RUN: begin
if (!rst_key) begin // reset button pressed
tim_en <= 1'b1;
cpu_state <= CPU_STATE_RST;
cpu_state <= CPU_STATE_PRE_RST;
end else
case (cmd_val)
4'b0001: begin // bios booting
4'b0001: begin // bios booting: S3_OK_Clear
gpio0_a1 <= 1'b1;
run_led_n <= 1'b0;
end
4'b0100: begin // system reset
cpu_state <= CPU_STATE_RST;
4'b0100: begin // system reset: reboot
cpu_state <= CPU_STATE_PRE_RST;
tim_en <= 1'b1;
end
//4'b1000: //S0->S3
//4'b1100: //S0->S5
endcase
end
CPU_STATE_PRE_RST: begin
if (tim_run) cpu_state <= CPU_STATE_RST;
end
CPU_STATE_RST: begin
if (!power_on) begin
tim_en <= 1'b0;
run_led_n <= 1;
cpu_state <= CPU_STATE_IDLE;
cpu_state <= CPU_STATE_POST_RST;
end
end
CPU_STATE_POST_RST: begin
if (!tim_run) cpu_state <= CPU_STATE_IDLE;
end
default: cpu_state <= cpu_state;
endcase
end
@ -199,37 +227,37 @@ end
always @(posedge clk_1k) begin
if (!power_on) begin
case(msclk_count)
16'd1: pwr_3v3_en <= 1;
16'd100: begin
12'd1: pwr_3v3_en <= 1;
12'd100: begin
pwr_1v2_en <= 1;
pwr_2v5_en <= 1;
end
16'd130: pwr_0v8_en <= 1;
16'd160: pwr_1v8_en <= 1;
16'd270: begin
12'd130: pwr_0v8_en <= 1;
12'd160: pwr_1v8_en <= 1;
12'd270: begin
pcierst <= 4'hf;
nvme_rst_n <= 1'b1;
end
16'd290: begin
12'd290: begin
ft_por <= 1;
power_on <= 1;
end
endcase
end else begin
case (msclk_count)
16'd10: begin
12'd10: begin
pcierst <= 4'h0;
nvme_rst_n <= 1'b0;
ft_por <= 1'b0;
end
16'd120: pwr_1v8_en <= 1'b0;
16'd140: pwr_0v8_en <= 1'b0;
16'd160: begin
12'd120: pwr_1v8_en <= 1'b0;
12'd140: pwr_0v8_en <= 1'b0;
12'd160: begin
pwr_1v2_en <= 1'b0;
pwr_2v5_en <= 1'b0;
end
16'd310: pwr_3v3_en <= 1'b0;
16'd1000: power_on <= 1'b0;
12'd310: pwr_3v3_en <= 1'b0;
12'd1000: power_on <= 1'b0;
endcase
end
end

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