update constraints

Signed-off-by: surenyi <surenyi82@163.com>

ft2004.lci

@@ -12,8 +12,8 @@ EN_PinMacrocell = No;
 
 [Revision]
 Parent = lc4k128v.lci;
-DATE = 07/26/2020;
+DATE = 07/27/2020;
-TIME = 08:15:40;
+TIME = 08:58:54;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -28,8 +28,8 @@ Clock_enable_optimization = Auto;
 Max_fanin_limit = 28;
 Nodes_collapsing_mode = Fmax;
 Logic_optimization_effort = 3;
-Balanced_partitioning = No;
+Balanced_partitioning = Yes;
-Fitter_effort_level = Medium;
+Fitter_effort_level = Low;
 
 [Location Assignments]
 layer = OFF;

ft2004.lct

@@ -12,8 +12,8 @@ EN_PinMacrocell = No;
 
 [Revision]
 Parent = lc4k128v.lci;
-DATE = 07/26/2020;
+DATE = 07/27/2020;
-TIME = 08:15:40;
+TIME = 08:58:54;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -28,8 +28,8 @@ Clock_enable_optimization = Auto;
 Max_fanin_limit = 28;
 Nodes_collapsing_mode = Fmax;
 Logic_optimization_effort = 3;
-Balanced_partitioning = No;
+Balanced_partitioning = Yes;
-Fitter_effort_level = Medium;
+Fitter_effort_level = Low;
 
 [Location Assignments]
 layer = OFF;

ft2004.sty

@@ -17,7 +17,9 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
-[STRATEGY-LIST]
-Normal=True, 1595388407
 [synthesis-type]
 tool=Synplify
+[STRATEGY-LIST]
+Normal=True, 1595388407
+[TOUCHED-REPORT]
+Design.bl5File=1595811534

src/ft2004_top.v

@@ -152,7 +152,7 @@ end
 
 // reset key detection
 wire rst_key;
-key_delay #(.debound(50)) reset_key(
+key_delay #(.debound(10'd50)) reset_key(
     .keypin(por_rst & sys_rst_in),
     .clk_1K(clk_1k),
     .keyout(rst_key)); // reset key pressed, output 1, otherwise output 0.
@@ -216,13 +216,13 @@ always @(posedge clk_33m)
 always @(posedge clk_1k) begin
     if (!power_on) begin
         case(mills_count)
-            12'd1:  pwr_3v3_en <= 1;
+            12'd1:  pwr_3v3_en <= 1'b1;
             12'd100: begin
-                pwr_1v2_en   <= 1;
+                pwr_1v2_en   <= 1'b1;
-                pwr_2v5_en   <= 1;
+                pwr_2v5_en   <= 1'b1;
             end
-            12'd130: pwr_0v8_en  <= 1;
+            12'd130: pwr_0v8_en  <= 1'b1;
-            12'd160: pwr_1v8_en  <= 1;
+            12'd160: pwr_1v8_en  <= 1'b1;
             12'd270: begin
                 pcierst     <= 4'hf;
                 nvme_rst_n  <= 1'b1;

src/key_delay.v

@@ -1,4 +1,4 @@
-module key_delay #(parameter debound = 30) (
+module key_delay #(parameter debound = 10'd30) (
     input keypin      ,// switch pin
     input clk_1K      ,// 1ms period
     output reg keyout  // if key on out 1