From 710a19ff44187c9893e362e00913339c1f4208a6 Mon Sep 17 00:00:00 2001 From: surenyi Date: Thu, 23 Jul 2020 12:33:37 +0800 Subject: [PATCH] reset key working, wire level converted signals Signed-off-by: surenyi --- ft2004.lci | 87 ++++++++++++-- ft2004.lct | 87 ++++++++++++-- ft2004.sty | 4 +- ft2004.syn | 1 + ft2004_top.jhd | 4 + src/ft2004_top.v | 301 +++++++++++++++++++++++++++++------------------ src/key_delay.v | 22 ++++ 7 files changed, 371 insertions(+), 135 deletions(-) create mode 100644 src/key_delay.v diff --git a/ft2004.lci b/ft2004.lci index 1f333b8..af3694d 100644 --- a/ft2004.lci +++ b/ft2004.lci @@ -7,13 +7,13 @@ PartType = LC4128V; Speed = -10; Operating_condition = IND; Status = Production; -EN_PinGLB = yes; -EN_PinMacrocell = yes; +EN_PinGLB = No; +EN_PinMacrocell = No; [Revision] Parent = lc4k128v.lci; -DATE = 07/22/2020; -TIME = 19:02:52; +DATE = 07/23/2020; +TIME = 12:07:46; Source_Format = Pure_Verilog_HDL; Synthesis = Synplify; @@ -34,15 +34,52 @@ pwr_1v2_en = Pin, 42, -, E, 2; pwr_1v8_en = Pin, 43, -, E, 4; pwr_2v5_en = Pin, 44, -, E, 6; pwr_3v3_en = Pin, 47, -, E, 8; -rst_done_led = Pin, 56, -, F, 6; ft_pwr_ctl0 = Pin, 97, -, A, 8; ft_pwr_ctl1 = Pin, 98, -, A, 10; pcierst_0_ = Pin, 48, -, E, 10; pcierst_1_ = Pin, 49, -, E, 12; pcierst_2_ = Pin, 50, -, E, 14; pcierst_3_ = Pin, 53, -, F, 0; -pcierst_4_ = Pin, 54, -, F, 2; -cpld_clk_33M = Pin, 88, -, -, -; +nvme_rst_n = Pin, 54, -, F, 2; +run_led_n = Pin, 56, -, F, 6; +clk_33m = Pin, 88, -, -, -; +can_rx0 = Pin, 58, -, F, 8; +ft_can_txd0 = Pin, 3, -, B, 0; +can_tx0 = Pin, 59, -, F, 10; +ft_can_rxd0 = Pin, 4, -, B, 2; +ft_i2c_scl3 = Pin, 10, -, B, 12; +ft_spi0_csn0 = Pin, 9, -, B, 10; +ft_spi0_sck = Pin, 5, -, B, 4; +ft_spi0_si = Pin, 8, -, B, 8; +spi0_so = Pin, 69, -, G, 6; +ft_spi0_so = Pin, 6, -, B, 6; +i2c_scl3 = Pin, 60, -, F, 12; +spi0_csn0 = Pin, 66, -, G, 10; +spi0_sck = Pin, 70, -, G, 5; +spi0_si = Pin, 67, -, G, 8; +ft_i2c_sda3 = Pin, 11, -, B, 13; +i2c_sda3 = Pin, 61, -, F, 13; +ft_spi0_csn3 = Pin, 21, -, C, 4; +ft_spi1_csn3 = Pin, 22, -, C, 2; +spi0_csn3 = Pin, 65, -, G, 12; +spi1_csn3 = Pin, 64, -, G, 14; +ft_gpio0_a2 = Pin, 12, 0, -, -; +ft_gpio0_a4 = Pin, 15, -, C, 12; +ft_gpio0_a5 = Pin, 17, -, C, 8; +ft_gpio0_a6 = Pin, 16, -, C, 10; +ft_gpio0_b6 = Pin, 36, -, D, 2; +ft_gpio0_b7 = Pin, 35, -, D, 4; +ft_gpio1_a4 = Pin, 19, -, C, 6; +ft_gpio1_b7 = Pin, 37, -, D, 0; +gpio0_a2 = Pin, 84, -, H, 6; +gpio0_a4 = Pin, 85, -, H, 4; +gpio0_a5 = Pin, 87, -, H, 0; +gpio0_a6 = Pin, 86, -, H, 2; +gpio0_b6 = Pin, 80, -, H, 10; +gpio0_b7 = Pin, 79, -, H, 12; +gpio1_a4 = Pin, 71, -, G, 4; +gpio1_b7 = Pin, 81, -, H, 8; +por_rst = Pin, 73, -, -, -; [Group Assignments] layer = OFF; @@ -67,6 +104,37 @@ NetList = VERILOG; [IO Types] layer = OFF; +pwr_0v8_en = LVCMOS33, PIN, 1, -; +pwr_1v2_en = LVCMOS33, PIN, 1, -; +pwr_1v8_en = LVCMOS33, PIN, 1, -; +pwr_2v5_en = LVCMOS33, PIN, 1, -; +pwr_3v3_en = LVCMOS33, PIN, 1, -; +pcierst_0_ = LVCMOS33, PIN, 1, -; +pcierst_1_ = LVCMOS33, PIN, 1, -; +pcierst_2_ = LVCMOS33, PIN, 1, -; +pcierst_3_ = LVCMOS33, PIN, 1, -; +nvme_rst_n = LVCMOS33, PIN, 1, -; +spi0_csn0 = LVCMOS33, PIN, 1, -; +spi0_csn3 = LVCMOS33, PIN, 1, -; +spi1_csn3 = LVCMOS33, PIN, 1, -; +run_led_n = LVCMOS33, PIN, 1, -; +can_tx0 = LVCMOS33, PIN, 1, -; +i2c_scl3 = LVCMOS33_OD, PIN, 1, -; +spi0_si = LVCMOS33, PIN, 1, -; +can_rx0 = LVCMOS33, PIN, 1, -; +spi0_so = LVCMOS33, PIN, 1, -; +spi0_sck = LVCMOS33, PIN, 1, -; +ft_i2c_sda3 = LVCMOS18, PIN, 0, -; +i2c_sda3 = LVCMOS33_OD, PIN, 1, -; +gpio0_a2 = LVCMOS33, PIN, 1, -; +gpio0_a4 = LVCMOS33, PIN, 1, -; +gpio0_a5 = LVCMOS33, PIN, 1, -; +gpio0_a6 = LVCMOS33, PIN, 1, -; +gpio0_b6 = LVCMOS33, PIN, 1, -; +gpio0_b7 = LVCMOS33, PIN, 1, -; +gpio1_a4 = LVCMOS33, PIN, 1, -; +gpio1_b7 = LVCMOS33, PIN, 1, -; +por_rst = LVCMOS33, PIN, 1, -; [Pullup] @@ -76,6 +144,7 @@ layer = OFF; [Timing Constraints] layer = OFF; +fMAX_0 = 30.3030, clk_33m, clk_33m; [HSI Attributes] @@ -129,7 +198,9 @@ layer = OFF; [Register Powerup] RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en, - rst_done_led, pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, pcierst_4_; + pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, nvme_rst_n, spi0_csn0, + spi0_csn3, spi1_csn3; +SET = run_led_n, can_tx0, ft_can_rxd0, ft_spi0_so, i2c_scl3, spi0_si; [Constraint Version] version = 1.0; diff --git a/ft2004.lct b/ft2004.lct index 1f333b8..af3694d 100644 --- a/ft2004.lct +++ b/ft2004.lct @@ -7,13 +7,13 @@ PartType = LC4128V; Speed = -10; Operating_condition = IND; Status = Production; -EN_PinGLB = yes; -EN_PinMacrocell = yes; +EN_PinGLB = No; +EN_PinMacrocell = No; [Revision] Parent = lc4k128v.lci; -DATE = 07/22/2020; -TIME = 19:02:52; +DATE = 07/23/2020; +TIME = 12:07:46; Source_Format = Pure_Verilog_HDL; Synthesis = Synplify; @@ -34,15 +34,52 @@ pwr_1v2_en = Pin, 42, -, E, 2; pwr_1v8_en = Pin, 43, -, E, 4; pwr_2v5_en = Pin, 44, -, E, 6; pwr_3v3_en = Pin, 47, -, E, 8; -rst_done_led = Pin, 56, -, F, 6; ft_pwr_ctl0 = Pin, 97, -, A, 8; ft_pwr_ctl1 = Pin, 98, -, A, 10; pcierst_0_ = Pin, 48, -, E, 10; pcierst_1_ = Pin, 49, -, E, 12; pcierst_2_ = Pin, 50, -, E, 14; pcierst_3_ = Pin, 53, -, F, 0; -pcierst_4_ = Pin, 54, -, F, 2; -cpld_clk_33M = Pin, 88, -, -, -; +nvme_rst_n = Pin, 54, -, F, 2; +run_led_n = Pin, 56, -, F, 6; +clk_33m = Pin, 88, -, -, -; +can_rx0 = Pin, 58, -, F, 8; +ft_can_txd0 = Pin, 3, -, B, 0; +can_tx0 = Pin, 59, -, F, 10; +ft_can_rxd0 = Pin, 4, -, B, 2; +ft_i2c_scl3 = Pin, 10, -, B, 12; +ft_spi0_csn0 = Pin, 9, -, B, 10; +ft_spi0_sck = Pin, 5, -, B, 4; +ft_spi0_si = Pin, 8, -, B, 8; +spi0_so = Pin, 69, -, G, 6; +ft_spi0_so = Pin, 6, -, B, 6; +i2c_scl3 = Pin, 60, -, F, 12; +spi0_csn0 = Pin, 66, -, G, 10; +spi0_sck = Pin, 70, -, G, 5; +spi0_si = Pin, 67, -, G, 8; +ft_i2c_sda3 = Pin, 11, -, B, 13; +i2c_sda3 = Pin, 61, -, F, 13; +ft_spi0_csn3 = Pin, 21, -, C, 4; +ft_spi1_csn3 = Pin, 22, -, C, 2; +spi0_csn3 = Pin, 65, -, G, 12; +spi1_csn3 = Pin, 64, -, G, 14; +ft_gpio0_a2 = Pin, 12, 0, -, -; +ft_gpio0_a4 = Pin, 15, -, C, 12; +ft_gpio0_a5 = Pin, 17, -, C, 8; +ft_gpio0_a6 = Pin, 16, -, C, 10; +ft_gpio0_b6 = Pin, 36, -, D, 2; +ft_gpio0_b7 = Pin, 35, -, D, 4; +ft_gpio1_a4 = Pin, 19, -, C, 6; +ft_gpio1_b7 = Pin, 37, -, D, 0; +gpio0_a2 = Pin, 84, -, H, 6; +gpio0_a4 = Pin, 85, -, H, 4; +gpio0_a5 = Pin, 87, -, H, 0; +gpio0_a6 = Pin, 86, -, H, 2; +gpio0_b6 = Pin, 80, -, H, 10; +gpio0_b7 = Pin, 79, -, H, 12; +gpio1_a4 = Pin, 71, -, G, 4; +gpio1_b7 = Pin, 81, -, H, 8; +por_rst = Pin, 73, -, -, -; [Group Assignments] layer = OFF; @@ -67,6 +104,37 @@ NetList = VERILOG; [IO Types] layer = OFF; +pwr_0v8_en = LVCMOS33, PIN, 1, -; +pwr_1v2_en = LVCMOS33, PIN, 1, -; +pwr_1v8_en = LVCMOS33, PIN, 1, -; +pwr_2v5_en = LVCMOS33, PIN, 1, -; +pwr_3v3_en = LVCMOS33, PIN, 1, -; +pcierst_0_ = LVCMOS33, PIN, 1, -; +pcierst_1_ = LVCMOS33, PIN, 1, -; +pcierst_2_ = LVCMOS33, PIN, 1, -; +pcierst_3_ = LVCMOS33, PIN, 1, -; +nvme_rst_n = LVCMOS33, PIN, 1, -; +spi0_csn0 = LVCMOS33, PIN, 1, -; +spi0_csn3 = LVCMOS33, PIN, 1, -; +spi1_csn3 = LVCMOS33, PIN, 1, -; +run_led_n = LVCMOS33, PIN, 1, -; +can_tx0 = LVCMOS33, PIN, 1, -; +i2c_scl3 = LVCMOS33_OD, PIN, 1, -; +spi0_si = LVCMOS33, PIN, 1, -; +can_rx0 = LVCMOS33, PIN, 1, -; +spi0_so = LVCMOS33, PIN, 1, -; +spi0_sck = LVCMOS33, PIN, 1, -; +ft_i2c_sda3 = LVCMOS18, PIN, 0, -; +i2c_sda3 = LVCMOS33_OD, PIN, 1, -; +gpio0_a2 = LVCMOS33, PIN, 1, -; +gpio0_a4 = LVCMOS33, PIN, 1, -; +gpio0_a5 = LVCMOS33, PIN, 1, -; +gpio0_a6 = LVCMOS33, PIN, 1, -; +gpio0_b6 = LVCMOS33, PIN, 1, -; +gpio0_b7 = LVCMOS33, PIN, 1, -; +gpio1_a4 = LVCMOS33, PIN, 1, -; +gpio1_b7 = LVCMOS33, PIN, 1, -; +por_rst = LVCMOS33, PIN, 1, -; [Pullup] @@ -76,6 +144,7 @@ layer = OFF; [Timing Constraints] layer = OFF; +fMAX_0 = 30.3030, clk_33m, clk_33m; [HSI Attributes] @@ -129,7 +198,9 @@ layer = OFF; [Register Powerup] RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en, - rst_done_led, pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, pcierst_4_; + pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, nvme_rst_n, spi0_csn0, + spi0_csn3, spi1_csn3; +SET = run_led_n, can_tx0, ft_can_rxd0, ft_spi0_so, i2c_scl3, spi0_si; [Constraint Version] version = 1.0; diff --git a/ft2004.sty b/ft2004.sty index 120eb66..c9c2f6b 100644 --- a/ft2004.sty +++ b/ft2004.sty @@ -2,7 +2,7 @@ synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes _vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True _EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200 -_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0, +_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0, _EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True _EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20 _EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16 @@ -19,7 +19,5 @@ _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False [STRATEGY-LIST] Normal=True, 1595388407 -[TOUCHED-REPORT] -Design.bl5File=1595415772 [synthesis-type] tool=Synplify diff --git a/ft2004.syn b/ft2004.syn index 3485e4e..f88199d 100644 --- a/ft2004.syn +++ b/ft2004.syn @@ -5,6 +5,7 @@ DESIGN ft2004 Normal DEVKIT LC4128V-10T100I ENTRY Pure Verilog HDL MODULE .\src\ft2004_top.v +MODSTYLE key_delay Normal MODSTYLE top Normal SYNTHESIS_TOOL Synplify SIMULATOR_TOOL ActiveHDL diff --git a/ft2004_top.jhd b/ft2004_top.jhd index ffda430..2b40f44 100644 --- a/ft2004_top.jhd +++ b/ft2004_top.jhd @@ -1 +1,5 @@ MODULE top DEFIN .\src\ft2004_top.v + SUBMODULE key_delay + INSTANCE reset_key +MODULE key_delay DEFIN .\src\key_delay.v +DEPEND INCLUDED_FILE .\src\key_delay.v diff --git a/src/ft2004_top.v b/src/ft2004_top.v index 0d418d6..c2aaa80 100644 --- a/src/ft2004_top.v +++ b/src/ft2004_top.v @@ -1,166 +1,235 @@ `timescale 1ns / 1ps +// key debounce +`include "key_delay.v" + ////////////////////////////////////////////////////////////////////////////////// module top( - input cpld_clk_33M, //88, 33M, 30NS - input por_rst, //low_effect, 73 + input clk_33m, //88, 33M, 30NS + input por_rst, //73 active low input ft_pwr_ctl0, //97 input ft_pwr_ctl1, //98 - output pwr_0v8_en, //41 - output pwr_1v2_en, //42 - output pwr_1v8_en, //43 - output pwr_2v5_en, //44 - output pwr_3v3_en, //47 - output [4:0] pcierst, //bit0: 48~49~50~53 ~54:bit4 - output ft_por, //94 - output rst_done_led, //56 - output gpio0_a1 //92 + output reg pwr_0v8_en, //41 + output reg pwr_1v2_en, //42 + output reg pwr_1v8_en, //43 + output reg pwr_2v5_en, //44 + output reg pwr_3v3_en, //47 + output reg [3:0] pcierst, //bit0: 48~49~50~53 bit4 active low + output reg nvme_rst_n, //54 active low + output reg ft_por, //94 + output reg gpio0_a1, //92 + + output reg run_led_n, //56 + + // can0 + input ft_can_txd0, // 3, 1.8v + output ft_can_rxd0, // 4, 1.8v + input can_rx0, // 58, 3.3v + output can_tx0, // 59, 3.3v + + // spi0 + input ft_spi0_sck, // 5, 1.8v + output ft_spi0_so, // 6, 1.8v + input ft_spi0_si, // 8, 1.8v + input ft_spi0_csn0, // 9, 1.8v + output spi0_sck, // 70, 3.3v + input spi0_so, // 69, 3.3v + output spi0_si, // 67, 3.3v + output spi0_csn0, // 66, 3.3v + input ft_spi0_csn3, // 21, 1.8v + input ft_spi1_csn3, // 22, 1.8v + output spi0_csn3, // 65, 3.3v + output spi1_csn3, // 64, 3.3v + + // i2c3 + input ft_i2c_scl3, // 10, 1.8v + inout ft_i2c_sda3, // 11, 1.8v + output i2c_scl3, // 60, 3.3v + inout i2c_sda3, // 61, 3.3v + + // gpio0 + inout ft_gpio1_a4, // 19, 1.8v + inout ft_gpio0_a5, // 17, 1.8v + inout ft_gpio0_a6, // 16, 1.8v + inout ft_gpio0_a4, // 15, 1.8v + inout ft_gpio0_a2, // 12, 1.8v + inout ft_gpio1_b7, // 37, 1.8v + inout ft_gpio0_b6, // 36, 1.8v + inout ft_gpio0_b7, // 35, 1.8v + inout gpio1_a4, // 71, 3.3v + inout gpio0_a5, // 87, 3.3v + inout gpio0_a6, // 86, 3.3v + inout gpio0_a4, // 85, 3.3v + inout gpio0_a2, // 84, 3.3v + inout gpio1_b7, // 81, 3.3v + inout gpio0_b6, // 80, 3.3v + inout gpio0_b7 // 79, 3.3v ); -reg pwr_0v8_en_r; -reg pwr_1v2_en_r; -reg pwr_1v8_en_r; -reg pwr_2v5_en_r; -reg pwr_3v3_en_r; -reg [4:0]pcierst_r; -reg ft_por_r; -reg rst_done_led_r; -reg gpio0_a1_r; - -assign pwr_0v8_en = pwr_0v8_en_r; -assign pwr_1v2_en = pwr_1v2_en_r; -assign pwr_1v8_en = pwr_1v8_en_r; -assign pwr_2v5_en = pwr_2v5_en_r; -assign pwr_3v3_en = pwr_3v3_en_r; -assign pcierst = pcierst_r; -assign ft_por = ft_por_r; -assign rst_done_led = rst_done_led_r; -assign gpio0_a1 = gpio0_a1_r; - -reg tick_en = 0; - -reg [15:0] uint_1ms_count; -reg [16:0] msclk_count; -reg tick_1ms; - -`define TICK_1MS 33000 - -always @(posedge cpld_clk_33M) begin - if (!tick_en) begin - uint_1ms_count <= 16'd0; - tick_1ms <= 0; - end else if (uint_1ms_count == `TICK_1MS) begin - uint_1ms_count <= 16'd0; - tick_1ms <= 1; - end else begin - uint_1ms_count <= uint_1ms_count + 1'd1; - tick_1ms <= 0; - end -end -always @(posedge cpld_clk_33M) begin - if (!tick_en) - msclk_count <= 17'd0; - else if (tick_1ms) begin +// can0 1.8v <-> 3.3v +assign can_tx0 = ft_can_txd0; +assign ft_can_rxd0 = can_rx0; + +// spi0 1.8v <-> 3.3v +assign spi0_sck = ft_spi0_sck; +assign ft_spi0_so = spi0_so; +assign spi0_si = ft_spi0_si; +assign spi0_csn0 = ft_spi0_csn0; +assign spi0_csn3 = ft_spi0_csn3; +assign spi1_csn3 = ft_spi1_csn3; + +// i2c3 1.8v <-> 3.3v +// XXX: sda line maybe work incorrectly. +// need to be fixed ? +assign i2c_scl3 = ft_i2c_scl3; +assign i2c_sda3 = ft_i2c_sda3; + +// gpio 1.8v <-> 3.3v +// XXX: inout maybe errors, it only works one direction, +// need to be fixed ? +assign gpio1_a4 = ft_gpio1_a4; +assign gpio0_a5 = ft_gpio0_a5; +assign gpio0_a6 = ft_gpio0_a6; +assign gpio0_a4 = ft_gpio0_a4; +assign gpio0_a2 = ft_gpio0_a2; +assign gpio1_b7 = ft_gpio1_b7; +assign gpio0_b6 = ft_gpio0_b6; +assign gpio0_b7 = ft_gpio0_b7; + +reg clk_1k = 1'b0; + +// divide to 1K clock +reg [15:0] unit_1ms_count = 16'd0; +always @(posedge clk_33m) + if (unit_1ms_count == 16499) begin + clk_1k <= ~clk_1k; + unit_1ms_count <= 0; + end else + unit_1ms_count <= unit_1ms_count + 1'b1; + +// 16bits 1ms timer +reg tim_en = 1'b0; +reg [15:0] msclk_count; + +always @(posedge clk_1k) begin + if (!tim_en) + msclk_count <= 16'd0; + else msclk_count <= msclk_count + 1'd1; - end end -localparam CPU_STATE_IDLE = 0, CPU_STATE_PWR = 1, CPU_STATE_RUN = 2, CPU_STATE_RST = 3; -reg [3:0] cpu_state = CPU_STATE_IDLE; - -reg power_on = 0; +// sample PWR_CTR1 clock ticks. reg [3:0] pr_count; - -always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0) begin +always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0) if (!ft_pwr_ctl0) pr_count <= 4'b0000; - else if (cpu_state == CPU_STATE_RUN) - pr_count <= pr_count + 1'b1; else - pr_count <= 4'b0000; + pr_count <= pr_count + 1'b1; + +reg [3:0] cycle_a, cycle_b, cmd_val; +always @(posedge clk_1k) begin + if (cpu_state == CPU_STATE_RUN) begin + cycle_a <= pr_count; + cycle_b <= cycle_a; + cmd_val <= cycle_b; + end else begin + cycle_a <= 4'h0; + cycle_b <= 4'h0; + cmd_val <= 4'h0; + end end -reg [3:0] cycle_a, cycle_b, cycle_c; +wire rst_key; -always @(posedge cpld_clk_33M) begin - cycle_a <= pr_count; - cycle_b <= cycle_a; - cycle_c <= cycle_b; -end +key_delay reset_key( + .keypin(por_rst), + .clk_1K(clk_1k), + .keyout(rst_key)); + +reg power_on = 1'b0; -always @(posedge cpld_clk_33M) begin +localparam CPU_STATE_IDLE = 0, CPU_STATE_PWR = 1, CPU_STATE_RUN = 2, CPU_STATE_RST = 3; +reg [3:0] cpu_state = CPU_STATE_IDLE; +always @(posedge clk_1k) begin case (cpu_state) CPU_STATE_IDLE: begin - tick_en <= 1; - gpio0_a1_r <= 0; - rst_done_led_r <= 1; - cpu_state <= CPU_STATE_PWR; + tim_en <= 1'b1; + gpio0_a1 <= 1'b0; + run_led_n <= 1'b1; + cpu_state <= CPU_STATE_PWR; end CPU_STATE_PWR: begin if (power_on) begin - tick_en <= 0; - cpu_state <= CPU_STATE_RUN; + tim_en <= 0; + cpu_state <= CPU_STATE_RUN; end end CPU_STATE_RUN: begin - if (cycle_c == 4'b0001) begin - gpio0_a1_r <= 1'b1; - rst_done_led_r <= 1'b0; - end - if (cycle_c == 4'b0100) begin + if (!rst_key) begin // reset button pressed + tim_en <= 1'b1; cpu_state <= CPU_STATE_RST; - tick_en <= 1'b1; - end + end else + case (cmd_val) + 4'b0001: begin // bios booting + gpio0_a1 <= 1'b1; + run_led_n <= 1'b0; + end + 4'b0100: begin // system reset + cpu_state <= CPU_STATE_RST; + tim_en <= 1'b1; + end + endcase end CPU_STATE_RST: begin if (!power_on) begin - tick_en <= 1'b0; - rst_done_led_r <= 1; - cpu_state <= CPU_STATE_IDLE; + tim_en <= 1'b0; + run_led_n <= 1; + cpu_state <= CPU_STATE_IDLE; end end default: cpu_state <= cpu_state; endcase end -always @(posedge cpld_clk_33M) begin - if (!por_rst) begin - pwr_0v8_en_r <= 0; - pwr_1v2_en_r <= 0; - pwr_1v8_en_r <= 0; - pwr_2v5_en_r <= 0; - pwr_3v3_en_r <= 0; - pcierst_r <= 5'b00000; - ft_por_r <= 0; - end else if (power_on == 0) begin +// enable various votage groups. +always @(posedge clk_1k) begin + if (!power_on) begin case(msclk_count) - 17'd1: pwr_3v3_en_r <= 1; - 17'd100: begin - pwr_1v2_en_r <= 1; - pwr_2v5_en_r <= 1; + 16'd1: pwr_3v3_en <= 1; + 16'd100: begin + pwr_1v2_en <= 1; + pwr_2v5_en <= 1; + end + 16'd130: pwr_0v8_en <= 1; + 16'd160: pwr_1v8_en <= 1; + 16'd270: begin + pcierst <= 4'hf; + nvme_rst_n <= 1'b1; + end + 16'd290: begin + ft_por <= 1; + power_on <= 1; end - 17'd130: pwr_0v8_en_r <= 1; - 17'd160: pwr_1v8_en_r <= 1; - 17'd270: pcierst_r <= 5'h1f; - 17'd290: begin ft_por_r <= 1; power_on <= 1; end endcase end else if (power_on == 1) begin case (msclk_count) - 17'd10: begin - pcierst_r <= 5'h00; - ft_por_r <= 1'b0; + 16'd10: begin + pcierst <= 4'h0; + nvme_rst_n <= 1'b0; + ft_por <= 1'b0; end - 17'd120: pwr_1v8_en_r <= 1'b0; - 17'd140: pwr_0v8_en_r <= 1'b0; - 17'd160: begin - pwr_1v2_en_r <= 1'b0; - pwr_2v5_en_r <= 1'b0; + 16'd120: pwr_1v8_en <= 1'b0; + 16'd140: pwr_0v8_en <= 1'b0; + 16'd160: begin + pwr_1v2_en <= 1'b0; + pwr_2v5_en <= 1'b0; end - 17'd310: pwr_3v3_en_r <= 1'b0; - 17'd1000: power_on <= 1'b0; + 16'd310: pwr_3v3_en <= 1'b0; + 16'd1000: power_on <= 1'b0; endcase + end else begin end end diff --git a/src/key_delay.v b/src/key_delay.v new file mode 100644 index 0000000..7783ff8 --- /dev/null +++ b/src/key_delay.v @@ -0,0 +1,22 @@ + +module key_delay( +keypin,//switch pin +clk_1K,//50MHZ +keyout//if key on out 0 +); +input keypin; +input clk_1K; +output reg keyout; + +reg [20:0] keystate=0; + +always @(posedge clk_1K) + if (keypin==0) keystate=keystate+1'b1; + else keystate=0; + +always @(posedge clk_1K) + if(keystate>=30) keyout=0; // 30ms key on ,if have 30 times 1 ,can ensure key on ,and output 0 + else keyout=1; + + +endmodule \ No newline at end of file