From 986670605b29b4bbf565190ee0d236260b5ef39d Mon Sep 17 00:00:00 2001
From: surenyi <surenyi82@163.com>
Date: Thu, 23 Jul 2020 20:07:21 +0800
Subject: [PATCH] Changes:

update A2 pin map
only A2 as input

Signed-off-by: surenyi <surenyi82@163.com>
---
 ft2004.lci       | 4 ++--
 ft2004.lct       | 4 ++--
 ft2004.sty       | 8 +++++---
 src/ft2004_top.v | 4 ++--
 4 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/ft2004.lci b/ft2004.lci
index af3694d..4f51ec5 100644
--- a/ft2004.lci
+++ b/ft2004.lci
@@ -13,7 +13,7 @@ EN_PinMacrocell = No;
 [Revision]
 Parent = lc4k128v.lci;
 DATE = 07/23/2020;
-TIME = 12:07:46;
+TIME = 17:33:57;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -63,7 +63,7 @@ ft_spi0_csn3 = Pin, 21, -, C, 4;
 ft_spi1_csn3 = Pin, 22, -, C, 2;
 spi0_csn3 = Pin, 65, -, G, 12;
 spi1_csn3 = Pin, 64, -, G, 14;
-ft_gpio0_a2 = Pin, 12, 0, -, -;
+ft_gpio0_a2 = Pin, 14, -, C, 14;
 ft_gpio0_a4 = Pin, 15, -, C, 12;
 ft_gpio0_a5 = Pin, 17, -, C, 8;
 ft_gpio0_a6 = Pin, 16, -, C, 10;
diff --git a/ft2004.lct b/ft2004.lct
index af3694d..4f51ec5 100644
--- a/ft2004.lct
+++ b/ft2004.lct
@@ -13,7 +13,7 @@ EN_PinMacrocell = No;
 [Revision]
 Parent = lc4k128v.lci;
 DATE = 07/23/2020;
-TIME = 12:07:46;
+TIME = 17:33:57;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -63,7 +63,7 @@ ft_spi0_csn3 = Pin, 21, -, C, 4;
 ft_spi1_csn3 = Pin, 22, -, C, 2;
 spi0_csn3 = Pin, 65, -, G, 12;
 spi1_csn3 = Pin, 64, -, G, 14;
-ft_gpio0_a2 = Pin, 12, 0, -, -;
+ft_gpio0_a2 = Pin, 14, -, C, 14;
 ft_gpio0_a4 = Pin, 15, -, C, 12;
 ft_gpio0_a5 = Pin, 17, -, C, 8;
 ft_gpio0_a6 = Pin, 16, -, C, 10;
diff --git a/ft2004.sty b/ft2004.sty
index c9c2f6b..448c2a4 100644
--- a/ft2004.sty
+++ b/ft2004.sty
@@ -2,7 +2,7 @@
 synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
 _vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
-_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,                         
+_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,                          
 _EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
 _EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
@@ -17,7 +17,9 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
-[STRATEGY-LIST]
-Normal=True, 1595388407
 [synthesis-type]
 tool=Synplify
+[STRATEGY-LIST]
+Normal=True, 1595388407
+[TOUCHED-REPORT]
+Design.bl5File=1595496837
diff --git a/src/ft2004_top.v b/src/ft2004_top.v
index a12b13c..54fc32c 100644
--- a/src/ft2004_top.v
+++ b/src/ft2004_top.v
@@ -54,7 +54,7 @@ module top(
     inout ft_gpio0_a5,     // 17, 1.8v
     inout ft_gpio0_a6,     // 16, 1.8v
     inout ft_gpio0_a4,     // 15, 1.8v
-    inout ft_gpio0_a2,     // 12, 1.8v
+    inout ft_gpio0_a2,     // 14, 1.8v
     inout ft_gpio1_b7,     // 37, 1.8v
     inout ft_gpio0_b6,     // 36, 1.8v
     inout ft_gpio0_b7,     // 35, 1.8v
@@ -93,7 +93,7 @@ assign gpio1_a4 = ft_gpio1_a4;
 assign gpio0_a5 = ft_gpio0_a5;
 assign gpio0_a6 = ft_gpio0_a6;
 assign gpio0_a4 = ft_gpio0_a4;
-assign gpio0_a2 = ft_gpio0_a2;
+assign ft_gpio0_a2 = gpio0_a2;
 assign gpio1_b7 = ft_gpio1_b7;
 assign gpio0_b6 = ft_gpio0_b6;
 assign gpio0_b7 = ft_gpio0_b7;