phytium
/
cpld
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
Browse Source

various code improvments 

Signed-off-by: surenyi <surenyi82@163.com>
master
surenyi 4 years ago
parent
1ea1c97432
commit
9b443773cb
2 changed files with 101 additions and 81 deletions
Whitespace
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Split View
Diff Options
Show Stats Download Patch File Download Diff File
  1. 15
      .gitignore
  2. 167
      src/ft2004_top.v

15
.gitignore
View File

@ -1,2 +1,17 @@
*.log
*.jed
*.err
*.naf
*.html
*.ini
*.csv
*.lc_
*.txt
top.*
ft2004.*
dm/
synlog/
syntmp/
synwork/
syndos.env
scratchproject.prs

167
src/ft2004_top.v
View File

@ -87,12 +87,12 @@ assign spi1_csn3 = ft_spi1_csn3;
// XXX: sda line maybe work incorrectly.
// need to be fixed ?
assign i2c_scl3 = ft_i2c_scl3;
// XXX: sda line can't work as bidirectiono
// XXX: sda line can't work bidirection, need to be fix.
assign i2c_sda3 = ft_i2c_sda3;
// gpio 1.8v <-> 3.3v
// XXX: inout maybe errors, it only works one direction,
// need to be fixed ?
// need to be fix ?
assign ft_gpio0_a2 = ft_gpio0_a3 == 1'b1 ? gpio0_a2 : 1'bZ;
assign gpio0_a2 = ft_gpio0_a3 == 1'b0 ? ft_gpio0_a2 : 1'bZ;
@ -106,6 +106,10 @@ assign gpio1_b7 = ft_gpio1_b7;
assign gpio0_b6 = ft_gpio0_b6;
assign gpio0_b7 = ft_gpio0_b7;
localparam CPU_STATE_IDLE = 2'b00,
CPU_STATE_RUN = 2'b01,
CPU_STATE_RST = 2'b10;
reg clk_1k = 1'b0;
// divide to 1K clock
@ -118,38 +122,24 @@ always @(posedge clk_33m)
unit_1ms_count <= unit_1ms_count + 1'b1;
// 12bits 1ms timer
reg tim_en = 1'b0;
reg tim_run = 1'b0;
reg timen_flag = 1'b0;
reg [11:0] msclk_count;
reg [11:0] mills_count;
always @(posedge clk_1k) begin
if (!tim_en) begin
msclk_count <= 12'd0;
tim_run <= 1'b0;
if (!timen_flag) begin
mills_count <= 12'd0;
end else begin
msclk_count <= msclk_count + 1'd1;
tim_run <= 1'b1;
mills_count <= mills_count + 1'd1;
end
end
// sample PWR_CTR1 clock ticks.
reg [3:0] pr_count;
reg [3:0] ctr_cnt;
always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0)
if (!ft_pwr_ctl0)
pr_count <= 4'b0000;
ctr_cnt <= 4'b0000;
else
pr_count <= pr_count + 1'b1;
reg [3:0] cmd_val_b, cmd_val;
always @(posedge clk_33m) begin
if (cpu_state == CPU_STATE_RUN) begin
cmd_val_b <= pr_count;
cmd_val <= cmd_val_b;
end else begin
cmd_val_b <= 4'h0;
cmd_val <= 4'h0;
end
end
ctr_cnt <= ctr_cnt + 1'b1;
// reset key detection
wire rst_key;
@ -160,73 +150,88 @@ key_delay reset_key(
reg power_on = 1'b0;
localparam CPU_STATE_IDLE = 0, CPU_STATE_PRE_PWR = 1, CPU_STATE_PWR = 2, CPU_STATE_POST_PWR = 3,
CPU_STATE_RUN = 4, CPU_STATE_PRE_RST = 5, CPU_STATE_RST = 6, CPU_STATE_POST_RST = 7;
reg [2:0] cpu_state = CPU_STATE_IDLE;
reg [1:0] state = CPU_STATE_IDLE;
reg [1:0] next_state = CPU_STATE_IDLE;
reg [3:0] cmd_b, cmd_q, cmd_val;
always @(posedge clk_33m) begin
cmd_b <= ctr_cnt;
cmd_q <= cmd_b;
end
always @(posedge clk_33m) begin
case (cpu_state)
state <= next_state;
end
always @(*) begin
case (state)
CPU_STATE_IDLE:
if (power_on)
next_state = CPU_STATE_RUN;
else if (!rst_key)
next_state = CPU_STATE_RST;
else
next_state = state;
CPU_STATE_RUN:
if (!rst_key)
next_state = CPU_STATE_RST;
else if (cmd_val == 4'b0100)
next_state = CPU_STATE_RST;
else
next_state = state;
CPU_STATE_RST:
if (!power_on)
next_state = CPU_STATE_IDLE;
else
next_state = state;
default: next_state = state;
endcase
end
always @(*) begin
case (state)
CPU_STATE_IDLE: begin
tim_en <= 1'b1;
gpio0_a1 <= 1'b0;
run_led_n <= 1'b1;
cpu_state <= CPU_STATE_PRE_PWR;
end
CPU_STATE_PRE_PWR: begin
if (tim_run) cpu_state <= CPU_STATE_PWR;
end
CPU_STATE_PWR: begin
if (power_on) begin
tim_en <= 0;
cpu_state <= CPU_STATE_POST_PWR;
end
end
CPU_STATE_POST_PWR: begin
if (!tim_run) cpu_state <= CPU_STATE_RUN;
gpio0_a1 = 1'b0;
run_led_n = 1'b1;
if (power_on)
timen_flag = 1'b0;
else
timen_flag = 1'b1;
end
CPU_STATE_RUN: begin
if (!rst_key) begin // reset button pressed
tim_en <= 1'b1;
cpu_state <= CPU_STATE_PRE_RST;
end else
case (cmd_val)
4'b0001: begin // bios booting: S3_OK_Clear
gpio0_a1 <= 1'b1;
run_led_n <= 1'b0;
end
4'b0100: begin // system reset: reboot
cpu_state <= CPU_STATE_PRE_RST;
tim_en <= 1'b1;
end
//4'b1000: //S0->S3
//4'b1100: //S0->S5
endcase
end
CPU_STATE_PRE_RST: begin
if (tim_run) cpu_state <= CPU_STATE_RST;
end
CPU_STATE_RST: begin
if (!power_on) begin
tim_en <= 1'b0;
run_led_n <= 1;
cpu_state <= CPU_STATE_POST_RST;
end
end
CPU_STATE_POST_RST: begin
if (!tim_run) cpu_state <= CPU_STATE_IDLE;
if (!cmd_b)
cmd_val = cmd_q;
else
cmd_val = 4'b0000;
case (cmd_val)
4'b0001: begin // bios booting: S3_OK_Clear
gpio0_a1 = 1'b1;
run_led_n = 1'b0;
end
4'b0100: begin // system reset: reboot
timen_flag = 1'b1;
end
//4'b1000: //S0->S3
//4'b1100: //S0->S5
default: run_led_n = run_led_n;
endcase
end
default: cpu_state <= cpu_state;
CPU_STATE_RST:
if (!power_on)
timen_flag = 1'b0;
else
timen_flag = 1'b1;
default: run_led_n = run_led_n;
endcase
end
// enable various votage groups.
// if `time_en == 1'b0, msclk_count always equal to `0`
// if `time_en == 1'b0, mills_count always equal to `0`
// so power pins will stable.
always @(posedge clk_1k) begin
if (!power_on) begin
case(msclk_count)
case(mills_count)
12'd1: pwr_3v3_en <= 1;
12'd100: begin
pwr_1v2_en <= 1;
@ -239,12 +244,12 @@ always @(posedge clk_1k) begin
nvme_rst_n <= 1'b1;
end
12'd290: begin
ft_por <= 1;
ft_por <= 1;
power_on <= 1;
end
endcase
end else begin
case (msclk_count)
case (mills_count)
12'd10: begin
pcierst <= 4'h0;
nvme_rst_n <= 1'b0;

Write Preview
Loading…
Cancel
Save