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import cpld code: cpu rest working 

Signed-off-by: surenyi <surenyi82@163.com>
master
surenyi 4 years ago
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  1. 1
      .gitignore
  2. 0
      ft2004.h
  3. 147
      ft2004.lci
  4. 147
      ft2004.lct
  5. 25
      ft2004.sty
  6. 11
      ft2004.syn
  7. 1
      ft2004_top.jhd
  8. 168
      src/ft2004_top.v

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.gitignore
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*.log

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ft2004.h
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147
ft2004.lci
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[Device]
Family = lc4k;
PartNumber = LC4128V-10T100I;
Package = 100TQFP;
PartType = LC4128V;
Speed = -10;
Operating_condition = IND;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;
[Revision]
Parent = lc4k128v.lci;
DATE = 07/22/2020;
TIME = 19:02:52;
Source_Format = Pure_Verilog_HDL;
Synthesis = Synplify;
[Ignore Assignments]
[Clear Assignments]
[Backannotate Assignments]
[Global Constraints]
[Location Assignments]
layer = OFF;
ft_por = Pin, 94, -, A, 6;
gpio0_a1 = Pin, 92, -, A, 2;
pwr_0v8_en = Pin, 41, -, E, 0;
pwr_1v2_en = Pin, 42, -, E, 2;
pwr_1v8_en = Pin, 43, -, E, 4;
pwr_2v5_en = Pin, 44, -, E, 6;
pwr_3v3_en = Pin, 47, -, E, 8;
rst_done_led = Pin, 56, -, F, 6;
ft_pwr_ctl0 = Pin, 97, -, A, 8;
ft_pwr_ctl1 = Pin, 98, -, A, 10;
pcierst_0_ = Pin, 48, -, E, 10;
pcierst_1_ = Pin, 49, -, E, 12;
pcierst_2_ = Pin, 50, -, E, 14;
pcierst_3_ = Pin, 53, -, F, 0;
pcierst_4_ = Pin, 54, -, F, 2;
cpld_clk_33M = Pin, 88, -, -, -;
[Group Assignments]
layer = OFF;
[Resource Reservations]
layer = OFF;
[Fitter Report Format]
[Power]
[Source Constraint Option]
[Fast Bypass]
[OSM Bypass]
[Input Registers]
[Netlist/Delay Format]
NetList = VERILOG;
[IO Types]
layer = OFF;
[Pullup]
[Slewrate]
[Region]
[Timing Constraints]
layer = OFF;
[HSI Attributes]
[Input Delay]
[opt global constraints list]
[Explorer User Settings]
[Pin attributes list]
[global constraints list]
[Global Constraints Process Update]
[pin lock limitation]
[LOCATION ASSIGNMENTS LIST]
[RESOURCE RESERVATIONS LIST]
[individual constraints list]
[Attributes list setting]
[Timing Analyzer]
[PLL Assignments]
[Dual Function Macrocell]
[Explorer Results]
[VHDL synplify constraints]
[VHDL spectrum constraints]
[verilog synplify constraints]
[verilog spectrum constraints]
[VHDL synplify constraints list]
[VHDL spectrum constraints list]
[verilog synplify constraints list]
[verilog spectrum constraints list]
[ORP Bypass]
[Register Powerup]
RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en,
rst_done_led, pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, pcierst_4_;
[Constraint Version]
version = 1.0;
[ORP ASSIGNMENTS]
layer = OFF;
[Node attribute]
layer = OFF;
[SYMBOL/MODULE attribute]
layer = OFF;
[Nodal Constraints]
layer = OFF;

147
ft2004.lct
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[Device]
Family = lc4k;
PartNumber = LC4128V-10T100I;
Package = 100TQFP;
PartType = LC4128V;
Speed = -10;
Operating_condition = IND;
Status = Production;
EN_PinGLB = yes;
EN_PinMacrocell = yes;
[Revision]
Parent = lc4k128v.lci;
DATE = 07/22/2020;
TIME = 19:02:52;
Source_Format = Pure_Verilog_HDL;
Synthesis = Synplify;
[Ignore Assignments]
[Clear Assignments]
[Backannotate Assignments]
[Global Constraints]
[Location Assignments]
layer = OFF;
ft_por = Pin, 94, -, A, 6;
gpio0_a1 = Pin, 92, -, A, 2;
pwr_0v8_en = Pin, 41, -, E, 0;
pwr_1v2_en = Pin, 42, -, E, 2;
pwr_1v8_en = Pin, 43, -, E, 4;
pwr_2v5_en = Pin, 44, -, E, 6;
pwr_3v3_en = Pin, 47, -, E, 8;
rst_done_led = Pin, 56, -, F, 6;
ft_pwr_ctl0 = Pin, 97, -, A, 8;
ft_pwr_ctl1 = Pin, 98, -, A, 10;
pcierst_0_ = Pin, 48, -, E, 10;
pcierst_1_ = Pin, 49, -, E, 12;
pcierst_2_ = Pin, 50, -, E, 14;
pcierst_3_ = Pin, 53, -, F, 0;
pcierst_4_ = Pin, 54, -, F, 2;
cpld_clk_33M = Pin, 88, -, -, -;
[Group Assignments]
layer = OFF;
[Resource Reservations]
layer = OFF;
[Fitter Report Format]
[Power]
[Source Constraint Option]
[Fast Bypass]
[OSM Bypass]
[Input Registers]
[Netlist/Delay Format]
NetList = VERILOG;
[IO Types]
layer = OFF;
[Pullup]
[Slewrate]
[Region]
[Timing Constraints]
layer = OFF;
[HSI Attributes]
[Input Delay]
[opt global constraints list]
[Explorer User Settings]
[Pin attributes list]
[global constraints list]
[Global Constraints Process Update]
[pin lock limitation]
[LOCATION ASSIGNMENTS LIST]
[RESOURCE RESERVATIONS LIST]
[individual constraints list]
[Attributes list setting]
[Timing Analyzer]
[PLL Assignments]
[Dual Function Macrocell]
[Explorer Results]
[VHDL synplify constraints]
[VHDL spectrum constraints]
[verilog synplify constraints]
[verilog spectrum constraints]
[VHDL synplify constraints list]
[VHDL spectrum constraints list]
[verilog synplify constraints list]
[verilog spectrum constraints list]
[ORP Bypass]
[Register Powerup]
RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en,
rst_done_led, pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, pcierst_4_;
[Constraint Version]
version = 1.0;
[ORP ASSIGNMENTS]
layer = OFF;
[Node attribute]
layer = OFF;
[SYMBOL/MODULE attribute]
layer = OFF;
[Nodal Constraints]
layer = OFF;

25
ft2004.sty
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[Normal]
synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
_vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,
_EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
_EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
_EdfPerDesignOptTiming=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
_EdfOutputPreFile=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfMapLogic=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
_EdfInsertIO=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
_EdfOutNetForm=lc4k_pvlg, Verilog.TASKLSVlog, 0, None
_EdfNumCritPath=lc4k_pvlg, Verilog.TASKLSVlog, 0, 3
_EdfUnconsClk=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
_EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
_EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
[STRATEGY-LIST]
Normal=True, 1595388407
[TOUCHED-REPORT]
Design.bl5File=1595415772
[synthesis-type]
tool=Synplify

11
ft2004.syn
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JDF B
// Created by Version 1.7
PROJECT ft2004
DESIGN ft2004 Normal
DEVKIT LC4128V-10T100I
ENTRY Pure Verilog HDL
MODULE .\src\ft2004_top.v
MODSTYLE top Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
TOPMODULE top

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ft2004_top.jhd
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MODULE top DEFIN .\src\ft2004_top.v

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src/ft2004_top.v
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module top(
input cpld_clk_33M, //88, 33M, 30NS
input por_rst, //low_effect, 73
input ft_pwr_ctl0, //97
input ft_pwr_ctl1, //98
output pwr_0v8_en, //41
output pwr_1v2_en, //42
output pwr_1v8_en, //43
output pwr_2v5_en, //44
output pwr_3v3_en, //47
output [4:0] pcierst, //bit0: 48~49~50~53 ~54:bit4
output ft_por, //94
output rst_done_led, //56
output gpio0_a1 //92
);
reg pwr_0v8_en_r;
reg pwr_1v2_en_r;
reg pwr_1v8_en_r;
reg pwr_2v5_en_r;
reg pwr_3v3_en_r;
reg [4:0]pcierst_r;
reg ft_por_r;
reg rst_done_led_r;
reg gpio0_a1_r;
assign pwr_0v8_en = pwr_0v8_en_r;
assign pwr_1v2_en = pwr_1v2_en_r;
assign pwr_1v8_en = pwr_1v8_en_r;
assign pwr_2v5_en = pwr_2v5_en_r;
assign pwr_3v3_en = pwr_3v3_en_r;
assign pcierst = pcierst_r;
assign ft_por = ft_por_r;
assign rst_done_led = rst_done_led_r;
assign gpio0_a1 = gpio0_a1_r;
reg tick_en = 0;
reg [15:0] uint_1ms_count;
reg [16:0] msclk_count;
reg tick_1ms;
`define TICK_1MS 33000
always @(posedge cpld_clk_33M) begin
if (!tick_en) begin
uint_1ms_count <= 16'd0;
tick_1ms <= 0;
end else if (uint_1ms_count == `TICK_1MS) begin
uint_1ms_count <= 16'd0;
tick_1ms <= 1;
end else begin
uint_1ms_count <= uint_1ms_count + 1'd1;
tick_1ms <= 0;
end
end
always @(posedge cpld_clk_33M) begin
if (!tick_en)
msclk_count <= 17'd0;
else if (tick_1ms) begin
msclk_count <= msclk_count + 1'd1;
end
end
localparam CPU_STATE_IDLE = 0, CPU_STATE_PWR = 1, CPU_STATE_RUN = 2, CPU_STATE_RST = 3;
reg [3:0] cpu_state = CPU_STATE_IDLE;
reg power_on = 0;
reg [3:0] pr_count;
always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0) begin
if (!ft_pwr_ctl0)
pr_count <= 4'b0000;
else if (cpu_state == CPU_STATE_RUN)
pr_count <= pr_count + 1'b1;
else
pr_count <= 4'b0000;
end
reg [3:0] cycle_a, cycle_b, cycle_c;
always @(posedge cpld_clk_33M) begin
cycle_a <= pr_count;
cycle_b <= cycle_a;
cycle_c <= cycle_b;
end
always @(posedge cpld_clk_33M) begin
case (cpu_state)
CPU_STATE_IDLE: begin
tick_en <= 1;
gpio0_a1_r <= 0;
rst_done_led_r <= 1;
cpu_state <= CPU_STATE_PWR;
end
CPU_STATE_PWR: begin
if (power_on) begin
tick_en <= 0;
cpu_state <= CPU_STATE_RUN;
end
end
CPU_STATE_RUN: begin
if (cycle_c == 4'b0001) begin
gpio0_a1_r <= 1'b1;
rst_done_led_r <= 1'b0;
end
if (cycle_c == 4'b0100) begin
cpu_state <= CPU_STATE_RST;
tick_en <= 1'b1;
end
end
CPU_STATE_RST: begin
if (!power_on) begin
tick_en <= 1'b0;
rst_done_led_r <= 1;
cpu_state <= CPU_STATE_IDLE;
end
end
default: cpu_state <= cpu_state;
endcase
end
always @(posedge cpld_clk_33M) begin
if (!por_rst) begin
pwr_0v8_en_r <= 0;
pwr_1v2_en_r <= 0;
pwr_1v8_en_r <= 0;
pwr_2v5_en_r <= 0;
pwr_3v3_en_r <= 0;
pcierst_r <= 5'b00000;
ft_por_r <= 0;
end else if (power_on == 0) begin
case(msclk_count)
17'd1: pwr_3v3_en_r <= 1;
17'd100: begin
pwr_1v2_en_r <= 1;
pwr_2v5_en_r <= 1;
end
17'd130: pwr_0v8_en_r <= 1;
17'd160: pwr_1v8_en_r <= 1;
17'd270: pcierst_r <= 5'h1f;
17'd290: begin ft_por_r <= 1; power_on <= 1; end
endcase
end else if (power_on == 1) begin
case (msclk_count)
17'd10: begin
pcierst_r <= 5'h00;
ft_por_r <= 1'b0;
end
17'd120: pwr_1v8_en_r <= 1'b0;
17'd140: pwr_0v8_en_r <= 1'b0;
17'd160: begin
pwr_1v2_en_r <= 1'b0;
pwr_2v5_en_r <= 1'b0;
end
17'd310: pwr_3v3_en_r <= 1'b0;
17'd1000: power_on <= 1'b0;
endcase
end
end
endmodule
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