adjust some contriants

Signed-off-by: surenyi <surenyi82@163.com>

.gitignore

@@ -7,6 +7,8 @@
 *.csv
 *.lc_
 *.txt
+*.dum
+*.rs2
 top.*
 ft2004.*
 dm/

ft2004.lci

@@ -12,8 +12,8 @@ EN_PinMacrocell = No;
 
 [Revision]
 Parent = lc4k128v.lci;
-DATE = 07/24/2020;
+DATE = 07/26/2020;
-TIME = 12:01:05;
+TIME = 08:15:40;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -24,6 +24,12 @@ Synthesis = Synplify;
 [Backannotate Assignments]
 
 [Global Constraints]
+Clock_enable_optimization = Auto;
+Max_fanin_limit = 28;
+Nodes_collapsing_mode = Fmax;
+Logic_optimization_effort = 3;
+Balanced_partitioning = No;
+Fitter_effort_level = Medium;
 
 [Location Assignments]
 layer = OFF;
@@ -141,6 +147,7 @@ por_rst = LVCMOS33, PIN, 1, -;
 sys_rst_in = LVCMOS33, PIN, 1, -;
 
 [Pullup]
+Default = DOWN;
 
 [Slewrate]
 

ft2004.lct

@@ -12,8 +12,8 @@ EN_PinMacrocell = No;
 
 [Revision]
 Parent = lc4k128v.lci;
-DATE = 07/24/2020;
+DATE = 07/26/2020;
-TIME = 12:01:05;
+TIME = 08:15:40;
 Source_Format = Pure_Verilog_HDL;
 Synthesis = Synplify;
 
@@ -24,6 +24,12 @@ Synthesis = Synplify;
 [Backannotate Assignments]
 
 [Global Constraints]
+Clock_enable_optimization = Auto;
+Max_fanin_limit = 28;
+Nodes_collapsing_mode = Fmax;
+Logic_optimization_effort = 3;
+Balanced_partitioning = No;
+Fitter_effort_level = Medium;
 
 [Location Assignments]
 layer = OFF;
@@ -141,6 +147,7 @@ por_rst = LVCMOS33, PIN, 1, -;
 sys_rst_in = LVCMOS33, PIN, 1, -;
 
 [Pullup]
+Default = DOWN;
 
 [Slewrate]
 

ft2004.sty

@@ -2,7 +2,7 @@
 synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
 _vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
-_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,                             
+_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,                                  
 _EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
 _EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
@@ -17,7 +17,7 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
-[STRATEGY-LIST]
-Normal=True, 1595388407
 [synthesis-type]
 tool=Synplify
+[STRATEGY-LIST]
+Normal=True, 1595388407

src/ft2004_top.v

@@ -216,7 +216,7 @@ always @(*) begin
                 end
                 //4'b1000: //S0->S3
                 //4'b1100: //S0->S5
-                default: run_led_n = run_led_n;
+                default: timen_flag = 1'b0;
             endcase
         end
         CPU_STATE_RST:
@@ -224,7 +224,7 @@ always @(*) begin
                 timen_flag = 1'b0;
             else
                 timen_flag = 1'b1;
-        default: run_led_n = run_led_n;
+        default: run_led_n = 1'b1;
     endcase
 end