change FSM from 3 segments to 2 segments

Signed-off-by: surenyi <surenyi82@163.com>

src/ft2004_top.v

@@ -137,6 +137,19 @@ always @(posedge ft_pwr_ctl1 or negedge ft_pwr_ctl0)
     else
         ctr_cnt <= ctr_cnt + 1'b1;
 
+// time domain crossing.
+reg [3:0] ctr_cnt_q, cmd_b, cmd_q, cmd_val;
+always @(posedge clk_33m) begin
+	ctr_cnt_q <= ctr_cnt;
+    cmd_b     <= ctr_cnt_q;
+    cmd_q     <= cmd_b;
+
+    if (cmd_b == 4'b0000)
+        cmd_val <= cmd_q;
+    else
+        cmd_val <= 4'b0000;
+end
+
 // reset key detection
 wire rst_key;
 key_delay #(.debound(50)) reset_key(
@@ -151,81 +164,51 @@ localparam CPU_STATE_IDLE = 2'b00,
            CPU_STATE_RST  = 2'b10;
            
 reg [1:0] state      = CPU_STATE_IDLE;
-reg [1:0] next_state = CPU_STATE_IDLE;
-
-reg [3:0] cmd_b, cmd_q, cmd_val;
-
-always @(posedge clk_33m) begin
-    cmd_b <= ctr_cnt;
-    cmd_q <= cmd_b;
-
-    if (cmd_b == 4'b0000)
-        cmd_val <= cmd_q;
-    else
-        cmd_val <= 4'b0000;
-end
-
 // cpu state transition
-always @(posedge clk_33m) begin
-    state   <= next_state;       
-end
-
-always @(*) begin
+always @(posedge clk_33m)
     case (state)
         CPU_STATE_IDLE:
             if (power_on)
-                next_state = CPU_STATE_RUN;
-            else
-                next_state = state;
+                state <= CPU_STATE_RUN;
         CPU_STATE_RUN:
             if (rst_key)
-                next_state = CPU_STATE_RST;
+                state <= CPU_STATE_RST;
             else if (cmd_val == 4'b0100) // reboot
-                next_state = CPU_STATE_RST;
-            else
-                next_state = state;
+                state <= CPU_STATE_RST;
         CPU_STATE_RST:
             if (!power_on)
-                next_state = CPU_STATE_IDLE;
-            else
-                next_state  = state;
-        default: next_state = state;
+                state <= CPU_STATE_IDLE;
     endcase
-end
 
-always @(*) begin
+always @(posedge clk_33m)
     case (state)
         CPU_STATE_IDLE: begin
-            gpio0_a1  = 1'b0;
-            run_led_n = 1'b1;
+            gpio0_a1  <= 1'b0;
+            run_led_n <= 1'b1;
             if (power_on)
-                timen_flag = 1'b0;
+                timen_flag <= 1'b0;
             else
-                timen_flag = 1'b1;
+                timen_flag <= 1'b1;
         end
         CPU_STATE_RUN: begin
             case (cmd_val)
                 4'b0001: begin // bios booting: S3_OK_Clear
-                    gpio0_a1   = 1'b1;
-                    run_led_n  = 1'b0;
+                    gpio0_a1   <= 1'b1;
+                    run_led_n  <= 1'b0;
                 end
                 4'b0100: begin // system reset: reboot
-                    timen_flag = 1'b1;
+                    timen_flag <= 1'b1;
                 end
                 //4'b1000: //S0->S3
                 //4'b1100: //S0->S5
-                default: timen_flag = 1'b0;
             endcase
         end
         CPU_STATE_RST:
             if (!power_on)
-                timen_flag = 1'b0;
+                timen_flag <= 1'b0;
             else
-                timen_flag = 1'b1;
-        default: run_led_n = 1'b1;
+                timen_flag <= 1'b1;
     endcase
-end
-
 //
 // enable various voltage groups.
 // if `time_en == 1'b0, mills_count always equal to `0`