key_delay: if pressed keyout == 1

Signed-off-by: surenyi <surenyi82@163.com>

ft2004.sty

@@ -17,7 +17,7 @@ _EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
 _EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
 _EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
-[synthesis-type]
-tool=Synplify
 [STRATEGY-LIST]
 Normal=True, 1595388407
+[synthesis-type]
+tool=Synplify

src/ft2004_top.v

@@ -142,9 +142,8 @@ wire rst_key;
 key_delay reset_key(
     .keypin(por_rst & sys_rst_in),
     .clk_1K(clk_1k),
-    .keyout(rst_key));
+    .keyout(rst_key)); // reset key pressed, output 1, otherwise output 0.
 
-// cpu state transition
 reg power_on = 1'b0;
 
 localparam CPU_STATE_IDLE = 2'b00, 
@@ -166,6 +165,7 @@ always @(posedge clk_33m) begin
         cmd_val <= 4'b0000;
 end
 
+// cpu state transition
 always @(posedge clk_33m) begin
     state   <= next_state;       
 end
@@ -175,14 +175,12 @@ always @(*) begin
         CPU_STATE_IDLE:
             if (power_on)
                 next_state = CPU_STATE_RUN;
-            else if (!rst_key)
-                next_state = CPU_STATE_RST;
             else
                 next_state = state;
         CPU_STATE_RUN:
-            if (!rst_key)
+            if (rst_key)
                 next_state = CPU_STATE_RST;
-            else if (cmd_val == 4'b0100)
+            else if (cmd_val == 4'b0100) // reboot
                 next_state = CPU_STATE_RST;
             else
                 next_state = state;

src/key_delay.v

@@ -1,22 +1,19 @@
-
-module key_delay(
-keypin,//switch pin
-clk_1K,//50MHZ
-keyout//if key on out 0
+module key_delay #(parameter debound = 30) (
+    input keypin      ,// switch pin
+    input clk_1K      ,// 1ms period
+    output reg keyout  // if key on out 1
 );
-input keypin;
-input clk_1K;
-output reg keyout;
-
-reg [20:0] keystate=0;
-
-always @(posedge clk_1K)
-		if (keypin==0) keystate=keystate+1'b1; 
-		else keystate=0;
-  
-always @(posedge clk_1K)
-		if(keystate>=30) keyout=0; // 30ms key on ,if have 30 times 1 ,can ensure key on ,and output 0
-		else keyout=1;
+    reg [9:0] keystate = 0;
 
+    always @(posedge clk_1K)
+        if (!keypin)
+            keystate = keystate + 1'b1; 
+        else
+            keystate = 0;
 
+    always @(posedge clk_1K)
+        if (keystate >= debound)
+            keyout = 1; // default 30ms key on, if have 30 times 1, can ensure key on, and output 1
+        else
+            keyout = 0;
 endmodule