|
|
@ -106,10 +106,6 @@ assign gpio1_b7 = ft_gpio1_b7; |
|
|
|
assign gpio0_b6 = ft_gpio0_b6; |
|
|
|
assign gpio0_b7 = ft_gpio0_b7; |
|
|
|
|
|
|
|
localparam CPU_STATE_IDLE = 2'b00, |
|
|
|
CPU_STATE_RUN = 2'b01, |
|
|
|
CPU_STATE_RST = 2'b10; |
|
|
|
|
|
|
|
reg clk_1k = 1'b0; |
|
|
|
|
|
|
|
// divide to 1K clock |
|
|
@ -148,8 +144,13 @@ key_delay reset_key( |
|
|
|
.clk_1K(clk_1k), |
|
|
|
.keyout(rst_key)); |
|
|
|
|
|
|
|
// cpu state transition |
|
|
|
reg power_on = 1'b0; |
|
|
|
|
|
|
|
localparam CPU_STATE_IDLE = 2'b00, |
|
|
|
CPU_STATE_RUN = 2'b01, |
|
|
|
CPU_STATE_RST = 2'b10; |
|
|
|
|
|
|
|
reg [1:0] state = CPU_STATE_IDLE; |
|
|
|
reg [1:0] next_state = CPU_STATE_IDLE; |
|
|
|
|
|
|
@ -158,6 +159,11 @@ reg [3:0] cmd_b, cmd_q, cmd_val; |
|
|
|
always @(posedge clk_33m) begin |
|
|
|
cmd_b <= ctr_cnt; |
|
|
|
cmd_q <= cmd_b; |
|
|
|
|
|
|
|
if (cmd_b == 4'b0000) |
|
|
|
cmd_val <= cmd_q; |
|
|
|
else |
|
|
|
cmd_val <= 4'b0000; |
|
|
|
end |
|
|
|
|
|
|
|
always @(posedge clk_33m) begin |
|
|
@ -200,10 +206,6 @@ always @(*) begin |
|
|
|
timen_flag = 1'b1; |
|
|
|
end |
|
|
|
CPU_STATE_RUN: begin |
|
|
|
if (!cmd_b) |
|
|
|
cmd_val = cmd_q; |
|
|
|
else |
|
|
|
cmd_val = 4'b0000; |
|
|
|
case (cmd_val) |
|
|
|
4'b0001: begin // bios booting: S3_OK_Clear |
|
|
|
gpio0_a1 = 1'b1; |
|
|
@ -226,9 +228,10 @@ always @(*) begin |
|
|
|
endcase |
|
|
|
end |
|
|
|
|
|
|
|
// enable various votage groups. |
|
|
|
// |
|
|
|
// enable various voltage groups. |
|
|
|
// if `time_en == 1'b0, mills_count always equal to `0` |
|
|
|
// so power pins will stable. |
|
|
|
// so power pins will stable at most time. |
|
|
|
always @(posedge clk_1k) begin |
|
|
|
if (!power_on) begin |
|
|
|
case(mills_count) |
|
|
|