JDF B
// Created by Version 1.7 
PROJECT ft2004
DESIGN ft2004 Normal
DEVKIT LC4128V-10T100I
ENTRY Pure Verilog HDL
MODULE .\src\ft2004_top.v
MODSTYLE key_delay Normal
MODSTYLE top Normal
SYNTHESIS_TOOL Synplify
SIMULATOR_TOOL ActiveHDL
TOPMODULE top