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25 lines
1.1 KiB
25 lines
1.1 KiB
[Normal]
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synlibXRef=lc4k_pvlg, Verilog.TASKLSVlog, 0, Yes
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_vlog_std_v2001=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfFrequency=lc4k_pvlg, Verilog.TASKLSVlog, 0, 200
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_EdfInConsFile=lc4k_pvlg, Verilog.TASKLSVlog, 0,
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_EdfSymFSM=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfFanin=lc4k_pvlg, Verilog.TASKLSVlog, 0, 20
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_EdfMaxMacrocell=lc4k_pvlg, Verilog.TASKLSVlog, 0, 16
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_EdfPerDesignOptTiming=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
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_EdfOutputPreFile=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfMapLogic=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
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_EdfInsertIO=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
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_EdfOutNetForm=lc4k_pvlg, Verilog.TASKLSVlog, 0, None
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_EdfNumCritPath=lc4k_pvlg, Verilog.TASKLSVlog, 0, 3
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_EdfUnconsClk=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfNumStartEnd=lc4k_pvlg, Verilog.TASKLSVlog, 0, 0
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_EdfResSharing=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfPushTirstates=lc4k_pvlg, Verilog.TASKLSVlog, 0, True
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_EdfAllowDUPMod=lc4k_pvlg, Verilog.TASKLSVlog, 0, False
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[STRATEGY-LIST]
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Normal=True, 1595388407
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[TOUCHED-REPORT]
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Design.bl5File=1595811534
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[synthesis-type]
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tool=Synplify
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