You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.
229 lines
5.0 KiB
229 lines
5.0 KiB
|
|
[Device]
|
|
Family = lc4k;
|
|
PartNumber = LC4128V-10T100I;
|
|
Package = 100TQFP;
|
|
PartType = LC4128V;
|
|
Speed = -10;
|
|
Operating_condition = IND;
|
|
Status = Production;
|
|
EN_PinGLB = No;
|
|
EN_PinMacrocell = No;
|
|
|
|
[Revision]
|
|
Parent = lc4k128v.lci;
|
|
DATE = 07/27/2020;
|
|
TIME = 08:58:54;
|
|
Source_Format = Pure_Verilog_HDL;
|
|
Synthesis = Synplify;
|
|
|
|
[Ignore Assignments]
|
|
|
|
[Clear Assignments]
|
|
|
|
[Backannotate Assignments]
|
|
|
|
[Global Constraints]
|
|
Clock_enable_optimization = Auto;
|
|
Max_fanin_limit = 28;
|
|
Nodes_collapsing_mode = Fmax;
|
|
Logic_optimization_effort = 3;
|
|
Balanced_partitioning = Yes;
|
|
Fitter_effort_level = Low;
|
|
|
|
[Location Assignments]
|
|
layer = OFF;
|
|
ft_por = Pin, 94, -, A, 6;
|
|
gpio0_a1 = Pin, 92, -, A, 2;
|
|
pwr_0v8_en = Pin, 41, -, E, 0;
|
|
pwr_1v2_en = Pin, 42, -, E, 2;
|
|
pwr_1v8_en = Pin, 43, -, E, 4;
|
|
pwr_2v5_en = Pin, 44, -, E, 6;
|
|
pwr_3v3_en = Pin, 47, -, E, 8;
|
|
ft_pwr_ctl0 = Pin, 97, -, A, 8;
|
|
ft_pwr_ctl1 = Pin, 98, -, A, 10;
|
|
pcierst_0_ = Pin, 48, -, E, 10;
|
|
pcierst_1_ = Pin, 49, -, E, 12;
|
|
pcierst_2_ = Pin, 50, -, E, 14;
|
|
pcierst_3_ = Pin, 53, -, F, 0;
|
|
nvme_rst_n = Pin, 54, -, F, 2;
|
|
run_led_n = Pin, 56, -, F, 6;
|
|
clk_33m = Pin, 88, -, -, -;
|
|
can_rx0 = Pin, 58, -, F, 8;
|
|
ft_can_txd0 = Pin, 3, -, B, 0;
|
|
can_tx0 = Pin, 59, -, F, 10;
|
|
ft_can_rxd0 = Pin, 4, -, B, 2;
|
|
ft_i2c_scl3 = Pin, 10, -, B, 12;
|
|
ft_spi0_csn0 = Pin, 9, -, B, 10;
|
|
ft_spi0_sck = Pin, 5, -, B, 4;
|
|
ft_spi0_si = Pin, 8, -, B, 8;
|
|
spi0_so = Pin, 69, -, G, 6;
|
|
ft_spi0_so = Pin, 6, -, B, 6;
|
|
i2c_scl3 = Pin, 60, -, F, 12;
|
|
spi0_csn0 = Pin, 66, -, G, 10;
|
|
spi0_sck = Pin, 70, -, G, 5;
|
|
spi0_si = Pin, 67, -, G, 8;
|
|
ft_i2c_sda3 = Pin, 11, -, B, 13;
|
|
i2c_sda3 = Pin, 61, -, F, 13;
|
|
ft_spi0_csn3 = Pin, 21, -, C, 4;
|
|
ft_spi1_csn3 = Pin, 22, -, C, 2;
|
|
spi0_csn3 = Pin, 65, -, G, 12;
|
|
spi1_csn3 = Pin, 64, -, G, 14;
|
|
ft_gpio0_a2 = Pin, 14, -, C, 14;
|
|
ft_gpio0_a4 = Pin, 15, -, C, 12;
|
|
ft_gpio0_a5 = Pin, 17, -, C, 8;
|
|
ft_gpio0_a6 = Pin, 16, -, C, 10;
|
|
ft_gpio0_b6 = Pin, 36, -, D, 2;
|
|
ft_gpio0_b7 = Pin, 35, -, D, 4;
|
|
ft_gpio1_a4 = Pin, 19, -, C, 6;
|
|
ft_gpio1_b7 = Pin, 37, -, D, 0;
|
|
gpio0_a2 = Pin, 84, -, H, 6;
|
|
gpio0_a4 = Pin, 85, -, H, 4;
|
|
gpio0_a5 = Pin, 87, -, H, 0;
|
|
gpio0_a6 = Pin, 86, -, H, 2;
|
|
gpio0_b6 = Pin, 80, -, H, 10;
|
|
gpio0_b7 = Pin, 79, -, H, 12;
|
|
gpio1_a4 = Pin, 71, -, G, 4;
|
|
gpio1_b7 = Pin, 81, -, H, 8;
|
|
por_rst = Pin, 73, -, -, -;
|
|
sys_rst_in = Pin, 72, -, G, 2;
|
|
ft_gpio0_a3 = Pin, 99, -, A, 12;
|
|
ft_gpio1_a3 = Pin, 20, -, C, 5;
|
|
|
|
[Group Assignments]
|
|
layer = OFF;
|
|
|
|
[Resource Reservations]
|
|
layer = OFF;
|
|
|
|
[Fitter Report Format]
|
|
|
|
[Power]
|
|
|
|
[Source Constraint Option]
|
|
|
|
[Fast Bypass]
|
|
|
|
[OSM Bypass]
|
|
|
|
[Input Registers]
|
|
|
|
[Netlist/Delay Format]
|
|
NetList = VERILOG;
|
|
|
|
[IO Types]
|
|
layer = OFF;
|
|
pwr_0v8_en = LVCMOS33, PIN, 1, -;
|
|
pwr_1v2_en = LVCMOS33, PIN, 1, -;
|
|
pwr_1v8_en = LVCMOS33, PIN, 1, -;
|
|
pwr_2v5_en = LVCMOS33, PIN, 1, -;
|
|
pwr_3v3_en = LVCMOS33, PIN, 1, -;
|
|
pcierst_0_ = LVCMOS33, PIN, 1, -;
|
|
pcierst_1_ = LVCMOS33, PIN, 1, -;
|
|
pcierst_2_ = LVCMOS33, PIN, 1, -;
|
|
pcierst_3_ = LVCMOS33, PIN, 1, -;
|
|
nvme_rst_n = LVCMOS33, PIN, 1, -;
|
|
spi0_csn0 = LVCMOS33, PIN, 1, -;
|
|
spi0_csn3 = LVCMOS33, PIN, 1, -;
|
|
spi1_csn3 = LVCMOS33, PIN, 1, -;
|
|
run_led_n = LVCMOS33, PIN, 1, -;
|
|
can_tx0 = LVCMOS33, PIN, 1, -;
|
|
i2c_scl3 = LVCMOS33_OD, PIN, 1, -;
|
|
spi0_si = LVCMOS33, PIN, 1, -;
|
|
can_rx0 = LVCMOS33, PIN, 1, -;
|
|
spi0_so = LVCMOS33, PIN, 1, -;
|
|
spi0_sck = LVCMOS33, PIN, 1, -;
|
|
ft_i2c_sda3 = LVCMOS18, PIN, 0, -;
|
|
i2c_sda3 = LVCMOS33_OD, PIN, 1, -;
|
|
gpio0_a2 = LVCMOS33, PIN, 1, -;
|
|
gpio0_a4 = LVCMOS33, PIN, 1, -;
|
|
gpio0_a5 = LVCMOS33, PIN, 1, -;
|
|
gpio0_a6 = LVCMOS33, PIN, 1, -;
|
|
gpio0_b6 = LVCMOS33, PIN, 1, -;
|
|
gpio0_b7 = LVCMOS33, PIN, 1, -;
|
|
gpio1_a4 = LVCMOS33, PIN, 1, -;
|
|
gpio1_b7 = LVCMOS33, PIN, 1, -;
|
|
por_rst = LVCMOS33, PIN, 1, -;
|
|
sys_rst_in = LVCMOS33, PIN, 1, -;
|
|
|
|
[Pullup]
|
|
Default = DOWN;
|
|
|
|
[Slewrate]
|
|
|
|
[Region]
|
|
|
|
[Timing Constraints]
|
|
layer = OFF;
|
|
fMAX_0 = 30.3030, clk_33m, clk_33m;
|
|
|
|
[HSI Attributes]
|
|
|
|
[Input Delay]
|
|
|
|
[opt global constraints list]
|
|
|
|
[Explorer User Settings]
|
|
|
|
[Pin attributes list]
|
|
|
|
[global constraints list]
|
|
|
|
[Global Constraints Process Update]
|
|
|
|
[pin lock limitation]
|
|
|
|
[LOCATION ASSIGNMENTS LIST]
|
|
|
|
[RESOURCE RESERVATIONS LIST]
|
|
|
|
[individual constraints list]
|
|
|
|
[Attributes list setting]
|
|
|
|
[Timing Analyzer]
|
|
|
|
[PLL Assignments]
|
|
|
|
[Dual Function Macrocell]
|
|
|
|
[Explorer Results]
|
|
|
|
[VHDL synplify constraints]
|
|
|
|
[VHDL spectrum constraints]
|
|
|
|
[verilog synplify constraints]
|
|
|
|
[verilog spectrum constraints]
|
|
|
|
[VHDL synplify constraints list]
|
|
|
|
[VHDL spectrum constraints list]
|
|
|
|
[verilog synplify constraints list]
|
|
|
|
[verilog spectrum constraints list]
|
|
|
|
[ORP Bypass]
|
|
|
|
[Register Powerup]
|
|
RESET = ft_por, gpio0_a1, pwr_0v8_en, pwr_1v2_en, pwr_1v8_en, pwr_2v5_en, pwr_3v3_en,
|
|
pcierst_0_, pcierst_1_, pcierst_2_, pcierst_3_, nvme_rst_n, spi0_csn0,
|
|
spi0_csn3, spi1_csn3;
|
|
SET = run_led_n, can_tx0, ft_can_rxd0, ft_spi0_so, i2c_scl3, spi0_si;
|
|
|
|
[Constraint Version]
|
|
version = 1.0;
|
|
|
|
[ORP ASSIGNMENTS]
|
|
layer = OFF;
|
|
|
|
[Node attribute]
|
|
layer = OFF;
|
|
|
|
[SYMBOL/MODULE attribute]
|
|
layer = OFF;
|
|
|
|
[Nodal Constraints]
|
|
layer = OFF;
|
|
|