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11 lines
235 B
11 lines
235 B
JDF B
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// Created by Version 1.7
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PROJECT ft2004
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DESIGN ft2004 Normal
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DEVKIT LC4128V-10T100I
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ENTRY Pure Verilog HDL
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MODULE .\src\ft2004_top.v
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MODSTYLE top Normal
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SYNTHESIS_TOOL Synplify
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SIMULATOR_TOOL ActiveHDL
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TOPMODULE top
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