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287 lines
10 KiB
287 lines
10 KiB
3 weeks ago
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/* vxbFtI2c.h - I2C Controller hardware driver */
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/*
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it;
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef __INCvxbFtI2ch
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#define __INCvxbFtI2ch
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/* includes */
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#include <vxWorks.h>
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#include <intLib.h>
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#include <arch/arm/intArmLib.h>
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#include <spinLockLib.h>
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#include <vxBusLib.h>
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#include <vxAtomicLib.h>
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#include <isrDeferLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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#define FT_I2C_DRIVER_NAME "ftI2c"
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#define I2C_TIMEOUT 500
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#define I2C_DELAY 100
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#define I2C_STANDARD_SPEED 100000
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#define I2C_FAST_SPEED 400000
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#define I2C_DEFAULT_SYSCLK_RATE 100
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#define I2C_S_TO_US 1000000
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#define I2C_ERR_STATUS_RX_UNDER 1
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#define I2C_ERR_STATUS_RX_OVER 2
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#define I2C_ERR_STATUS_TX_ABRT 3
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/* Register Definition */
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#define I2C_CON 0x00
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#define I2C_TAR 0x04
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#define I2C_SAR 0x08
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#define I2C_HS_MADDR 0x0C
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#define I2C_DATA_CMD 0x10
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#define I2C_SS_SCL_HCNT 0x14
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#define I2C_SS_SCL_LCNT 0x18
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#define I2C_FS_SCL_HCNT 0x1C
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#define I2C_FS_SCL_LCNT 0x20
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#define I2C_HS_SCL_HCNT 0x24
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#define I2C_HS_SCL_LCNT 0x28
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#define I2C_INTR_STAT 0x2C
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#define I2C_INTR_MASK 0x30
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#define I2C_RAW_INTR_STAT 0x34
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#define I2C_RX_TL 0x38
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#define I2C_TX_TL 0x3C
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#define I2C_CLR_INTR 0x40
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#define I2C_CLR_RX_UNDER 0x44
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#define I2C_CLR_RX_OVER 0x48
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#define I2C_CLR_TX_OVER 0x4C
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#define I2C_CLR_RD_REQ 0x50
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#define I2C_CLR_TX_ABRT 0x54
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#define I2C_CLR_RX_DONE 0x58
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#define I2C_CLR_ACTIVITY 0x5c
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#define I2C_CLR_STOP_DET 0x60
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#define I2C_CLR_START_DET 0x64
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#define I2C_CLR_GEN_CALL 0x68
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#define I2C_ENABLE 0x6C
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#define I2C_STATUS 0x70
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#define I2C_TXFLR 0x74
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#define I2C_RXFLR 0x78
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#define I2C_TX_ABRT_SOURCE 0x80
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#define I2C_SLV_DATA_NACK_ONLY 0x84
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#define I2C_DMA_CR 0x88
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#define I2C_DMA_TDLR 0x8c
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#define I2C_DMA_RDLR 0x90
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#define I2C_SDA_SETUP 0x94
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#define I2C_ACK_GENERAL_CALL 0x98
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#define I2C_ENABLE_STATUS 0x9C
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#define I2C_COMP_PARAM_1 0xf4
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#define I2C_COMP_VERSION 0xf8
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#define I2C_COMP_TYPE 0xfc
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#define I2C_RAW_INTR_STAT_RX_UNDER 0x1
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#define I2C_RAW_INTR_STAT_RX_OVER 0x2
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#define I2C_RAW_INTR_STAT_RX_FULL 0x4
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#define I2C_RAW_INTR_STAT_TX_OVER 0x8
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#define I2C_RAW_INTR_STAT_TX_EMPTY 0x10
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/* Default parameters */
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#define I2C_CON_ME (0x1 << 0)
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#define I2C_CON_MS_SS (0x1 << 1)
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#define I2C_CON_MS_FS (0x2 << 1)
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#define I2C_CON_SLAVE_ADR_7BIT (0x0 << 3)
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#define I2C_CON_SLAVE_ADR_10BIT (0x1 << 3)
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#define I2C_CON_MASTER_ADR_7BIT (0x0 << 4)
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#define I2C_CON_MASTER_ADR_10BIT (0x1 << 4)
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#define I2C_CON_RESTART_EN (0x1 << 5)
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#define I2C_CON_SLAVE_DISABLE (0x1 << 6)
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#define I2C_CTR_DEFAULT (I2C_CON_ME | I2C_CON_MASTER_ADR_7BIT | \
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I2C_CON_SLAVE_DISABLE)
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#define I2C_IRQ_NONE_MASK 0x0
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#define I2C_IRQ_ALL_MASK 0x8ff
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#define I2C_TAR_STARTBYTE (0x1 << 10)
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#define I2C_TAR_SPECIAL_STARTBYTE (0x1 << 11)
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#define I2C_TAR_ADR_7BIT (0x0)
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#define I2C_TAR_ADR_10BIT (0x1 << 12)
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#define I2C_SLAVE_DISABLE_DEFAULT 0
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#define I2C_RESTART_EN_DEFAULT 1
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#define I2C_10BITADDR_MASTER_DEFAULT 0
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#define I2C_10BITADDR_SLAVE_DEFAULT 1
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#define I2C_MAX_SPEED_MODE_DEFAULT 3
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#define I2C_MASTER_MODE_DEFAULT 1
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#define I2C_DEFAULT_TAR_ADDR_DEFAULT 0x055
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#define I2C_DEFAULT_SLAVE_ADDR_DEFAULT 0x055
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#define I2C_COMP_VERSION_DEFAULT 0x3131352A
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#define I2C_HS_MASTER_CODE_DEFAULT 1
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#define I2C_SS_SCL_HIGH_COUNT_DEFAULT 0x0190
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#define I2C_SS_SCL_LOW_COUNT_DEFAULT 0x01d6
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#define I2C_FS_SCL_HIGH_COUNT_DEFAULT 0x003c
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#define I2C_FS_SCL_LOW_COUNT_DEFAULT 0x0082
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#define I2C_HS_SCL_HIGH_COUNT_DEFAULT 0x006
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#define I2C_HS_SCL_LOW_COUNT_DEFAULT 0x0010
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#define I2C_RX_TL_DEFAULT 0
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#define I2C_TX_TL_DEFAULT 0
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#define I2C_DEFAULT_SDA_SETUP_DEFAULT 0x64
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#define I2C_DEFAULT_ACK_GENERAL_CALL_DEFAULT 1
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#define I2C_DYNAMI2C_TAR_UPDATE_DEFAULT 1
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#define I2C_RX_BUFFER_DEPTH_DEFAULT 8
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#define I2C_TX_BUFFER_DEPTH_DEFAULT 8
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#define I2C_ADD_ENCODED_PARAMS_DEFAULT 1
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#define I2C_HAS_DMA_DEFAULT 0
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#define I2C_INTR_IO_DEFAULT 0
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#define I2C_HC_COUNT_VALUES_DEFAULT 0
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#define APB_DATA_WIDTH_DEFAULT 0
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#define I2C_SLV_DATA_NACK_ONLY_DEFAULT 0
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#define I2C_USE_COUNTS_DEFAULT 0
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#define I2C_CLK_TYPE_DEFAULT 1
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#define I2C_CLOCK_PERIOD_DEFAULT 10
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/* Raw Interrupt Status */
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#define I2C_IRQ_NONE 0x000
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#define I2C_IRQ_RX_UNDER 0x001
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#define I2C_IRQ_RX_OVER 0x002
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#define I2C_IRQ_RX_FULL 0x004
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#define I2C_IRQ_TX_OVER 0x008
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#define I2C_IRQ_TX_EMPTY 0x010
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#define I2C_IRQ_RD_REQ 0x020
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#define I2C_IRQ_TX_ABRT 0x040
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#define I2C_IRQ_RX_DONE 0x080
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#define I2C_IRQ_ACTIVITY 0x100
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#define I2C_IRQ_STOP_DET 0x200
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#define I2C_IRQ_START_DET 0x400
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#define I2C_IRQ_GEN_CALL 0x800
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#define I2C_IRQ_ALL 0xFFF
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/* Default IRQ Mask Bit Setting */
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#define I2C_IRQ_DEFAULT_MASK (I2C_IRQ_RX_FULL | I2C_IRQ_TX_EMPTY | \
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I2C_IRQ_TX_ABRT | I2C_IRQ_STOP_DET | \
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I2C_IRQ_START_DET | I2C_IRQ_RX_UNDER | \
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I2C_IRQ_RX_OVER | I2C_IRQ_TX_OVER)
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/* Data command stop bit */
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#define I2C_DATA_CMD_RD 0x100
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#define I2C_DATA_CMD_WR 0x000
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#define I2C_DATA_CMD_RESTART 0x400
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#define I2C_DATA_CMD_STOP 0x200
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#define I2C_DATA_CMD_WR_STOP_BIT 0x200
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#define I2C_DATA_CMD_RD_STOP_BIT 0x300
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/* I2C TX Abort Source*/
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#define I2C_ABRT_7B_ADDR_NOACK 0x001
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#define I2C_ABRT_10_ADDR1_NOACK 0x002
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#define I2C_ABRT_10_ADDR2_NOACK 0x004
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#define I2C_ABRT_TXDATA_NOACK 0x008
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#define I2C_ABRT_GCALL_NOACK 0x010
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#define I2C_ABRT_GCALL_READ 0x020
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#define I2C_ABRT_HS_ACKDET 0x040
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#define I2C_ABRT_SBYTE_ACKDET 0x080
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#define I2C_ABRT_HS_NORSTRT 0x100
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#define I2C_ABRT_SBYTE_NORSTRT 0x200
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#define I2C_ABRT_10B_RD_NORSTRT 0x400
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#define I2C_ABRT_MASTER_DIS 0x800
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#define I2C_ABRT_ARB_LOST 0x1000
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#define I2C_ABRT_SLVFLUSH_TXFIFO 0x2000
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#define I2C_ABRT_SLV_ARBLOST 0x5000
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#define I2C_ABRT_SLVRD_INTX 0x8000
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/* I2C_STATUS */
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#define I2C_STATUS_ACTIVITY (0x1 << 0)
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#define I2C_STATUS_TFNF (0x1 << 1)
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#define I2C_STATUS_TFE (0x1 << 2)
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#define I2C_STATUS_RFNE (0x1 << 3)
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#define I2C_STATUS_RFF (0x1 << 4)
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#define I2C_STATUS_MST_ACTIVITY (0x1 << 5)
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#define I2C_STATUS_SLV_ACTIVITY (0x1 << 6)
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/* I2C_ENABLE_STATUS */
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#define IC_ENABLE_STATUS_IC_EN (0x1 << 0)
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/* Interrupts status */
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#define I2C_INTR_RX_UNDER (0x1 << 0)
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#define I2C_INTR_RX_OVER (0x1 << 1)
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#define I2C_INTR_RX_FULL (0x1 << 2)
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#define I2C_INTR_TX_OVER (0x1 << 3)
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#define I2C_INTR_TX_EMPTY (0x1 << 4)
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#define I2C_INTR_RD_REQ (0x1 << 5)
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#define I2C_INTR_TX_ABRT (0x1 << 6)
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#define I2C_INTR_RX_DONE (0x1 << 7)
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#define I2C_INTR_ACTIVITY (0x1 << 8)
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#define I2C_INTR_STOP_DET (0x1 << 9)
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#define I2C_INTR_START_DET (0x1 << 10)
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#define I2C_INTR_GEN_CALL (0x1 << 11)
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#define I2C_INTR_MAX_BITS 12
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/* I2C Component Parameter */
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#define I2C_COMP_PARAM_1_TX_SHIFT (16)
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#define I2C_COMP_PARAM_1_TX_MASK (0xff)
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#define I2C_COMP_PARAM_1_RX_SHIFT (8)
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#define I2C_COMP_PARAM_1_RX_MASK (0xff)
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/* structure holding the instance specific details */
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typedef struct i2c_drv_ctrl
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{
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VXB_DEVICE_ID i2cDev;
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void * i2cHandle;
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SEM_ID i2cDevSem;
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SEM_ID i2cDataSem;
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UINT32 clkFrequency;
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UINT32 busSpeed;
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UINT32 defBusSpeed;
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BOOL polling;
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UINT32 errorStatus;
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UINT32 rxFifoSize;
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UINT32 txFifoSize;
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I2C_MSG * msgs;
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UINT32 num;
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UINT32 totalLen;
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UINT64 timeout; /* unit : us */
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UINT32 pollIrqMask;
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spinlockIsr_t lock;
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UINT32 msgsRxIdx;
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UINT32 msgRxLen;
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UINT8 * msgRxBuf;
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UINT32 fifoRdLvl;
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UINT32 msgsTxIdx;
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UINT32 msgTxLen;
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UINT8 * msgTxBuf;
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ISR_DEFER_QUEUE_ID trxQueueId;
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ISR_DEFER_JOB txIsrDef;
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ISR_DEFER_JOB rxIsrDef;
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} I2C_DRV_CTRL;
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/* I2C controller read and write interface */
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#define FT_I2C_BAR(pCtrl) ((char *)(((VXB_DEVICE_ID)(pCtrl)->i2cDev)->pRegBase[0]))
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#define FT_I2C_HANDLE(pCtrl) ((I2C_DRV_CTRL *)((pCtrl)->i2cHandle))
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INC_vxbFtI2c_H */
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