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/* vxbFtQspi.h - QSPI driver */
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/*
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it;
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef __INCvxbFtQspih
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#define __INCvxbFtQspih
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#include <vxWorks.h>
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#include <config.h>
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#include <sysLib.h>
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#include <vxBusLib.h>
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#include <string.h>
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#include <memLib.h>
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#include <stdlib.h>
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#include <semLibCommon.h>
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#include <hwif/vxbus/vxbSpiLib.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* defines */
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#define FT_QSPI_NAME "ftQspi"
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/* chip selects supported */
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#define QSPI_MAX_CS_NUM (4)
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/* qspi flash controller registers */
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#define REG_BASE_QSPI 0x28014000
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/* register definition */
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#define REG_QSPI_CAP (0x00)
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#define REG_QSPI_RD_CFG (0x04)
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#define REG_QSPI_WR_CFG (0x08)
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#define REG_QSPI_FLUSH (0x0C)
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#define REG_QSPI_CMD_PORT (0x10)
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#define REG_QSPI_ADDR_PORT (0x14)
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#define REG_QSPI_HD_PORT (0x18)
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#define REG_QSPI_LD_PORT (0x1C)
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#define REG_QSPI_FUN_SET (0x20)
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#define REG_QSPI_WIP_RD (0x24)
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#define REG_QSPI_WP (0x28)
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#define REG_QSPI_MODE (0x2C)
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/*QSPI_CAP*/
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#define CAP_FLASH_NUM(data) ((data) << 3)
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#define CAP_FLASH_CAP(data) ((data) << 0)
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/*QSPI_RD_CFG*/
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#define RD_CFG_CMD(data) ((data) << 24)
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#define RD_CFG_THROUGH(data) ((data) << 23)
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#define RD_CFG_TRANSFER(data) ((data) << 20)
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#define RD_CFG_ADDR_SEL(data) ((data) << 19)
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#define RD_CFG_LATENCY(data) ((data) << 18)
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#define RD_CFG_MODE_BYTE(data) ((data) << 17)
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#define RD_CFG_CMD_SIGN(data) ((data) << 9)
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#define RD_CFG_DUMMY(data) ((data) << 4)
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#define RD_CFG_D_BUFFER(data) ((data) << 3)
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#define RD_CFG_SCK_SEL(data) ((data) << 0)
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/*QSPI_WR_CFG*/
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#define WR_CFG_CMD(data) ((data) << 24)
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#define WR_CFG_WAIT(data) ((data) << 9)
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#define WR_CFG_THROUGH(data) ((data) << 8)
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#define WR_CFG_TRANSFER(data) ((data) << 5)
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#define WR_CFG_ADDRSEL(data) ((data) << 4)
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#define WR_CFG_MODE(data) ((data) << 3)
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#define WR_CFG_SCK_SEL(data) ((data) << 0)
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/*QSPI_CMD_PORT*/
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#define CMD_PORT_CMD(data) ((data) << 24)
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#define CMD_PORT_WAIT(data) ((data) << 22)
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#define CMD_PORT_THROUGH(data) ((data) << 21)
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#define CMD_PORT_CS(data) ((data) << 19)
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#define CMD_PORT_TRANSFER(data) ((data) << 16)
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#define CMD_PORT_ADDR(data) ((data) << 15)
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#define CMD_PORT_LATENCY(data) ((data) << 14)
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#define CMD_PORT_DATA_TRANS(data) ((data) << 13)
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#define CMD_PORT_ADDR_SEL(data) ((data) << 12)
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#define CMD_PORT_DUMMY(data) ((data) << 7)
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#define CMD_PORT_P_BUFFER(data) ((data) << 6)
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#define CMD_PORT_RW_NUM(data) ((data) << 3)
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#define CMD_PORT_CLK_SEL(data) ((data) << 0)
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/*QSPI_FUN_SET*/
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#define FUN_SET_CS_HOLD(data) ((data) << 24)
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#define FUN_SET_CS_SETUP(data) ((data) << 16)
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#define FUN_SET_CS_DELAY(data) ((data) << 0)
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/*QSPI_WIP_RD*/
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#define WIP_RD_CMD(data) ((data) << 24)
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#define WIP_RD_TRANSFER(data) ((data) << 3)
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#define WIP_RD_SCK_SEL(data) ((data) << 0)
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/*QSPI_WP*/
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#define WP_EN(data) ((data) << 17)
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#define WP_WP(data) ((data) << 16)
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#define WP_HOLD(data) ((data) << 8)
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#define WP_SETUP(data) ((data) << 0)
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/*QSPI_MODE*/
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#define MODE_VALID(data) ((data) << 8)
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#define MODE_MODE(data) ((data) << 0)
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#define QSPI_FLASH_CAP_4MB 0
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#define QSPI_FLASH_CAP_8MB 1
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#define QSPI_FLASH_CAP_16MB 2
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#define QSPI_FLASH_CAP_32MB 3
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#define QSPI_FLASH_CAP_64MB 4
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#define QSPI_FLASH_CAP_128MB 5
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#define QSPI_FLASH_CAP_256MB 6
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#define QSPI_ADDR_SEL_3 0
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#define QSPI_ADDR_SEL_4 1
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#define QSPI_SCK_DIV_128 0
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#define QSPI_SCK_DIV_2 1
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#define QSPI_SCK_DIV_4 2
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#define QSPI_SCK_DIV_8 3
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#define QSPI_SCK_DIV_16 4
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#define QSPI_SCK_DIV_32 5
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#define QSPI_SCK_DIV_64 6
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#define QSPI_TRANSFER_1_1_1 0
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#define QSPI_TRANSFER_1_1_2 1
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#define QSPI_TRANSFER_1_1_4 2
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#define QSPI_TRANSFER_1_2_2 3
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#define QSPI_TRANSFER_1_4_4 4
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#define QSPI_TRANSFER_2_2_2 5
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#define QSPI_TRANSFER_4_4_4 6
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/* qspi command instruction */
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#define QSPI_FLASH_CMD_WRR 0x01 /* Write status register */
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#define QSPI_FLASH_CMD_PP 0x02 /* Page program */
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#define QSPI_FLASH_CMD_READ 0x03 /* Normal read data bytes */
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#define QSPI_FLASH_CMD_WRDI 0x04 /* Write disable */
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#define QSPI_FLASH_CMD_RDSR1 0x05 /* Read status register */
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#define QSPI_FLASH_CMD_WREN 0x06 /* Write enable */
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#define QSPI_FLASH_CMD_RDSR2 0x07 /* Read status register */
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#define QSPI_FLASH_CMD_FAST_READ 0x0B /* Fast read data bytes */
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#define QSPI_FLASH_CMD_4FAST_READ 0x0C /* Fast read data bytes */
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#define QSPI_FLASH_CMD_4PP 0x12 /* Page program */
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#define QSPI_FLASH_CMD_4READ 0x13 /* Normal read data bytes */
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#define QSPI_FLASH_CMD_P4E 0x20 /* Erase 4kb sector */
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#define QSPI_FLASH_CMD_4P4E 0x21 /* Erase 4kb sector */
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#define QSPI_FLASH_CMD_QPP 0x32 /* Quad Page program */
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#define QSPI_FLASH_CMD_4QPP 0x34 /* Quad Page program */
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#define QSPI_FLASH_CMD_RDCR 0x35 /* Read config register */
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#define QSPI_FLASH_CMD_BE 0x60 /* Bulk erase */
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#define QSPI_FLASH_CMD_RDAR 0x65 /* Read Any Register */
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#define QSPI_FLASH_CMD_QOR 0x6B /* Quad read data bytes */
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#define QSPI_FLASH_CMD_4QOR 0x6C /* Quad read data bytes */
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#define QSPI_FLASH_CMD_WRAR 0x71 /* Write Any Register */
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#define QSPI_FLASH_CMD_RDID 0x9F /* Read JEDEC ID */
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#define QSPI_FLASH_CMD_4BAM 0xB7 /* Enter 4 Bytes Mode */
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#define QSPI_FLASH_CMD_4BE 0xC7 /* Bulk erase */
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#define QSPI_FLASH_CMD_SE 0xD8 /* Sector erase */
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#define QSPI_FLASH_CMD_4SE 0xDC /* Sector erase */
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#define QSPI_FLASH_CMD_4BEX 0xE9 /* Exit 4 Bytes Mode */
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#define QSPI_FLASH_CMD_QIOR 0xEB /* Quad read data bytes */
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#define QSPI_FLASH_CMD_4QIOR 0xEC /* Quad read data bytes */
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/* S25FL256 status register bit defined */
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#define SR_SRWD (0x1 << 7) /* SR write protect */
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#define SR_PERR (0x1 << 6) /* Program err bit */
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#define SR_EERR (0x1 << 5) /* erase err bit */
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#define SR_BP2 (0x1 << 4) /* Block protect 2 */
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#define SR_BP1 (0x1 << 3) /* Block protect 1 */
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#define SR_BP0 (0x1 << 2) /* Block protect 0 */
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#define SR_WEL (0x1 << 1) /* Write enable latch */
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#define SR_WIP (0x1 << 0) /* Write in progress */
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#define WIP_TOUT 300000 /* max 300s */
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/* typedefs */
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/*QSPI_RD_CFG*/
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typedef union
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{
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UINT32 data;
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struct
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{
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UINT32 rd_sck_sel :3; /* 2:0 */
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UINT32 d_buffer :1; /* 3 */
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UINT32 dummy :5; /* 8:4 */
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UINT32 cmd_sign :8; /* 16:9 */
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UINT32 mode_byte :1; /* 17 */
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UINT32 rd_latency :1; /* 18 */
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UINT32 rd_addr_sel :1; /* 19 */
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UINT32 rd_transfer :3; /* 22:20 */
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UINT32 rd_through :1; /* 23 */
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UINT32 rd_cmd :8; /* 31:24 */
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} val;
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} QSPI_RD_CFG_REG_T;
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/*QSPI_WR_CFG*/
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typedef union
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{
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UINT32 data;
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struct
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{
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UINT32 wr_sck_sel :3; /* 2:0 */
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UINT32 wr_mode :1; /* 3 */
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UINT32 wr_addrsel :1; /* 4 */
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UINT32 wr_transfer :3; /* 7:5 */
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UINT32 wr_through :1; /* 8 */
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UINT32 wr_wait :1; /* 9 */
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UINT32 wr_res :14; /* 23:10 */
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UINT32 wr_cmd :8; /* 31:24 */
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} val;
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} QSPI_WR_CFG_REG_T;
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/*QSPI_CMD_PORT*/
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typedef union
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{
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UINT32 data;
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struct
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{
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UINT32 sck_sel :3; /* 2:0 */
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UINT32 rw_mum :3; /* 5:3 */
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UINT32 p_buffer :1; /* 6 */
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UINT32 dummy :5; /* 11:7 */
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UINT32 addr_sel :1; /* 12 */
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UINT32 data_transfer :1;/* 13 */
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UINT32 latency :1; /* 14 */
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UINT32 cmd_addr :1; /* 15 */
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UINT32 transfer :3; /* 18:16 */
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UINT32 cs :2; /* 20:19 */
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UINT32 through :1; /* 21 */
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UINT32 wait :1; /* 22 */
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UINT32 res :1; /* 23 */
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UINT32 cmd :8; /* 31:24 */
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} val;
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} QSPI_CMD_PORT_REG_T;
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/* structure holding the instance specific details */
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typedef struct ft_qspi_drv_ctrl
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{
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VXB_DEVICE_ID pDev;
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void * regBase;
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void * regHandle;
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UINT32 capacity;
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UINT32 clkDiv;
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UINT32 transMode;
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UINT32 addrMode;
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UINT32 spiDevNum;
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UINT32 channel;
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UINT32 initPhase;
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UINT8 * txBuf;
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UINT32 txLen;
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UINT8 * rxBuf;
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UINT32 rxLen;
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BOOL initDone;
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SEM_ID muxSem;
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VXB_SPI_BUS_CTRL vxbSpiCtrl;
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} FT_QSPI_CTRL;
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbFtQspih */
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