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288 lines
12 KiB
288 lines
12 KiB
3 weeks ago
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/* vxbFtcan.h - CAN driver */
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/*
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it;
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef __INCvxbftcanh
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#define __INCvxbftcanh
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define FTCAN_QUEUE_SIZE 1024
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#define VXB_FTCAN_MSG_SIZE 64
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/* CAN payload length and DLC definitions according to ISO 11898-1 */
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#define CAN_MAX_DLC 8
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#define CAN_MAX_DLEN 8
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#define CAN_MAX_CTL 3
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#define CAN_SFF_ID_BITS 11
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#define CAN_EFF_ID_BITS 29
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/* special address description flags for the CAN_ID */
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#define CAN_EFF_FLAG 0x80000000U /* EFF/SFF is set in the MSB */
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#define CAN_RTR_FLAG 0x40000000U /* remote transmission request */
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#define CAN_ERR_FLAG 0x20000000U /* error message frame */
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/* valid bits in CAN ID for frame formats */
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#define CAN_SFF_MASK 0x000007FFU /* standard frame format (SFF) */
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#define CAN_EFF_MASK 0x1FFFFFFFU /* extended frame format (EFF) */
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#define CAN_ERR_MASK 0x1FFFFFFFU /* omit EFF, RTR, ERR flags */
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/* Frame type */
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#define STANDARD_FRAME 0 /* standard frame */
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#define EXTEND_FRAME 1 /* extended frame */
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/*
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* Controller Area Network Identifier structure
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*
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* bit 0-28 : CAN identifier (11/29 bit)
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* bit 29 : error message frame flag (0 = data frame, 1 = error message)
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* bit 30 : remote transmission request flag (1 = rtr frame)
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* bit 31 : frame format flag (0 = standard 11 bit, 1 = extended 29 bit)
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*/
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#define min_t(type, x, y) ({ \
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type __min1 = (x); \
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type __min2 = (y); \
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__min1 < __min2 ? __min1: __min2; })
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/*
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* get_can_dlc(value) - helper macro to cast a given data length code (dlc)
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* to __u8 and ensure the dlc value to be max. 8 bytes.
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*
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* To be used in the CAN netdriver receive path to ensure conformance with
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* ISO 11898-1 Chapter 8.4.2.3 (DLC field)
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*/
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#define get_can_dlc(i) (min_t(UINT8, (i), CAN_MAX_DLC))
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/***ft CAN REGISTER offset*/
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#define FTCAN_CTRL_OFFSET 0x00 /* Global control register */
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#define FTCAN_INTR_OFFSET 0x04 /* Interrupt register */
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#define FTCAN_ARB_RATE_CTRL_OFFSET 0x08 /* Arbitration rate control register */
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#define FTCAN_DAT_RATE_CTRL_OFFSET 0x0C /* Data rate control register */
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#define FTCAN_ACC_ID0_OFFSET 0x10 /* Acceptance identifier0 register */
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#define FTCAN_ACC_ID1_OFFSET 0x14 /* Acceptance identifier1 register */
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#define FTCAN_ACC_ID2_OFFSET 0x18 /* Acceptance identifier2 register */
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#define FTCAN_ACC_ID3_OFFSET 0x1C /* Acceptance identifier3 register */
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#define FTCAN_ACC_ID0_MASK_OFFSET 0x20 /* Acceptance identifier0 mask register */
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#define FTCAN_ACC_ID1_MASK_OFFSET 0x24 /* Acceptance identifier1 mask register */
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#define FTCAN_ACC_ID2_MASK_OFFSET 0x28 /* Acceptance identifier2 mask register */
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#define FTCAN_ACC_ID3_MASK_OFFSET 0x2C /* Acceptance identifier3 mask register */
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#define FTCAN_XFER_STS_OFFSET 0x30 /* Transfer status register */
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#define FTCAN_ERR_CNT_OFFSET 0x34 /* Error counter register */
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#define FTCAN_FIFO_CNT_OFFSET 0x38 /* FIFO counter register */
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#define FTCAN_DMA_CTRL_OFFSET 0x3C /* DMA request control register */
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#define FTCAN_TX_FIFO_OFFSET 0x100 /* TX FIFO shadow register */
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#define FTCAN_RX_FIFO_OFFSET 0x200 /* RX FIFO shadow register */
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/*----------------------------------------------------------------------------*/
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/* CAN register bit masks - FTCAN_<REG>_<BIT>_MASK */
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/*----------------------------------------------------------------------------*/
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/* FTCAN_CTRL mask */
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#define FTCAN_CTRL_XFER_MASK (0x1 << 0) /* RW */ /*Transfer enable*/
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#define FTCAN_CTRL_TXREQ_MASK (0x1 << 1) /* RW */ /*Transmit request*/
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#define FTCAN_CTRL_AIME_MASK (0x1 << 2) /* RW */ /*Acceptance identifier mask enable*/
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/* FTCAN_INTR mask */
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#define FTCAN_INTR_STATUS_MASK (0xFF << 0) /* RO */ /*the interrupt status*/
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#define FTCAN_INTR_BOIS_MASK (0x1 << 0) /* RO */ /*Bus off interrupt status*/
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#define FTCAN_INTR_PWIS_MASK (0x1 << 1) /* RO */ /*Passive warning interrupt status*/
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#define FTCAN_INTR_PEIS_MASK (0x1 << 2) /* RO */ /*Passive error interrupt status*/
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#define FTCAN_INTR_RFIS_MASK (0x1 << 3) /* RO */ /*RX FIFO full interrupt status*/
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#define FTCAN_INTR_TFIS_MASK (0x1 << 4) /* RO */ /*TX FIFO empty interrupt status*/
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#define FTCAN_INTR_REIS_MASK (0x1 << 5) /* RO */ /*RX frame end interrupt status*/
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#define FTCAN_INTR_TEIS_MASK (0x1 << 6) /* RO */ /*TX frame end interrupt status*/
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#define FTCAN_INTR_EIS_MASK (0x1 << 7) /* RO */ /*Error interrupt status*/
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#define FTCAN_INTR_EN_MASK (0xFF << 8) /* RO */ /*the interrupt enable*/
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#define FTCAN_INTR_BOIE_MASK (0x1 << 8) /* RW */ /*Bus off interrupt enable*/
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#define FTCAN_INTR_PWIE_MASK (0x1 << 9) /* RW */ /*Passive warning interrupt enable*/
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#define FTCAN_INTR_PEIE_MASK (0x1 << 10) /* RW */ /*Passive error interrupt enable*/
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#define FTCAN_INTR_RFIE_MASK (0x1 << 11) /* RW */ /*RX FIFO full interrupt enable*/
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#define FTCAN_INTR_TFIE_MASK (0x1 << 12) /* RW */ /*TX FIFO empty interrupt enable*/
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#define FTCAN_INTR_REIE_MASK (0x1 << 13) /* RW */ /*RX frame end interrupt enable*/
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#define FTCAN_INTR_TEIE_MASK (0x1 << 14) /* RW */ /*TX frame end interrupt enable*/
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#define FTCAN_INTR_EIE_MASK (0x1 << 15) /* RW */ /*Error interrupt enable*/
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#define FTCAN_INTR_BOIC_MASK (0x1 << 16) /* WO */ /*Bus off interrupt clear*/
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#define FTCAN_INTR_PWIC_MASK (0x1 << 17) /* WO */ /*Passive warning interrupt clear*/
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#define FTCAN_INTR_PEIC_MASK (0x1 << 18) /* WO */ /*Passive error interrupt clear*/
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#define FTCAN_INTR_RFIC_MASK (0x1 << 19) /* WO */ /*RX FIFO full interrupt clear*/
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#define FTCAN_INTR_TFIC_MASK (0x1 << 20) /* WO */ /*TX FIFO empty interrupt clear*/
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#define FTCAN_INTR_REIC_MASK (0x1 << 21) /* WO */ /*RX frame end interrupt clear*/
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#define FTCAN_INTR_TEIC_MASK (0x1 << 22) /* WO */ /*TX frame end interrupt clear*/
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#define FTCAN_INTR_EIC_MASK (0x1 << 23) /* WO */ /*Error interrupt clear*/
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/* FTCAN_ACC_ID(0-3)_MASK mask */
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#define FTCAN_ACC_IDN_MASK 0x1FFFFFFF /* WO */ /*don’t care the matching */
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/* FTCAN_DAT_RATE_CTRL mask */
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/* FTCAN_ERR_CNT_OFFSET mask */
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#define FTCAN_ERR_CNT_RFN_MASK (0xFF << 0) /* RO */ /*Receive error counter*/
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#define FTCAN_ERR_CNT_TFN_MASK (0xFF << 16)/* RO */ /*Transmit error counter*/
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/* FTCAN_FIFO_CNT_OFFSET mask */
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#define FTCAN_FIFO_CNT_RFN_MASK (0xFF << 0) /* RO */ /*Receive FIFO valid data number*/
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#define FTCAN_FIFO_CNT_TFN_MASK (0xFF << 16)/* RO */ /*Transmit FIFO valid data number*/
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#define FTCAN_ERR_CNT_TFN_SHIFT 16 /* Tx Error Count shift */
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#define FTCAN_FIFO_CNT_TFN_SHIFT 16 /* Tx FIFO Count shift*/
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#define FTCAN_IDR_ID1_SHIFT 21 /* Standard Messg Identifier */
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#define FTCAN_IDR_ID2_SHIFT 1 /* Extended Message Identifier */
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#define FTCAN_IDR_SDLC_SHIFT 14
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#define FTCAN_IDR_EDLC_SHIFT 26
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#define FTCAN_ACC_IDN_SHIFT 18 /*Standard ACC ID shift*/
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#define FTCAN_IDR_ID2_MASK 0x0007FFFE /* Extended message ident */
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#define FTCAN_IDR_ID1_MASK 0xFFE00000 /* Standard msg identifier */
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#define FTCAN_IDR_IDE_MASK 0x00080000 /* Identifier extension */
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#define FTCAN_IDR_SRR_MASK 0x00100000 /* Substitute remote TXreq */
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#define FTCAN_IDR_RTR_MASK 0x00000001 /* Extended frames remote TX request */
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#define FTCAN_IDR_DLC_MASK 0x0003C000 /* Standard msg dlc */
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#define FTCAN_IDR_PAD_MASK 0x00003FFF /* Standard msg padding 1 */
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#define FTCAN_IDR_EDLC_MASK 0x3C000000 /* Extended msg dlc */
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/*#define FTCAN_INTR_EN (FTCAN_INTR_TEIE_MASK | FTCAN_INTR_BOIE_MASK |\
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FTCAN_INTR_RFIE_MASK | FTCAN_INTR_EIE_MASK | \
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FTCAN_INTR_REIE_MASK)*/
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#define FTCAN_INTR_EN (FTCAN_INTR_TEIE_MASK | FTCAN_INTR_REIE_MASK)
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#define FTCAN_INTR_DIS 0x00000000
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#define FTCAN_FIFOFRAME_SIZE 4
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#define FTCAN_TX_FIFO_MAX 0x40
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#define CAN_CALC_MAX_ERROR 50 /* in one-tenth of a percent */
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#define CAN_CALC_SYNC_SEG 1
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#define clamp(x, low, high) (min(max(low, x), high))
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#define CAN_CLK_FREQ 600000000
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#define FWOHCI_CPU_TO_BE32(x) (htobe32((uint32_t)x))
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#define cpu_to_be32p(x) (htobe32((uint32_t)x))
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#define be32_to_cpup(x) (be32toh((uint32_t)x))
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#define DMA_CACHE_DRV_VIRT_TO_PHYS(adrs) \
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CACHE_DRV_VIRT_TO_PHYS(&cacheDmaFuncs, (void *) (adrs))
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/*
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* CAN bit-timing parameters
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*
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* For further information, please read chapter "8 BIT TIMING
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* REQUIREMENTS" of the "Bosch CAN Specification version 2.0"
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* at http://www.semiconductors.bosch.de/pdf/can2spec.pdf.
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*/
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typedef struct can_bittiming {
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UINT bitrate; /* Bit-rate in bits/second */
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UINT sample_point; /* Sample point in one-tenth of a percent */
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UINT tq; /* Time quanta (TQ) in nanoseconds */
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UINT prop_seg; /* Propagation segment in TQs */
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UINT phase_seg1; /* Phase buffer segment 1 in TQs */
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UINT phase_seg2; /* Phase buffer segment 2 in TQs */
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UINT sjw; /* Synchronisation jump width in TQs */
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UINT brp; /* Bit-rate prescaler */
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} FTCAN_BITTIMING;
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/*
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* CAN harware-dependent bit-timing constant
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*
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* Used for calculating and checking bit-timing parameters
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*/
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typedef struct can_bittiming_const {
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char name[16]; /* Name of the CAN controller hardware */
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UINT tseg1_min; /* Time segement 1 = prop_seg + phase_seg1 */
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UINT tseg1_max;
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UINT tseg2_min; /* Time segement 2 = phase_seg2 */
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UINT tseg2_max;
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UINT sjw_max; /* Synchronisation jump width */
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UINT brp_min; /* Bit-rate prescaler */
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UINT brp_max;
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UINT brp_inc;
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} FTCAN_BITTIMING_CONST;
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typedef struct can_frame {
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UINT can_id; /* 32 bit CAN_ID + EFF/RTR/ERR flags */
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UINT8 can_dlc; /* frame payload length in byte (0 .. CAN_MAX_DLEN) */
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UINT8 data[CAN_MAX_DLEN];
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} FTCAN_FRAME;
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typedef struct ftCan_drv_ctrl
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{
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VXB_DEVICE_ID ftCanDev;
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void * ftCanHandle;
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void * ftCanRegbase;
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UINT irq;
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UINT txCfCnt;
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UINT txCfMax;
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FTCAN_BITTIMING ftcan_bittiming;
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MSG_Q_ID ftcanQueue;
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void (*ftCanRecvRtn)(FTCAN_FRAME* pFtCanFrame);
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SEM_ID canTxSem;
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} FTCAN_DRV_CTRL;
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#define FTCAN_BASE(p) ((FTCAN_DRV_CTRL *)(p)->pDrvCtrl)->ftCanRegbase
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#define FTCAN_HANDLE(p) ((FTCAN_DRV_CTRL *)(p)->pDrvCtrl)->ftCanHandle
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#define CSR_READ_4(pDev, addr) \
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vxbRead32 (FTCAN_HANDLE(pDev), (UINT32 *)((char *)FTCAN_BASE(pDev) + addr))
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#define CSR_WRITE_4(pDev, addr, data) \
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vxbWrite32 (FTCAN_HANDLE(pDev), \
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(UINT32 *)((char *)FTCAN_BASE(pDev) + addr), data)
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#define CSR_SETBIT_4(pDev, offset, val) \
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CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) | (val))
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#define CSR_CLRBIT_4(pDev, offset, val) \
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CSR_WRITE_4(pDev, offset, CSR_READ_4(pDev, offset) & (UINT32)(~(val)))
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#define CSR_READ_2(pDev, addr) \
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vxbRead16 (FTCAN_HANDLE(pDev), \
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(UINT16 *)((char *)FTCAN_BASE(pDev) + addr))
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#define CSR_WRITE_2(pDev, addr, data) \
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vxbWrite16 (FTCAN_HANDLE(pDev), \
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(UINT16 *)((char *)FTCAN_BASE(pDev) + addr), data)
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#define CSR_READ_1(pDev, addr) \
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vxbRead8 (FTCAN_HANDLE(pDev), \
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((UINT8 *)FTCAN_BASE(pDev) + addr))
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#define CSR_WRITE_1(pDev, addr, data) \
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vxbWrite8 (FTCAN_HANDLE(pDev), \
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((UINT8 *)FTCAN_BASE(pDev) + addr), data)
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STATUS ftCanRecvCallback
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(
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unsigned char ctlNo,
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void (*ftCanRecvRtn)(FTCAN_FRAME* pFtCanFrame)
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);
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STATUS ftCanSend
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(
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unsigned char ctlNo,
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char * sendbuff,
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int lenth
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);
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#ifdef __cplusplus
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}
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#endif
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#endif /*end of __INCvxbftcanh*/
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