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/* vxbSp25SpiFlash.h - Spansion S25XX serials SPI Flash Head File */
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/*
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* Copyright (c) 2012, 2013 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01d,14Oct13,d_l add cfi offset macros and remove structure cfi_ident
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WRS_PACK_ALIGN(1) attribute to eliminate a warning.
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01c,01feb13,ylu Change the parameter flash from pointer to
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struct in pDrvCtrl.
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01b,24jan13,y_y Added support for SST chips.
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01a,14sep12,y_y created.
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*/
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#ifndef __INCvxbSp25SpiFlashh
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#define __INCvxbSp25SpiFlashh
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include <../h/flash/vxbFlash.h>
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#include <../h/flash/vxbFlashCommon.h>
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/* defines */
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/* macros for mutex */
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#define SPIFLASH_MUTEX_OPT SEM_Q_PRIORITY | \
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SEM_DELETE_SAFE | \
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SEM_INVERSION_SAFE
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#define SPIFLASH_LOCK(x) semTake((SEM_ID)(x), WAIT_FOREVER)
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#define SPIFLASH_UNLOCK(x) semGive((SEM_ID)(x))
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/* manufacturer ID */
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#define SPANSION (0x01) /* The manufacturer id for SPANSION */
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#define FUJITSU (0x04) /* The manufacturer id for FUJITSU */
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#define NEC (0x10) /* The manufacturer id for NEC */
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#define EON (0x1C) /* The manufacturer id for EON */
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#define ATMEL (0x1F) /* The manufacturer id for ATMEL */
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#define MICRO (0x20) /* The manufacturer id for MICRO */
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#define AMIC (0x37) /* The manufacturer id for AMIC */
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#define ESI (0x4A) /* The manufacturer id for ESI */
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#define INTEL (0x89) /* The manufacturer id for INTEL */
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#define ESMT (0x8C) /* The manufacturer id for ESMT */
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#define TOSHIBA (0x98) /* The manufacturer id for TOSHIBA */
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#define PMC (0x9D) /* The manufacturer id for PMC */
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#define HYUNDAI (0xAD) /* The manufacturer id for HYUNDAI */
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#define SHARP (0xB0) /* The manufacturer id for SHARP */
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#define SST (0xBF) /* The manufacturer id for SST */
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#define MXIC (0xC2) /* The manufacturer id for MXIC */
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#define SAMSUNG (0xEC) /* The manufacturer id for SAMSUNG */
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#define WINBOND (0xEF) /* The manufacturer id for SAMSUNG */
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#define GIGADEVICE (0xC8) /* The manufacturer id for GigaDevice */
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#define MISSING (0xFF)
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/* Spansion SPI Flash Commands info */
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#define SPI_WRSR_CMD (0x01)
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#define SPI_WRR_CMD (0x01)
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#define SPI_PP_CMD (0x02)
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#define SPI_READ_CMD (0x03)
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#define SPI_WRDI_CMD (0x04)
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#define SPI_RDSR_CMD (0x05)
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#define SPI_WREN_CMD (0x06)
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#define SPI_RDSR2_CMD (0x07)
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#define SPI_FAST_READ_CMD (0x0B)
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#define SPI_FAST_READ_4B_CMD (0x0C)
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#define SPI_FAST_READ_DDR_CMD (0x0D)
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#define SPI_FAST_READ_DDR_4B_CMD (0x0E)
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#define SPI_PP_4B_CMD (0x12)
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#define SPI_READ_4B_CMD (0x13)
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#define SPI_RABT_CMD (0x14)
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#define SPI_WABT_CMD (0x15)
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#define SPI_RBNK_CMD (0x16)
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#define SPI_WBNK_CMD (0x17)
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#define SPI_RECC_CMD (0x18)
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#define SPI_P4E_CMD (0x20)
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#define SPI_P4E_4B_CMD (0x21)
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#define SPI_RASP_CMD (0x2B)
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#define SPI_WASP_CMD (0x2F)
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#define SPI_CLSR_CMD (0x30)
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#define SPI_QPP_CMD (0x32)
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#define SPI_QPP_4B_CMD (0x34)
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#define SPI_RCR_CMD (0x35)
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#define SPI_DUALIO_RD_CMD (0x3B)
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#define SPI_DUALIO_RD_4B_CMD (0x3C)
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#define SPI_P8E_CMD (0x40)
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#define SPI_DLPRD_CMD (0x41)
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#define SPI_OTPP_CMD (0x42)
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#define SPI_PROGRAM_SECURITY_CMD (0x42) /* Program Security Register */
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#define SPI_PNVDLR_CMD (0x43)
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#define SPI_ERASE_SECURITY_CMD (0x44) /* Erase Security Register */
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#define SPI_READ_SECURITY_CMD (0x48) /* Read Security Register */
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#define SPI_WVDLR_CMD (0x4A)
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#define SPI_OTPR_CMD (0x4B)
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#define SPI_READ_UNIQUE_ID_CMD (0x4B) /* Read Unique ID Number */
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#define SPI_P8E_4B_CMD (0x4C)
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#define SPI_WRITE_VOLATILE_CMD (0x50) /* Write Enable for Volatile Status Register */
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#define SPI_BE32KB_CMD (0x52) /* Block Erase 32KB */
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#define SPI_READ_SFDP_CMD (0x5A) /* Read Serial Flash Discoverable Parameter Register */
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#define SPI_BE1_CMD (0x60)
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#define SPI_QUADIO_RD_CMD (0x6B)
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#define SPI_QUADIO_RD_4B_CMD (0x6C)
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#define SPI_ERS_SSP_CMD (0x75) /* Erase / Program Suspend */
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#define SPI_SETBURSTWRAP_CMD (0x77) /* Set Burst with Wrap */
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#define SPI_ERS_RES_CMD (0x7A) /* Erase / Program Resume */
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#define SPI_PRG_SSP_CMD (0x85)
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#define SPI_PRG_RES_CMD (0x8A)
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#define SPI_READID_90_CMD (0x90)
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#define SPI_READID_DUAL_CMD (0x92)
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#define SPI_READID_QUAD_CMD (0x94)
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#define SPI_RDID_9F_CMD (0x9F)
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#define SPI_READ_ID_9F_CMD (0x9F)
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#define SPI_MPM_CMD (0xA3)
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#define SPI_PLBWR_CMD (0xA6)
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#define SPI_PLBRD_CMD (0xA7)
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#define SPI_READ_ID_AB_CMD (0xAB)
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#define SPI_RDID_AB_CMD (0xAB)
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#define SPI_RES_CMD (0xAB)
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#define SPI_SP_CMD (0xB9)
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#define SPI_DP_CMD (0xB9)
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#define SPI_DUALIO_HPRD_CMD (0xBB)
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#define SPI_DUALIO_HPRD_4B_CMD (0xBC)
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#define SPI_DDR_DUALIO_HPRD_CMD (0xBD)
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#define SPI_DDR_DUALIO_HPRD_4B_CMD (0xBE)
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#define SPI_BE_CMD (0xC7)
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#define SPI_SE_CMD (0xD8)
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#define SPI_SE_4B_CMD (0xDC)
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#define SPI_DYB_RD_CMD (0xE0)
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#define SPI_DYB_PG_CMD (0xE1)
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#define SPI_PPB_RD_CMD (0xE2)
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#define SPI_PPB_PG_CMD (0xE3)
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#define SPI_OCTALWORDREADQUAD_CMD (0xE3) /* Octal Word Read Quad */
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#define SPI_PPB_ERS_CMD (0xE4)
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#define SPI_WDBRD_CMD (0xE5)
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#define SPI_WDBP_CMD (0xE6)
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#define SPI_RPWD_CMD (0xE7)
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#define SPI_WORDREADQUAD_CMD (0xE7) /* Word Read Quad */
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#define SPI_WPWD_CMD (0xE8)
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#define SPI_PWDU_CMD (0xE9)
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#define SPI_QUADIO_HPRD_CMD (0xEB)
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#define SPI_QUADIO_HPRD_4B_CMD (0xEC)
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#define SPI_DDR_QUADIO_HPRD_CMD (0xED)
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#define SPI_DDR_QUADIO_HPRD_4B_CMD (0xEE)
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#define SPI_SOFTWARE_RESET (0xF0)
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#define SPI_RMB_CMD (0xFF)
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#define SPI_READMODE_RESET_CMD (0xFF) /* Continuous Read Mode Reset */
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/* SST OPERATION INSTRUCTIONS */
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#define SST_AAI_WORD_CMD (0xAD) /* Auto Address Increment Programming*/
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/* Fast read */
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#undef FAST_READ
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#ifdef FAST_READ
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#define SPI_READ_OPCODE SPI_FAST_READ_CMD
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#define READ_CMD_BYTE 5
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#else
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#define SPI_READ_OPCODE SPI_READ_CMD
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#define READ_CMD_BYTE 4
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#endif
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/* Generic JEDEC ID get func */
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#ifndef JEDEC_ID_GET
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#define JEDEC_ID_GET(pDev, jedecId, length) \
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do \
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{ \
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UINT8 cmd = SPI_READ_ID_9F_CMD; \
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SPI_TRANSFER transInfo; \
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memset(&transInfo, 0, sizeof(SPI_TRANSFER)); \
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transInfo.txBuf = &cmd; \
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transInfo.txLen = 1; \
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transInfo.rxBuf = jedecId; \
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transInfo.rxLen = length; \
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(void)vxbSpiTransfer (pDev, &transInfo); \
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} \
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while (0)
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#endif
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/* Spi Flash flags features */
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#define NO_JEDEC_ID 0x0001
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#define JEDECID_NO_EXT 0x0002
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/* define macros */
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#define SR_SRWD 0x80
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#define SR_BP2 0x10
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#define SR_BP1 0x08
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#define SR_BP0 0x04
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#define SR_WEL 0x02
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#define SR_WIP 0x01
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#define MAX_CMD_SIZE 5
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#define TIMEOUT 2000000
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#define SPI_3B_MAX 0x1000000
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#define DEFAULT_PP_TIME 500
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/*
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* Device Interface Code Assignments from the "Common Flash Memory Interface
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* Publication 100" dated December 1, 2001.
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*/
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#define CFI_INTERFACE_X8_ASYNC 0x0000
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#define CFI_INTERFACE_X16_ASYNC 0x0001
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#define CFI_INTERFACE_X8_BY_X16_ASYNC 0x0002
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#define CFI_INTERFACE_X32_ASYNC 0x0003
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#define CFI_INTERFACE_SINGLE_IO_SPI_ASYNC 0x0004
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#define CFI_INTERFACE_MULTI_IO_SPI_ASYNC 0x0005
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#define CFI_INTERFACE_NOT_ALLOWED 0xff
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/* byte Swap */
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#if (_BYTE_ORDER == _BIG_ENDIAN)
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#define CPU_TO_SPI_FLASH_16(bigEndian, x) \
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((bigEndian != 0) ? (UINT16) (x) : vxbSwap16 (x))
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#define CPU_TO_SPI_FLASH_32(bigEndian, x) \
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((bigEndian != 0) ? (UINT32) (x) : vxbSwap32 (x))
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#define SPI_FLASH_LE16_TO_CPU(x) vxbSwap16 (x)
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#define SPI_FLASH_LE32_TO_CPU(x) vxbSwap32 (x)
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#else
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#define CPU_TO_SPI_FLASH_16(bigEndian, x) \
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((bigEndian == 0) ? (UINT16) (x) : vxbSwap16 (x))
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#define CPU_TO_SPI_FLASH_32(bigEndian, x) \
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((bigEndian == 0) ? (UINT32) (x) : vxbSwap32 (x))
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#define SPI_FLASH_LE16_TO_CPU(x) ((UINT16) (x))
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#define SPI_FLASH_LE32_TO_CPU(x) ((UINT32) (x))
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#endif /* _BIG_ENDIAN */
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#define SPI_FLASH_16_TO_CPU(bigEndian, x) CPU_TO_SPI_FLASH_16 (bigEndian, x)
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#define SPI_FLASH_32_TO_CPU(bigEndian, x) CPU_TO_SPI_FLASH_32 (bigEndian, x)
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/* Basic Query Structure */
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#define SPI_CFI_ERASE_REGIONS 4
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#define CFI_MAGIC_STR_LEN 3
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#define SPI_CFI_OFFSET 0x10 /* Start of CFI data in RDID result */
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/*
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* Erase Block(s) within this Region are (blkSize) times 256 bytes
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* in size. The value blkSize = 0 is used for 128-byte block size.
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*/
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#define CFI_BLK_SIZE(x) (((x) == 0) ? 0x80 : ((x) << 8))
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#define OFF_QS (0)
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#define OFF_PCS (3)
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#define OFF_PETA (5)
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#define OFF_ACS (7)
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#define OFF_AETA (9)
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#define OFF_VCCMIN (11)
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#define OFF_VCCMAX (12)
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#define OFF_VPPMIN (13)
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#define OFF_VPPMAX (14)
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#define OFF_WTO (15)
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#define OFF_WBTO (16)
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#define OFF_BETO (17)
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#define OFF_CETO (18)
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#define OFF_WTOM (19)
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#define OFF_WBTOM (20)
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#define OFF_BETOM (21)
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#define OFF_CETOM (22)
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#define OFF_DS (23)
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#define OFF_ID (24)
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#define OFF_WBL (26)
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#define OFF_RN (28)
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#define OFF_ERI0 (29)
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#define OFF_ERI1 (33)
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#define OFF_ERI2 (37)
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#define OFF_ERI3 (41)
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#define SPI_CFI_LEN (45)
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struct cfi_ident
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{
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/* CFI Query Identification String */
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UINT8 qryStr[CFI_MAGIC_STR_LEN]; /* Query-unique ASCII string */
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UINT16 priCmdSet; /* Primary Vendor Command Set and Control */
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/* Interface ID code */
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UINT16 priExtTblAdrs; /* Address for Primary Algorithm extended Query */
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/* table */
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UINT16 altCmdSet; /* Alternate Vendor Command Set and Control */
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/* Interface ID code */
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UINT16 altExtTblAdrs; /* Address for Alternate Algorithm extended Query */
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/* table */
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/* CFI Query System Interface Information */
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/* Vcc Logic Supply Minimum/Maximum Write/Erase voltage */
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UINT8 vccMin;
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UINT8 vccMax;
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/* Vpp [Programming] Supply Minimum/Maximum Write/Erase voltage */
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UINT8 vppMin;
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UINT8 vppMax;
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/*
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* Typical timeout per single byte/word write (buffer write count = 1),
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* 2**N microsecond
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*/
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UINT8 wrTimeout;
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/*
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* Typical timeout for minimum-size buffer write, 2**N microsecond
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* (if supported; 00h=not supported)
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*/
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UINT8 wrBufTimeout;
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/* Typical timeout per individual block erase, 2**N millisecond */
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UINT8 blkEraseTimeout;
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/*
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* Typical timeout for full chip erase, 2**N millisecond
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* (if supported; 00h=not supported)
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*/
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UINT8 chipEraseTimeout;
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/* Maximum timeout for byte/word write, 2**N times typical */
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UINT8 wrTimeoutMax;
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/* Maximum timeout for buffer write, 2**N times typical */
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UINT8 wrBufTimeoutMax;
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/* Maximum timeout per individual block erase, 2**N times typical */
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UINT8 blkEraseTimeoutMax;
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/* Maximum timeout per individual block erase, 2**N times typical */
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UINT8 chipEraseTimeoutMax;
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/* Device Geometry Definition */
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UINT8 devSize; /* Device Size(2**n in number of bytes) */
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UINT16 ifDesc; /* Flash Device Interface description */
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UINT16 wrBufLen; /* Maximum number of bytes in multi-byte write = 2**n */
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UINT8 regionNum; /* Number of Erase Block Regions within device */
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UINT32 EraseRegionInfo[SPI_CFI_ERASE_REGIONS];
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};
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/* CFI standard query structure region information */
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struct cfi_region
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{
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UINT16 blkSize; /* Erase Block Size devided by 256 */
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UINT16 blkNum; /* Number of Erase Blocks - 1 */
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};
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/* typedef */
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typedef struct spiFlash_info
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{
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char name[MAX_DRV_NAME_LEN];
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UINT16 manuId;
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UINT16 devId;
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UINT16 extId;
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UINT16 pageSize;
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UINT32 sectorSize;
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UINT32 sectorNum;
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UINT32 flags;
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}SPIFLASH_INFO;
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/* SPI_NOR_FLASH device struct */
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typedef struct spi_norFlash_drv_ctrl
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{
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VXB_DEVICE_ID pDev;
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char type[MAX_DRV_NAME_LEN];
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int index;
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UINT32 chipSize;
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UINT32 ppTime;
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UINT8 * pWrBuf;
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SEM_ID muteSem; /* operation semaphore */
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UINT8 addrWidth; /* 4-byte or 3-byte address */
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BOOL isProbeOk; /* whether probe ok */
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FLASH_CHIP mtd; /* FileSystem used */
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VXB_SPI_MAST_SPEC * specialInfo;
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SPIFLASH_INFO flash;
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} SPI_FLASH_DEV;
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#define PageSize(x) ((x)->flash.pageSize)
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#define SectorSize(x) ((x)->flash.sectorSize)
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#define SectorNum(x) ((x)->flash.sectorNum)
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#define ChipSize(x) ((x)->chipSize)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCvxbSp25SpiFlashh */
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