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/* ft2000-4.h - FT2000A/4 chip file */
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/*
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it;
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#ifndef __INCft2000_4_h
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#define __INCft2000_4_h
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#define FT2000_UART_CLK (48000000) /* UART clock */
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#define UART_0_BASE_ADR (0x28000000) /* UART 0 base address */
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#define UART_1_BASE_ADR (0x28001000) /* UART 1 base address */
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#define UART_2_BASE_ADR (0x28002000) /* UART 2 base address */
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#define UART_3_BASE_ADR (0x28003000) /* UART 3 base address */
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#define GPIO_0_BASE_ADR (0x28004000) /* GPIO 0 base address */
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#define GPIO_1_BASE_ADR (0x28005000) /* GPIO 1 base address */
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#define GIC_BASE_ADR (0x29900000)
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#define INT_VEC_UART0INTR 38
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#define INT_VEC_UART1INTR 39
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#define INT_VEC_UART2INTR 40
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#define INT_VEC_UART3INTR 41
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#define INT_VEC_GPIO0INTR 42
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#define INT_VEC_GPIO1INTR 43
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/*CAN Baudrate*/
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enum can_bitrate{
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CAN_BRATE_5 = 5, /* */
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CAN_BRATE_10 = 10, /* */
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CAN_BRATE_20 = 20, /* */
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CAN_BRATE_40 = 40, /* */
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CAN_BRATE_50 = 50, /* */
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CAN_BRATE_80 = 80, /* */
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CAN_BRATE_100 = 100, /* */
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CAN_BRATE_125 = 125, /* */
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CAN_BRATE_200 = 200, /* */
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CAN_BRATE_250 = 250, /* */
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CAN_BRATE_400 = 400, /* */
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CAN_BRATE_500 = 500, /* */
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CAN_BRATE_800 = 800, /* */
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CAN_BRATE_1000 = 1000, /* */
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};
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#define FT2000_I2C_CLK (48000000) /* I2C clock */
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#define I2C_0_INTR_IRQ (44)
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#define I2C_1_INTR_IRQ (45)
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#define I2C_2_INTR_IRQ (46)
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#define I2C_3_INTR_IRQ (47)
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#define REG_I2C0_BASE (0x28006000)
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#define REG_I2C1_BASE (0x28007000)
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#define REG_I2C2_BASE (0x28008000)
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#define REG_I2C3_BASE (0x28009000)
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#define FT_SDHC0_BASE (0x28207c00)
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#define FTCAN_BRATE_DEFAULT (CAN_BRATE_1000*1000)
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#define FTCAN0_BASE 0x28207000
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#define FTCAN0_IRQ 119
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#define FTCAN0_BITRATE FTCAN_BRATE_DEFAULT
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#define FTCAN1_BASE 0x28207400
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#define FTCAN1_IRQ 123
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#define FTCAN1_BITRATE FTCAN_BRATE_DEFAULT
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#define FTCAN2_BASE 0x28207800
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#define FTCAN2_IRQ 124
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#define FTCAN2_BITRATE FTCAN_BRATE_DEFAULT
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#define FT2000_SPI_CLK (48000000) /* SPI clock */
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#define FTSPI0_BASE 0x2800c000
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#define FTSPI0_IRQ 50
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#define FTSPI1_BASE 0x28013000
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#define FTSPI1_IRQ 51
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/* pad pin multi-function demux component */
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#define PIN_DEMUX_BASE 0x28180000
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#define REG200 0x200
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#define REG204 0x204
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#define REG208 0x208
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#define REG210 0x210
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#define REG214 0x214
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#define REG218 0x218
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#define CAN_TXD_0 (1<<24)
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#define CAN_RXD_0 (1<<12)
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#define CAN_TXD_1 (1<<20)
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#define CAN_RXD_1 (1<<8)
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#define CAN_TXD_2 (1<<16)
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#define CAN_RXD_2 (1<<4)
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#define I2C_2_SCL (2<<8) /* can_rxd_1 = I2C_2_scl: ONLY choose one component! */
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#define I2C_2_SDA (2<<4) /* can_rxd_2 = i2c_2_sda */
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#define FUNC1_GPIO1_PORTA_5 (1<<16)
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#define FUNC1_GPIO1_PORTA_6 (1<<12)
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/*
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* FT2004C size usage
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* 0x000_40000000~0x000_4FFFFFFF 256MB Config
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* 0x000_50000000~0x000_57FFFFFF 128MB i/o
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* 0x000_58000000~0x000_7FFFFFFF 640MB mem32
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* 0x010_00000000~0x01F_FFFFFFFF 64GB mem64
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*/
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#define FT_PCI_CONFIG_ADDR 0x40000000
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#define FT_PCI_CONFIG_LEN 0x10000000 /*256MB*/
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#define CPU_IO_SPACE_OFFSET 0x50000000
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#define FT_SECONDARY_BOOT_ADDR 0x8007fff0
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typedef unsigned char u8, __u8, unchar;
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typedef char s8, __s8;
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typedef unsigned short u16, __u16, __be16;
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typedef short s16, __s16;
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typedef unsigned int u32, __u32, __be32, uint;
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typedef int s32, __s32;
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typedef unsigned long long u64;
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/* ARM ARCH7 later. */
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#define ISB __asm__ volatile ("isb sy" : : : "memory")
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#define DSB __asm__ volatile ("dsb sy" : : : "memory")
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#define DMB __asm__ volatile ("dmb sy" : : : "memory")
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#define isb() ISB
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#define dsb() DSB
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#define dmb() DMB
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/*
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* Generic virtual read/write. Note that we don't support half-word
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* read/writes. We define __arch_*[bl] here, and leave __arch_*w
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* to the architecture specific code.
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*/
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#define __arch_getb(a) (*(volatile unsigned char *)(a))
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#define __arch_getw(a) (*(volatile unsigned short *)(a))
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#define __arch_getl(a) (*(volatile unsigned int *)(a))
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#define __arch_getq(a) (*(volatile unsigned long long *)(a))
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#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
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#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
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#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
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#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
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#define __raw_writeb(v,a) __arch_putb(v,a)
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#define __raw_writew(v,a) __arch_putw(v,a)
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#define __raw_writel(v,a) __arch_putl(v,a)
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#define __raw_writeq(v,a) __arch_putq(v,a)
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#define __raw_readb(a) __arch_getb(a)
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#define __raw_readw(a) __arch_getw(a)
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#define __raw_readl(a) __arch_getl(a)
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#define __raw_readq(a) __arch_getq(a)
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/*
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* TODO: The kernel offers some more advanced versions of barriers, it might
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* have some advantages to use them instead of the simple one here.
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*/
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#define mb() dsb()
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#define __iormb() dmb()
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#define __iowmb() dmb()
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#define writeb(v,c) ({ u8 __v = v; __iowmb(); __arch_putb(__v,c); __v; })
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#define writew(v,c) ({ u16 __v = v; __iowmb(); __arch_putw(__v,c); __v; })
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#define writel(v,c) ({ u32 __v = v; __iowmb(); __arch_putl(__v,c); __v; })
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#define readb(c) ({ u8 __v = __arch_getb(c); __iormb(); __v; })
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#define readw(c) ({ u16 __v = __arch_getw(c); __iormb(); __v; })
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#define readl(c) ({ u32 __v = __arch_getl(c); __iormb(); __v; })
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/* assembly functions */
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void sys_icc_igrpen1_set(unsigned int);
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unsigned int sys_icc_igrpen1_get(void);
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void sys_icc_ctlr_set(unsigned int);
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unsigned int sys_icc_hppir1_get(void);
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void sys_icc_eoir1_set(unsigned int);
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void sys_icc_pmr_set(unsigned int);
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unsigned int sys_icc_iar1_get(void);
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void sys_icc_dir_set(unsigned int);
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void sys_icc_bpr1_set(unsigned int);
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unsigned int sys_icc_sre_get(void);
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unsigned int vxMpidrGet();
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unsigned int sys_dfar_get();
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unsigned int sys_dfsr_get();
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unsigned int sys_ifar_get();
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unsigned int sys_ifsr_get();
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#ifdef __cplusplus
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}
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#endif
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#endif /* __INCft2000_4_h */
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