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654 lines
26 KiB
654 lines
26 KiB
/* vxbAhciStorage.h - AHCI SATA disk controller header */
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/*
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* Copyright (c) 2011-2016, 2018 Wind River Systems, Inc.
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*
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* The right to copy, distribute, modify or otherwise make use
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* of this software may be licensed only pursuant to the terms
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* of an applicable Wind River license agreement.
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*/
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/*
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modification history
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--------------------
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01j,25sep18,syt add bit fields definitions for FIS-based Switching
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Control Register (VXW6-86615)
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01i,17jun16,hma fix the sata test error (VXW6-83903)
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01h,27feb15,m_y reduce the default watch dog time (VXW6-84034)
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01g,19nov14,m_y modify watch dog time (VXW6-83672)
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01f,18jun13,m_y add code to support XBD sched policy and NCQ
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01e,02jul12,sye fixed static analyze issue. (WIND00354953)
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01d,06apr12,sye fixed compile issue when included by a CPP file. (WIND00342562)
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01c,15mar12,e_d added portPhyNum in AHCI_DRIVE struct
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to identify physical port. (WIND00335995)
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01b,29feb12,syt added macro AHCI_REG_HANDLE_SWAP to fit big endian
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type register bank.
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01a,22oct11,e_d adapted from vxbintelAhciStorage.h version 01s.
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*/
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#ifndef __INCvxbAhciStorageh
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#define __INCvxbAhciStorageh
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#ifndef _ASMLANGUAGE
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/* includes */
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#include <dosFsLib.h>
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#include <blkIo.h>
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#include <semLib.h>
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#include <wdLib.h>
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#include <drv/xbd/xbd.h> /* XBD library header */
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#include <drv/erf/erfLib.h> /* event frame work library header */
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#include "vxbSataLib.h"
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#include <../src/hwif/h/storage/vxbSataXbd.h>
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#include <lstLib.h>
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#ifndef _ASMLANGUAGE
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/* defines */
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#define AHCI_NAME "ahciSata"
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enum
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{
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INTEL_VENDOR_ID = 0x8086,
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ICH6_DEVICE_ID = 0x2654,
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ICH6R_DEVICE_ID = 0x2652,
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ICH6M_DEVICE_ID = 0x2653,
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ESB2_DEVICE_ID = 0x2681,
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ICH7M_DEVICE_ID = 0x27c5,
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ICH8M_DEVICE_ID = 0x2829,
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ICH9R_DEVICE_ID = 0x2922,
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ICH9M_DEVICE_ID = 0x2929,
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ICH10R_DEVICE_ID = 0x3a22,
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ICH10_DEVICE_ID = 0x3a02,
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PCH_6PORT_DEVICE_ID_0 = 0x3b22,
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PCH_6PORT_DEVICE_ID_1 = 0x3b2f,
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PCH_PATSBURG_DEVICE_ID = 0x1D02,
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PCH_COUGAR_POINT_DEVICE_ID = 0x1c03,
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IOH_TOPCILFF_DEVICE_ID = 0x880b
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};
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#define HIGHPOINT_VERDOR_ID 0x1103
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#define HIGHPOINT_ROCKETRAID640L_DEVICE_ID 0x0641
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#define AHCI_CLASS_ID 0x01060100
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#define AHCI_MAX_CTRLS 6 /* max number of ATA controller */
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#define AHCI_MAX_DRIVES 32 /* max number of SATA drives/controller */
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#define AHCI_MAX_CMD_SLOTS 32 /* max number of command slots per port */
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#define AHCI_MAX_PRD_ENTRIES 256/* max prd entries modify from 16 to 256 */
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#define AHCI_ATAPI_MAX_CMD_LENGTH 16 /* maximum length in bytes of a ATAPI command */
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/* device types */
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#define AHCI_TYPE_NONE 0x00 /* device is faulty or not present */
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#define AHCI_TYPE_ATA 0x01 /* ATA device */
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#define AHCI_TYPE_ATAPI 0x02 /* ATAPI device */
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#define AHCI_TYPE_INIT 255 /* device must be identified */
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/* device states */
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#define AHCI_DEV_OK 0 /* device is OK */
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#define AHCI_DEV_NONE 1 /* device absent or does not respond */
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#define AHCI_DEV_DIAG_F 2 /* device diagnostic failed */
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#define AHCI_DEV_PREAD_F 3 /* read device parameters failed */
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#define AHCI_DEV_MED_CH 4 /* medium have been changed */
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#define AHCI_DEV_NO_BLKDEV 5 /* No block device available */
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#define AHCI_DEV_INIT 255 /* uninitialized device */
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typedef struct ahciPrd
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{
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UINT32 dataBaseAddressLow;
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UINT32 dataBaseAddressHigh;
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UINT32 reserved;
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UINT32 dataByteCountInterrupt;
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} AHCI_PRD;
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typedef struct ahciCmdTable
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{
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UINT8 commandFis[64];
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UINT8 atapiCommand[16];
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UINT8 reserved[48];
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AHCI_PRD prd[AHCI_MAX_PRD_ENTRIES];
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} AHCI_CMD_TABLE;
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typedef struct ahciCmdList
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{
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UINT32 flagsPrdLength;
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UINT32 recvByteCount;
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UINT32 cmdTableAddressLow;
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UINT32 cmdTableAddressHigh;
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UINT32 reserved0;
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UINT32 reserved1;
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UINT32 reserved2;
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UINT32 reserved3;
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} AHCI_CMD_LIST;
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typedef struct ahciRecvFis
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{
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UINT8 dmaSetupFis[28];
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UINT8 reserved0[4];
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UINT8 pioSetupFis[20];
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UINT8 reserved1[12];
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UINT8 d2hRegisterFis[20];
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UINT8 reserved2[4];
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UINT8 setDeviceBitsFis[8];
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UINT8 unknownFis[64];
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UINT8 reserved3[96];
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} AHCI_RECV_FIS;
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#if _BYTE_ORDER == _BIG_ENDIAN
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# define AHCI_SWAP(x) LONGSWAP(x)
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# define AHCI_REG_HANDLE_SWAP(x) VXB_HANDLE_SWAP(x)
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#else
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# define AHCI_SWAP(x) (x)
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# define AHCI_REG_HANDLE_SWAP(x) (x)
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#endif /* _BYTE_ORDER == _BIG_ENDIAN */
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typedef struct ahciDrive
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{
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SATA_DEVICE sataPortDev;
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void * regsAddr;
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AHCI_CMD_LIST *commandList;
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AHCI_RECV_FIS *recvFis;
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AHCI_CMD_TABLE *commandTable;
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SEM_ID syncSem[AHCI_MAX_CMD_SLOTS];
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SEM_ID muteSem;
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SEM_ID tagMuteSem;
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SEM_ID queueSlotSem;
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SEM_ID monSyncSem;
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UINT32 cmdStarted;
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int intCount; /* interrupt count */
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UINT32 intStatus; /* interrupt status */
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UINT32 intError; /* interrupt status */
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int taskFileErrorCount; /* Error counters*/
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int timeoutErrorCount; /* Error counters */
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BOOL portError;
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int nextTag;
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BOOL queuedMode;
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int queueDepth;
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WDOG_ID wdgId;
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BOOL wdgOkay;
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int semTimeout; /* timeout ticks for sync semaphore */
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int wdgTimeout; /* timeout ticks for watch dog */
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UINT8 state;
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UINT8 portPhyNum; /* physical port number */
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UINT32 initActive;
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UINT32 slotBit; /* use tagMuteSem to protect */
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SEM_ID portCmdSem; /* mutex for commands to the port*/
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UINT32 attr; /* attribute of the current transfer*/
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} AHCI_DRIVE;
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typedef struct vxbAhciMsg
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{
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SATA_HOST * pCtrl; /* AHCI controller structure pointer */
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char drive; /* drive number */
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char msgId; /* message ID */
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} VXB_AHCI_MSG;
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#define VXB_AHCI_MSG_SIZE sizeof(VXB_AHCI_MSG)
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/* AHCI SATA Controller Generic Host Control Register Offsets */
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#define AHCI_CAP 0x00 /* Host Capabilities */
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#define AHCI_GHC 0x04 /* Global Host Control */
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#define AHCI_IS 0x08 /* Interrupt Status */
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#define AHCI_PI 0x0C /* Ports Implemented */
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#define AHCI_VS 0x10 /* Version */
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/* AHCI SATA Controller Generic Host Control Register WIDTH */
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#define AHCI_PI_WIDTH 0x20 /*Ports Implemented Register width*/
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/* AHCI SATA Controller Generic Host Control Register Offsets */
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#define AHCI_PxCLB 0x00 /* Port x Command List Base Address Lower 32bits */
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#define AHCI_PxCLBU 0x04 /* Port x Command List Base Address Upper 32bits */
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#define AHCI_PxFB 0x08 /* Port x FIS Base Address Lower 32bits */
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#define AHCI_PxFBU 0x0C /* Port x FIS Base Address Upper 32bits */
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#define AHCI_PxIS 0x10 /* Port x Interrupt Status */
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#define AHCI_PxIE 0x14 /* Port x Interrupt Enable */
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#define AHCI_PxCMD 0x18 /* Port x Command and Status */
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#define AHCI_PxTFD 0x20 /* Port x Task File Data */
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#define AHCI_PxSIG 0x24 /* Port x Signature */
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#define AHCI_PxSSTS 0x28 /* Port x Serial ATA Status */
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#define AHCI_PxSCTL 0x2C /* Port x Serial ATA Control */
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#define AHCI_PxSERR 0x30 /* Port x Serial ATA Error */
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#define AHCI_PxSACT 0x34 /* Port x Serial ATA Active */
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#define AHCI_PxCI 0x38 /* Port x Command Issue */
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#define AHCI_PxSNTF 0x3C /* Port x SNotification */
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#define AHCI_PxVS 0x70 /* Port x Vendor Specific */
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/* register access macros */
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#define CTRL_REG_READ(pCtrl,offset) \
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vxbRead32 (pCtrl->regHandle, \
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(UINT32 *)((ULONG)(pCtrl)->regBase[0] + offset))
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#define CTRL_REG_WRITE(pCtrl,offset,value) \
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vxbWrite32 (pCtrl->regHandle, \
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(UINT32 *)((ULONG)(pCtrl)->regBase[0] + offset), value)
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#define PORT_REG_READ(port,offset) \
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vxbRead32 (port->sataPortDev.host->regHandle, \
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(UINT32 *)((ULONG)(port)->regsAddr + offset))
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#define PORT_REG_WRITE(port,offset,value) \
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vxbWrite32 (port->sataPortDev.host->regHandle, \
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(UINT32 *)((ULONG)(port)->regsAddr + offset),value)
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/* AHCI Host Capabilities Bit Mask Definitions */
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#define AHCI_CAP_S64A 0x80000000 /* Supports 64Bit Addressing */
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#define AHCI_CAP_SNCQ 0x40000000 /* Supports NCQ */
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#define AHCI_CAP_SSNTF 0x20000000 /* Supports SNotification register */
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#define AHCI_CAP_SMPS 0x10000000 /* Supports Mechanical Presence Switch */
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#define AHCI_CAP_SSS 0x08000000 /* Supports Staggered Spin Up */
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#define AHCI_CAP_SALP 0x04000000 /* Supports Agressive Link Power Manage */
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#define AHCI_CAP_SAL 0x02000000 /* Supports Activity LED */
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#define AHCI_CAP_SCLO 0x01000000 /* Supports Command List Override */
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#define AHCI_CAP_ISS 0x00F00000 /* Interface Speed Support */
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#define AHCI_CAP_ISS_SHFT 20
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#define AHCI_CAP_SNZO 0x00080000 /* Supports Non-Zero DMA Offsets */
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#define AHCI_CAP_SAM 0x00040000 /* Supports ACHI mode only */
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#define AHCI_CAP_SPM 0x00020000 /* Supports Port Multiplier */
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#define AHCI_CAP_FBSS 0x00010000 /* Supports FIS Based Switching */
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#define AHCI_CAP_PMD 0x00008000 /* PIO Multiple DRQ Block */
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#define AHCI_CAP_SSC 0x00004000 /* Slumber State Capable */
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#define AHCI_CAP_PSC 0x00002000 /* Parial State Capable */
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#define AHCI_CAP_NCS 0x00001F00 /* Number of Command Slots per port */
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#define AHCI_CAP_NCS_SHFT 8
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#define AHCI_CAP_CCCS 0x00000080 /* Supports Command Completion Coalescing */
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#define AHCI_CAP_EMS 0x00000040 /* Supports Enclosure Management */
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#define AHCI_CAP_SXS 0x00000020 /* Supports External SATA */
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#define AHCI_CAP_NP 0x0000001F /* Number of Ports */
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/* AHCI Global Host Control Bit Mask Definitions */
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#define AHCI_GHC_AE 0x80000000 /* AHCI Enable */
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#define AHCI_GHC_IE 0x00000002 /* Interrupt Enable */
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#define AHCI_GHC_HR 0x00000001 /* Controller Reset */
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/* AHCI Port Interrupt Status Bit Mask Definitions */
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#define AHCI_PIS_CPDS 0x80000000 /* Cold Port Detect Status */
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#define AHCI_PIS_TFES 0x40000000 /* Task File Error Status */
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#define AHCI_PIS_HBFS 0x20000000 /* Host Bus Fatal Error Status */
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#define AHCI_PIS_HBDS 0x10000000 /* Host Bus Data Error Status */
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#define AHCI_PIS_IFS 0x08000000 /* Interface Fatal Error Status */
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#define AHCI_PIS_INFS 0x04000000 /* Interface Non-Fatal Error Status */
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#define AHCI_PIS_OFS 0x01000000 /* Overflow Status */
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#define AHCI_PIS_IPMS 0x00800000 /* Incorrect Port Multiplier Status */
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#define AHCI_PIS_PRCS 0x00400000 /* PhyDry Change Status */
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#define AHCI_PIS_DPMS 0x00000080 /* Device Mechanical Presence Status */
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#define AHCI_PIS_PCS 0x00000040 /* Port Connect Change Status */
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#define AHCI_PIS_DPS 0x00000020 /* Descriptor Processed Status */
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#define AHCI_PIS_UFS 0x00000010 /* Umknown FIS Interrupt Status */
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#define AHCI_PIS_SDBS 0x00000008 /* Set Device Bits Interrupt Status */
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#define AHCI_PIS_DSS 0x00000004 /* DMA Setup FIS Interrupt Status */
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#define AHCI_PIS_PSS 0x00000002 /* PIO Setup FIS Interrupt Status */
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#define AHCI_PIS_DHRS 0x00000001 /* Device to Host Register FIS Status */
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/* AHCI Port Interrupt Enable Bit Mask Definitions */
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#define AHCI_PIE_CPDE 0x80000000 /* Cold Port Detect Enable */
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#define AHCI_PIE_TFEE 0x40000000 /* Task File Error Enable */
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#define AHCI_PIE_HBFE 0x20000000 /* Host Bus Fatal Error Enable */
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#define AHCI_PIE_HBDE 0x10000000 /* Host Bus Data Error Enable */
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#define AHCI_PIE_IFE 0x08000000 /* Interface Fatal Error Enable */
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#define AHCI_PIE_INFE 0x04000000 /* Interface Non-Fatal Error Enable */
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#define AHCI_PIE_OFE 0x01000000 /* Overflow Enable */
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#define AHCI_PIE_IPME 0x00800000 /* Incorrect Port Multiplier Enable */
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#define AHCI_PIE_PRCE 0x00400000 /* PhyDry Change Enable */
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#define AHCI_PIE_DPME 0x00000080 /* Device Mechanical Presence Enable */
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#define AHCI_PIE_PCE 0x00000040 /* Port Connect Change Enable */
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#define AHCI_PIE_DPE 0x00000020 /* Descriptor Processed Enable */
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#define AHCI_PIE_UFE 0x00000010 /* Unknown FIS Interrupt Enable */
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#define AHCI_PIE_SDBE 0x00000008 /* Set Device Bits Interrupt Enable */
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#define AHCI_PIE_DSE 0x00000004 /* DMA Setup FIS Interrupt Enable */
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#define AHCI_PIE_PSE 0x00000002 /* PIO Setup FIS Interrupt Enable */
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#define AHCI_PIE_DHRE 0x00000001 /* Device to Host Register FIS Enable */
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/* AHCI Port Command and Status Bit Mask Definitions */
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#define AHCI_PCMD_ICC 0xF0000000 /* Interface Communication Control */
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#define AHCI_PCMD_ICC_A 0x10000000 /* Active */
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#define AHCI_PCMD_ICC_P 0x20000000 /* Partial */
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#define AHCI_PCMD_ICC_S 0x60000000 /* Slumber */
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#define AHCI_PCMD_ICC_SHFT 28
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#define AHCI_PCMD_ASP 0x08000000 /* Aggressive Slumber/Partial */
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#define AHCI_PCMD_ALPE 0x04000000 /* Aggressive Link Power Manage Enable */
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#define AHCI_PCMD_DLAE 0x02000000 /* Drive LED on ATAPI Enable */
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#define AHCI_PCMD_ATAPI 0x01000000 /* Device is ATAPI */
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#define AHCI_PCMD_ESP 0x00200000 /* External SATA Port*/
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#define AHCI_PCMD_CPD 0x00100000 /* Cold Presence Detection */
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#define AHCI_PCMD_MPSP 0x00080000 /* Mechanical Presence Switch Attached */
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#define AHCI_PCMD_HPCP 0x00040000 /* Hot Plug Capable Port */
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#define AHCI_PCMD_PMA 0x00020000 /* Port Multiplier Attached */
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#define AHCI_PCMD_CPS 0x00010000 /* Cold Presence State */
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#define AHCI_PCMD_CR 0x00008000 /* Command List Running */
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#define AHCI_PCMD_FR 0x00004000 /* FIS Receive Running */
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#define AHCI_PCMD_MPSS 0x00002000 /* Mechanical Presence Switch */
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#define AHCI_PCMD_CCS 0x00001F00 /* Current Command Slot */
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#define AHCI_PCMD_CCS_SHFT 8
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#define AHCI_PCMD_FRE 0x00000010 /* FIS Receive Enable */
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#define AHCI_PCMD_CLO 0x00000008 /* Command List Override */
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#define AHCI_PCMD_POD 0x00000004 /* Power On Device */
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#define AHCI_PCMD_SUD 0x00000002 /* Spin-Up Device */
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#define AHCI_PCMD_ST 0x00000001 /* Start */
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/* AHCI Port Serial ATA Status Bit Mask Definitions */
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#define AHCI_PSSTS_IPM_MSK 0x00000F00 /* Interface Power Management */
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#define AHCI_PSSTS_IPM_NO_DEVICE 0x00000000
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#define AHCI_PSSTS_IPM_ACTIVE 0x00000100
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#define AHCI_PSSTS_IPM_PARTIAL 0x00000200
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#define AHCI_PSSTS_IPM_SLUMBER 0x00000600
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#define AHCI_PSSTS_SPD_MSK 0x000000F0 /* Current Interface Speed */
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#define AHCI_PSSTS_SPD_NO_DEVICE 0x00000000
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#define AHCI_PSSTS_SPD_GEN1 0x00000010
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#define AHCI_PSSTS_SPD_GEN2 0x00000020
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#define AHCI_PSSTS_DET_MSK 0x0000000F /* Device Detection */
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#define AHCI_PSSTS_DET_NO_DEVICE 0x00000000
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#define AHCI_PSSTS_DET_NO_PHY 0x00000001
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#define AHCI_PSSTS_DET_PHY 0x00000003
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#define AHCI_PSSTS_DET_PHY_OFF 0x00000004
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/* AHCI Port Serial ATA Control Bit Mask Definitions */
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#define AHCI_PSCTL_IPM_MSK 0x00000F00 /* Interface Power Management */
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#define AHCI_PSCTL_IPM_NO_RESTRICT 0x00000000
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#define AHCI_PSCTL_IPM_NO_PARTIAL 0x00000100
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#define AHCI_PSCTL_IPM_NO_SLUMBER 0x00000200
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#define AHCI_PSCTL_IPM_NO_PARSLUM 0x00000300
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#define AHCI_PSCTL_SPD_MSK 0x000000F0 /* Speed Allowed */
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#define AHCI_PSCTL_SPD_NO_RESTRICT 0x00000000
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#define AHCI_PSCTL_SPD_LIMIT_GEN1 0x00000010
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#define AHCI_PSCTL_SPD_LIMIT_GEN2 0x00000020
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#define AHCI_PSCTL_DET_MSK 0x0000000F /* Speed Allowed */
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#define AHCI_PSCTL_DET_NO_ACTION 0x00000000
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#define AHCI_PSCTL_DET_RESET 0x00000001
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#define AHCI_PSCTL_DET_DISABLE 0x00000004
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/* AHCI Port Interrupt Enable Bit Mask Definitions */
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#define AHCI_PSERR_DIAG_X 0x04000000 /* Exchanged */
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#define AHCI_PSERR_DIAG_F 0x02000000 /* Unknown FIS Type */
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#define AHCI_PSERR_DIAG_T 0x01000000 /* Transport State Transition Error */
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#define AHCI_PSERR_DIAG_S 0x00800000 /* Link Sequence Error */
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#define AHCI_PSERR_DIAG_H 0x00400000 /* Handshake Error */
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#define AHCI_PSERR_DIAG_C 0x00200000 /* CRC Error */
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#define AHCI_PSERR_DIAG_D 0x00100000 /* Disparity Error */
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#define AHCI_PSERR_DIAG_B 0x00080000 /* 10B to 8B Decode Error */
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#define AHCI_PSERR_DIAG_W 0x00040000 /* Comm Wake */
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#define AHCI_PSERR_DIAG_I 0x00020000 /* Phy Internal Error*/
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#define AHCI_PSERR_DIAG_N 0x00010000 /* Phy Rdy Change */
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#define AHCI_PSERR_ERR_E 0x00000800 /* Internal Error */
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#define AHCI_PSERR_ERR_P 0x00000400 /* Protocol Error */
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#define AHCI_PSERR_ERR_C 0x00000200 /* Data Integrity Error */
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#define AHCI_PSERR_ERR_T 0x00000100 /* Transient Data Integrity Error */
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#define AHCI_PSERR_ERR_M 0x00000002 /* Recovered Communication Error */
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#define AHCI_PSERR_ERR_I 0x00000001 /* Recoever Data Integrity Error */
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/* AHCI Command List Bit Mask Definitions */
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#define AHCI_CMD_LIST_PRDTL 0xFFFF0000 /* PDT Table Length (entries) */
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#define AHCI_CMD_LIST_PRDTL_SHFT 16
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#define AHCI_CMD_LIST_PMP 0x0000F000 /* Port Multiplier Port */
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#define AHCI_CMD_LIST_PMP_SHFT 12
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#define AHCI_CMD_LIST_C 0x00000400 /* Clear Busy upon R_OK */
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#define AHCI_CMD_LIST_B 0x00000200 /* BIST FIS */
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#define AHCI_CMD_LIST_R 0x00000100 /* Reset Command */
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#define AHCI_CMD_LIST_P 0x00000080 /* Prefetchable */
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#define AHCI_CMD_LIST_W 0x00000040 /* Write */
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#define AHCI_CMD_LIST_A 0x00000020 /* ATAPI */
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#define AHCI_CMD_LIST_CFL 0x0000001F /* Command Length (in 32 bit words */
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/* AHCI PRD Bit Maks Definitions */
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#define AHCI_PRD_I 0x80000000 /* Interrupt upon completion */
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#define AHCI_PRD_MAX_BYTES 0x400000
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#define AHCI_NCQ_MODE 0x1000 /* Native Command Queueing Mode */
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#define AHCI_DMA_ULTRA 0x0c00 /* RW DMA ultra */
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#define AHCI_DMA_AUTO 0x0017 /* DMA max supported mode */
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#define AHCI_MODE_ALL (AHCI_DMA_AUTO | AHCI_DMA_ULTRA | AHCI_NCQ_MODE)
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/* default timeout for ATA sync sem */
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#define AHCI_SEM_TIMEOUT_DEF (10*sysClkRateGet())
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/* default timeout for ATA watch dog */
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#define AHCI_WDG_TIMEOUT_DEF (5*sysClkRateGet())
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/* default for number of service tasks per drive */
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#define AHCI_SVC_TASK_COUNT_DEF 1
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#ifndef AHCI_SVC_TASK_COUNT
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# define AHCI_SVC_TASK_COUNT 1 /* Number of service tasks per drive */
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#endif /* AHCI_SVC_TASK_COUNT */
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/* Monitor Task Message types */
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#define AHCI_ATTACH_MSG 'A'
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#define AHCI_REMOVE_MSG 'R'
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#define AHCI_PORT_ERROR_MSG 'E'
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/* diagnostic code */
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#define AHCI_DIAG_OK 0x01
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/* control register */
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#define AHCI_CTL_4BIT 0x8 /* use 4 head bits (wd1003) */
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#define AHCI_CTL_RST 0x4 /* reset controller */
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#define AHCI_CTL_IDS 0x2 /* disable interrupts */
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/* status register */
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#define AHCI_STAT_ACCESS (AHCI_STAT_BUSY | AHCI_STAT_DRQ)
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/* device accessible */
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#define AHCI_STAT_BUSY 0x80 /* controller busy */
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#define AHCI_STAT_READY 0x40 /* selected drive ready */
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#define AHCI_STAT_WRTFLT 0x20 /* write fault */
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#define AHCI_STAT_SEEKCMPLT 0x10 /* seek complete */
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#define AHCI_STAT_DRQ 0x08 /* data request */
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#define AHCI_STAT_ECCCOR 0x04 /* ECC correction made in data */
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#define AHCI_STAT_INDEX 0x02 /* index pulse from selected drive */
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#define AHCI_STAT_ERR 0x01 /* error detect */
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/* size/drive/head register: addressing mode CHS or LBA */
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#define AHCI_SDH_IBM 0xa0 /* chs, 512 bytes sector, ecc */
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#define AHCI_SDH_LBA 0xe0 /* lba, 512 bytes sector, ecc */
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#define AHCI_MAX_RW_SECTORS 0x100 /* max sectors per transfer */
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#define AHCI_MAX_RW_48LBA_SECTORS 0x10000 /* max sectors per transfer in 48-bit LBA mode */
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/* configuration flags: transfer mode, bits, unit, geometry */
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#define AHCI_PIO_DEF_0 AHCI_PIO_DEF_W /* PIO default mode */
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#define AHCI_PIO_DEF_1 AHCI_PIO_DEF_WO /* PIO default mode, no IORDY */
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#define AHCI_PIO_0 AHCI_PIO_W_0 /* PIO mode 0 */
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#define AHCI_PIO_1 AHCI_PIO_W_1 /* PIO mode 1 */
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#define AHCI_PIO_2 AHCI_PIO_W_2 /* PIO mode 2 */
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#define AHCI_PIO_3 AHCI_PIO_W_3 /* PIO mode 3 */
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#define AHCI_PIO_4 AHCI_PIO_W_4 /* PIO mode 4 */
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#define AHCI_PIO_AUTO 0x000d /* PIO max supported mode */
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#define AHCI_DMA_0 0x0010 /* DMA mode 0 */
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#define AHCI_DMA_1 0x0011 /* DMA mode 1 */
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#define AHCI_DMA_2 0x0012 /* DMA mode 2 */
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#define AHCI_DMA_3 0x0013 /* DMA mode 3 */
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#define AHCI_DMA_4 0x0014 /* DMA mode 4 */
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#define AHCI_DMA_5 0x0015 /* DMA mode 5 */
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#define AHCI_DMA_6 0x0016 /* DMA mode 6 */
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#define AHCI_MODE_MASK 0x00FF /* transfer mode mask */
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#define AHCI_PIO_SINGLE 0x0100 /* RW PIO single sector */
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#define AHCI_PIO_MULTI 0x0200 /* RW PIO multi sector */
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#define AHCI_PIO_MASK 0x0300 /* RW PIO mask */
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#define AHCI_DMA_SINGLE 0x0400 /* RW DMA single word */
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#define AHCI_DMA_MULTI 0x0800 /* RW DMA multi word */
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#define AHCI_DMA_MASK 0x0c00 /* RW DMA mask */
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#define AHCI_NCQ_MASK 0x1000 /* Native Command Queueing Mask */
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/* config */
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#define AHCI_CONFIG_PROT_TYPE 0xc000 /* Protocol Type */
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#define AHCI_CONFIG_PROT_TYPE_ATAPI 0x8000 /* ATAPI */
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#define AHCI_CONFIG_DEV_TYPE 0x1f00 /* Device Type */
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#define AHCI_CONFIG_DEV_TYPE_CD_ROM 0x0500
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#define AHCI_CONFIG_REMOVABLE 0x0080 /* Removable */
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#define AHCI_CONFIG_PKT_TYPE 0x0060 /* CMD DRQ Type */
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#define AHCI_CONFIG_PKT_TYPE_MICRO 0x0000 /* Microprocessor DRQ */
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#define AHCI_CONFIG_PKT_TYPE_INTER 0x0020 /* Interrupt DRQ */
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#define AHCI_CONFIG_PKT_TYPE_ACCEL 0x0040 /* Accelerated DRQ */
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#define AHCI_CONFIG_PKT_SIZE 0x0003 /* Command Packet Size */
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#define AHCI_CONFIG_PKT_SIZE_12 0x0000 /* 12 bytes */
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/* capabilities */
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#define AHCI_CAPABIL_DMA 0x0100 /* DMA Supported */
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#define AHCI_CAPABIL_LBA 0x0200 /* LBA Supported */
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#define AHCI_CAPABIL_IORDY_CTRL 0x0400 /* IORDY can be disabled */
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#define AHCI_CAPABIL_IORDY 0x0800 /* IORDY Supported */
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#define AHCI_CAPABIL_OVERLAP 0x2000 /* Overlap Operation Supported */
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/* valid */
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#define AHCI_FIELDS_VALID 0x0002
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/* singleDma */
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#define AHCI_SINGLEDMA_MODE 0xff00 /* 15-8: mode active */
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#define AHCI_SINGLEDMA_SUPPORT 0x00ff /* 7-0: modes supported */
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/* multiDma */
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#define AHCI_MULTIDMA_MODE 0xff00 /* 15-8: mode active */
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#define AHCI_MULTIDMA_SUPPORT 0x00ff /* 7-0: modes supported */
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/* advPio */
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#define AHCI_ADVPIO_MODE3 0x0001 /* The Device supports PIO Mode 3 */
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/* Error Register */
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#define AHCI_ERR_SENSE_KEY 0xf0 /* Sense Key mask */
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#define AHCI_SENSE_NO_SENSE 0x00 /* no sense sense key */
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#define AHCI_SENSE_RECOVERED_ERROR 0x10 /* recovered error sense key */
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#define AHCI_SENSE_NOT_READY 0x20 /* not ready sense key */
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#define AHCI_SENSE_MEDIUM_ERROR 0x30 /* medium error sense key */
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#define AHCI_SENSE_HARDWARE_ERROR 0x40 /* hardware error sense key */
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#define AHCI_SENSE_ILLEGAL_REQUEST 0x50 /* illegal request sense key */
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#define AHCI_SENSE_UNIT_ATTENTION 0x60 /* unit attention sense key */
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#define AHCI_SENSE_DATA_PROTECT 0x70 /* data protect sense key */
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#define AHCI_SENSE_ABBORTED_COMMAND 0xb0 /* aborted command sense key */
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#define AHCI_SENSE_MISCOMPARE 0xe0 /* miscompare sense key */
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#define AHCI_ERR_MCR 0x08 /* Media Change Requested */
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#define AHCI_ERR_ABRT 0x04 /* Aborted command */
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#define AHCI_ERR_EOM 0x02 /* End Of Media */
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#define AHCI_ERR_ILI 0x01 /* Illegal Length Indication */
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/* Feature Register */
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#define AHCI_FEAT_OVERLAP 0x02 /* command may be overlapped */
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|
#define AHCI_FEAT_DMA 0x01 /* data will be transferred via DMA */
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/* Interrupt Reason Register */
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#define AHCI_INTR_RELEASE 0x04 /* Bus released before completing the command */
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#define AHCI_INTR_IO 0x02 /* 1 - In to the Host; 0 - Out to the device */
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#define AHCI_INTR_COD 0x01 /* 1 - Command; 0 - user Data */
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/* Drive Select Register */
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#define AHCI_DSEL_FILLER 0xa0 /* to fill static fields */
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#define AHCI_DSEL_DRV 0x10 /* Device 0 (DRV=0) or 1 (DRV=1) */
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/* Status Register */
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#define AHCI_STAT_BUSY 0x80 /* controller busy */
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#define AHCI_STAT_READY 0x40 /* selected drive ready */
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#define AHCI_STAT_DMA_READY 0x20 /* ready to a DMA data transfer */
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#define AHCI_STAT_WRTFLT 0x20 /* write fault */
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#define AHCI_STAT_SERVICE 0x10 /* service or interrupt request */
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#define AHCI_STAT_SEEKCMPLT 0x10 /* seek complete */
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#define AHCI_STAT_DRQ 0x08 /* data request */
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#define AHCI_STAT_ECCCOR 0x04 /* ECC correction made in data */
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#define AHCI_STAT_ERR 0x01 /* error detect */
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/* Device Control Register */
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#define AHCI_CTL_FILLER 0x8 /* bit 3 must be always set */
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#define AHCI_CTL_RST 0x4 /* reset controller */
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#define AHCI_CTL_IDS 0x2 /* disable interrupts */
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/* Power Management States */
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|
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#define AHCI_PM_ACTIVE_IDLE 0
|
|
#define AHCI_PM_STANDBY 1
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#define AHCI_PM_SLEEP 2
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/* ATA Ioctl function codes */
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|
|
|
#define AHCIIOAPMENABLE 0x100
|
|
#define AHCIIOAPMDISABLE 0x101
|
|
#define AHCIIOAPMGET 0x102
|
|
#define AHCIIOCHECKPOWERLEVEL 0x103
|
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#define AHCIIOPMIDLE 0x104
|
|
#define AHCIIOPMSTANDBY 0x105
|
|
#define AHCIIOPMSLEEP 0x106
|
|
#define AHCIIOPMWAKE 0x107
|
|
#define AHCIIOSMARTENABLE 0x108
|
|
#define AHCIIOSMARTDISABLE 0x109
|
|
#define AHCIIOSMARTSAVEATTR 0x10A
|
|
#define AHCIIOSMARTISENABLED 0x10B
|
|
#define AHCIIOSMARTAUTOSAVEENABLE 0x10C
|
|
#define AHCIIOSMARTAUTOSAVEDISABLE 0x10D
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|
#define AHCIIOSMARTOFFLINEDIAG 0x10E
|
|
#define AHCIIOSMARTRETURNSTATUS 0x10F
|
|
#define AHCIIOSMARTREADDATA 0x110
|
|
#define AHCIIOSMARTREADTHRESHOLDS 0x111
|
|
#define AHCIIOPARMSGET 0x112
|
|
#define AHCIIOMAXSECTORXFERSET 0x113
|
|
#define AHCIIOMAXSECTORXFERGET 0x114
|
|
#define AHCIIODRIVEHALT 0x115
|
|
#define AHCIIODRIVESTOP 0x116
|
|
#define AHCIIODRIVESTART 0x117
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|
|
|
/* attribute of the current */
|
|
#define AHCI_TRANSFER_WITH_DATA 0x00000001
|
|
#define AHCI_TRANSFER_NCQ_CMD 0x00000002
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|
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#endif /* _ASMLANGUAGE */
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|
|
#ifdef __cplusplus
|
|
}
|
|
#endif /* __cplusplus */
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|
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#endif /* __INCvxbAhciStorageh */
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