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#ifndef __VXB_SM2130_SPI_DEV_H
#define __VXB_SM2130_SPI_DEV_H
#define SPI_DEV_SM2130 "SM2130"
#define SM2130_DEV_NAME "/sm2130"
#define __SM2130__IOC_MAGIC ('S' << 16)
#define XFER_TYPE_WR (1)
#define XFER_TYPE_RD (2)
#define FIOC_SM2130_WR (__SM2130__IOC_MAGIC | XFER_TYPE_WR)
#define FIOC_SM2130_RD (__SM2130__IOC_MAGIC | XFER_TYPE_RD)
#define FIOC_SM2130_READY (__SM2130__IOC_MAGIC | 0x10)
#define FIOC_SM2130_ACKABLE (__SM2130__IOC_MAGIC | 0x11)
#define FIOC_SM2130_ACKIRQ (__SM2130__IOC_MAGIC | 0x12)
#define FIOC_SM2130_RST (__SM2130__IOC_MAGIC | 0x13)
#define FIOC_SM2130_REQISR (__SM2130__IOC_MAGIC | 0x14)
#define FIOC_SM2130_REGRD (__SM2130__IOC_MAGIC | 0x21)
#define FIOC_SM2130_REGWR (__SM2130__IOC_MAGIC | 0x22)
#define FIOC_SM2130_SMADDR (__SM2130__IOC_MAGIC | 0x23)
#define FIOC_SM2130_RDMEM (__SM2130__IOC_MAGIC | 0x24)
#define FIOC_SM2130_WRMEM (__SM2130__IOC_MAGIC | 0x25)
struct sm2130_xfer {
UINT8 reg;
UINT16 val;
};
typedef struct sm2130_xfer SM2130_XFER;
#define SMX_MAX_WORDS (64)
struct sm2130_xfer_mem {
int count;
UINT8 reg;
UINT16 address;
UINT16 *membuf;
};
typedef struct sm2130_xfer_mem SM2130_MEM_XFER;
typedef struct _spi_1553b_drv_ctrl {
VXB_DEVICE_ID pDev;
char name[16];
const char *devName;
volatile int refcount;
volatile UINT32 irqCount;
volatile BOOL irqFlag;
spinlockIsr_t spinLock;
void *devHandle;
int (*funcReqIsr)(void *data, void (*isr)(void *data));
int (*funcIsReady)();
void (*funcAckIrq)(BOOL);
void (*funcReset)(BOOL);
INT32 (*read)(VXB_DEVICE_ID pDev, UINT8 cmd);
STATUS (*write)(VXB_DEVICE_ID pDev, UINT8 cmd, UINT16 var);
UINT16 regmem[SMX_MAX_WORDS+1]; /* add 1 dummy slot */
SEM_ID muteSem; /* operation semaphore */
VXB_SPI_MAST_SPEC *specialInfo;
} SM2130_SPI_DEV;
#endif