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617 lines
25 KiB
617 lines
25 KiB
/* hwconf.c - Hardware configuration support module */
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/*
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it;
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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*/
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#include <vxWorks.h>
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#include <vsbConfig.h>
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#include <vxBusLib.h>
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#include <hwif/vxbus/vxBus.h>
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#include <hwif/vxbus/vxbIntrCtlr.h>
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#include <hwif/util/vxbParamSys.h>
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#include <hwif/vxbus/hwConf.h>
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#include "config.h"
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#include "ft2000-4.h"
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#ifdef DRV_FTI2C
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#include <hwif/vxbus/vxbI2cLib.h>
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#endif
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#ifdef DRV_FTQSPI
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#include "vxbFtQspi.h"
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#endif
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#ifdef DRV_FTSPI
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#include "vxbFtSpi.h"
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#endif
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#ifdef DRV_PCIBUS_FT
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# include <drv/pci/pciAutoConfigLib.h>
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#endif
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#define GEN_TIMER_IRQ 30
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#define AUX_GEN_TIMER_IRQ 27
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#define SYS_CLK_REG_BASE 0xeeee0000
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#define SYS_CLK_FREQ 50000000
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#define AUX_CLK_REG_BASE 0xeeef0000
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#define AUX_CLK_FREQ 50000000
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#ifdef DRV_ARM_GICV3
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LOCAL struct intrCtlrInputs gicInputs[] = {
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/* pin, driver, unit, index */
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{ GEN_TIMER_IRQ, "armGenTimer", 0, 0 },
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#ifdef DRV_ARM_GEN_AUX_TIMER
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{ AUX_GEN_TIMER_IRQ, "armAuxTimer", 0, 0 },
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#endif
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{ INT_VEC_UART0INTR, "primeCellSioDev", 0, 0 },
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{ INT_VEC_UART1INTR, "primeCellSioDev", 1, 0 },
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{ INT_VEC_UART2INTR, "primeCellSioDev", 2, 0 },
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{ INT_VEC_UART3INTR, "primeCellSioDev", 3, 0 },
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{ 81, "gmac", 0, 0 },
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{ 82, "gmac", 1, 0 },
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{ FTCAN0_IRQ, "ftCan", 0, 0 },
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{ FTCAN1_IRQ, "ftCan", 1, 0 },
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{ FTCAN2_IRQ, "ftCan", 2, 0 },
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{ 60, "legacy", 0, 60}, /* Peu0 legacy interrupt number : 60,61,62,63*/
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{ 61, "legacy", 0, 61},
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{ 62, "legacy", 0, 62},
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{ 63, "legacy", 0, 63},
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#ifdef DRV_FTSPI
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{ FTSPI0_IRQ, FT_SPI_NAME, 0, 0 },
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{ FTSPI1_IRQ, FT_SPI_NAME, 1, 0 },
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#endif
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{ 52, "ftSdhci", 0, 0 },
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{ 53, "ftSdhci", 0, 1 },
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{ 54, "ftSdhci", 0, 2 },
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{ I2C_0_INTR_IRQ, "ftI2c", 0, 0 },
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{ I2C_1_INTR_IRQ, "ftI2c", 1, 0 },
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{ I2C_2_INTR_IRQ, "ftI2c", 2, 0 },
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{ I2C_3_INTR_IRQ, "ftI2c", 3, 0 },
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{ INT_VEC_GPIO0INTR, "ftGpio", 0, 0 },
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{ INT_VEC_GPIO1INTR, "ftGpio", 1, 0 },
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{ INT_VEC_GPIO0INTR, "legacy", 0, INT_VEC_GPIO0INTR },
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{ INT_VEC_GPIO1INTR, "legacy", 0, INT_VEC_GPIO1INTR },
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};
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LOCAL const struct intrCtlrPriority gicPriority[] = {
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/* pin, priority */
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{ GEN_TIMER_IRQ, 0x0 },
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#ifdef DRV_ARM_GEN_AUX_TIMER
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{ AUX_GEN_TIMER_IRQ, 0x0 },
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#endif
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{ INT_VEC_UART0INTR, 0x10 },
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{ INT_VEC_UART1INTR, 0x10 },
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{ INT_VEC_UART2INTR, 0x10 },
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{ INT_VEC_UART3INTR, 0x10 },
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{ 81, 0x10 }, /*gmac0*/
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{ 82, 0x10 }, /*gmac1*/
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{ FTCAN0_IRQ, 0x10 },
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{ FTCAN1_IRQ, 0x10 },
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{ FTCAN2_IRQ, 0x10 },
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{ 60, 0x10 }, /* Peu0 legacy interrupt number : 60,61,62,63*/
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{ 61, 0x10 },
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{ 62, 0x10 },
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{ 63, 0x10 },
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#ifdef DRV_FTSPI
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{ FTSPI0_IRQ, 0x10},
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{ FTSPI1_IRQ, 0x10},
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#endif
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{ 52, 0x20 }, /*ftSdhci interrupt number : 52,53,54*/
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{ 53, 0x20 },
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{ 54, 0x20 },
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{ I2C_0_INTR_IRQ, 0x20 },
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{ I2C_1_INTR_IRQ, 0x20 },
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{ I2C_2_INTR_IRQ, 0x20 },
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{ I2C_3_INTR_IRQ, 0x20 },
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{ INT_VEC_GPIO0INTR, 0x20 },
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{ INT_VEC_GPIO1INTR, 0x20 },
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};
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#ifdef _WRS_CONFIG_SMP
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struct intrCtlrCpu gicCpu[] = {
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/* pin, CPU */
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{ INT_VEC_UART0INTR, 0 },
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{ INT_VEC_UART1INTR, 2 },
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{ INT_VEC_UART2INTR, 0 },
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{ INT_VEC_UART3INTR, 0 },
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{ 81, 1 }, /*gmac0*/
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{ 82, 0 }, /*gmac1*/
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{ FTCAN0_IRQ, 0 },
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{ FTCAN1_IRQ, 0 },
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{ FTCAN2_IRQ, 0 },
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{ 60, 0 }, /* Peu0 legacy interrupt number : 60,61,62,63*/
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{ 61, 0 },
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{ 62, 0 },
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{ 63, 0 },
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#ifdef DRV_FTSPI
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{ FTSPI0_IRQ, 0},
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{ FTSPI1_IRQ, 0},
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#endif
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{ 52, 0 }, /*ftSdhci interrupt number : 52,53,54*/
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{ 53, 0 },
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{ 54, 0 },
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{ I2C_0_INTR_IRQ, 0 },
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{ I2C_1_INTR_IRQ, 3 },
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{ I2C_2_INTR_IRQ, 0 },
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{ I2C_3_INTR_IRQ, 0 },
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{ INT_VEC_GPIO0INTR, 0 },
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{ INT_VEC_GPIO1INTR, 0 },
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};
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#endif /* _WRS_CONFIG_SMP */
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LOCAL const struct intrCtlrTrigger gicTrigger[] = {
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/* pin, sensitivity */
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{ INT_VEC_GPIO0INTR, VXB_INTR_TRIG_RISING_EDGE },
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{ INT_VEC_GPIO1INTR, VXB_INTR_TRIG_FALLING_EDGE },
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};
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/* dts info:
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interrupt-controller;
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reg = <0x0 0x29900000 0 0x20000>, GICD
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<0x0 0x29980000 0 0x80000>, GICR
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<0x0 0x29c00000 0 0x10000>, GICC
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<0x0 0x29c10000 0 0x10000>, GICH
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<0x0 0x29c20000 0 0x10000>; GICV
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*/
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/*
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* interrupt mode - interrupts can be in either preemptive or non-preemptive
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* mode. For preemptive mode, change INT_MODE to INT_PREEMPT_MODEL
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*/
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#define INT_MODE INT_NON_PREEMPT_MODEL
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LOCAL const struct hcfResource armGICv3Resources[] = {
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{ "regBase", HCF_RES_INT, { (void *)GIC_BASE_ADR } },
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{ "distOffset", HCF_RES_INT, {(void *)0 } },
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{ "redistOffset", HCF_RES_INT, {(void *)0x80000 } },
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{ "input", HCF_RES_ADDR, {(void *)&gicInputs[0] } },
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#ifdef _WRS_CONFIG_SMP
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{ "cpuRoute", HCF_RES_ADDR, {(void *)&gicCpu[0] } },
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{ "cpuRouteTableSize", HCF_RES_INT, {(void *)NELEMENTS(gicCpu) } },
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#endif
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{ "inputTableSize", HCF_RES_INT, {(void *)NELEMENTS(gicInputs) } },
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{ "priority", HCF_RES_ADDR, {(void *)&gicPriority[0]} },
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{ "priorityTableSize", HCF_RES_INT, {(void *)NELEMENTS(gicPriority) } },
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{ "trigger", HCF_RES_ADDR, {(void *)&gicTrigger[0]} },
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{ "triggerTableSize", HCF_RES_INT, {(void *)NELEMENTS(gicTrigger) } },
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{ "intMode", HCF_RES_INT, {(void *)INT_MODE } },
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#ifdef _WRS_CONFIG_SMP
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{ "maxCpuNum", HCF_RES_INT, {(void *)4} },
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#endif /* _WRS_CONFIG_SMP */
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};
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#define armGICv3Num NELEMENTS(armGICv3Resources)
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#endif /* DRV_ARM_GICV3 */
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struct hcfResource primeCellSioDev0Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)UART_0_BASE_ADR} },
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{ "clkFreq", HCF_RES_INT, {(void *)FT2000_UART_CLK} },
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};
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#define primeCellSioDev0Num NELEMENTS(primeCellSioDev0Resources)
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struct hcfResource primeCellSioDev1Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)UART_1_BASE_ADR} },
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{ "clkFreq", HCF_RES_INT, {(void *)FT2000_UART_CLK} },
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};
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#define primeCellSioDev1Num NELEMENTS(primeCellSioDev1Resources)
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struct hcfResource primeCellSioDev2Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)UART_2_BASE_ADR} },
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{ "clkFreq", HCF_RES_INT, {(void *)FT2000_UART_CLK} },
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};
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#define primeCellSioDev2Num NELEMENTS(primeCellSioDev2Resources)
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struct hcfResource primeCellSioDev3Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)UART_3_BASE_ADR} },
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{ "clkFreq", HCF_RES_INT, {(void *)FT2000_UART_CLK} },
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};
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#define primeCellSioDev3Num NELEMENTS(primeCellSioDev3Resources)
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struct hcfResource ftCanDev0Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)FTCAN0_BASE} },
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{ "irq", HCF_RES_INT, {(void *)FTCAN0_IRQ} },
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{ "bitrate", HCF_RES_INT, {(void *)FTCAN0_BITRATE} },
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};
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#define ftCanDev0Num NELEMENTS(ftCanDev0Resources)
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struct hcfResource ftCanDev1Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)FTCAN1_BASE} },
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{ "irq", HCF_RES_INT, {(void *)FTCAN1_IRQ} },
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{ "bitrate", HCF_RES_INT, {(void *)FTCAN1_BITRATE} },
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};
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#define ftCanDev1Num NELEMENTS(ftCanDev1Resources)
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struct hcfResource ftCanDev2Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)FTCAN2_BASE} },
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{ "irq", HCF_RES_INT, {(void *)FTCAN2_IRQ} },
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{ "bitrate", HCF_RES_INT, {(void *)FTCAN2_BITRATE} },
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};
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#define ftCanDev2Num NELEMENTS(ftCanDev2Resources)
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#ifdef DRV_FTQSPI
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struct vxbSpiDevInfo qspiDevTbl[] = {
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/* name cs width freq mode */
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#ifdef DRV_SPIFLASH_SP25
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{ SPI_FLASH_DEVICE_NAME, 0, 8, 18000000, 1},
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#endif
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};
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struct hcfResource qspiResources[] = {
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{ "regBase", HCF_RES_INT, { (void *)(0x28014000) } },
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{ "capacity", HCF_RES_INT, { (void *)(QSPI_FLASH_CAP_32MB) } },
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{ "clkDiv", HCF_RES_INT, { (void *)(QSPI_SCK_DIV_128) } },
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{ "transMode", HCF_RES_INT, { (void *)(QSPI_TRANSFER_1_1_1) } },
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{ "addrMode", HCF_RES_INT, { (void *)(QSPI_ADDR_SEL_4) } },
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{ "spiDev", HCF_RES_ADDR, { (void *)&qspiDevTbl[0]} },
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{ "spiDevNum", HCF_RES_INT, { (void *)NELEMENTS(qspiDevTbl)}},
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};
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# define qspiNum NELEMENTS(qspiResources)
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#endif /* DRV_FTQSPI */
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#ifdef DRV_FTSPI
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struct vxbSpiDevInfo sm2130DevRes[] = {
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/* name cs width freq mode */
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{ "SM2130", 0, 8, 16000000, 3},
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};
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struct vxbSpiDevInfo spiRawDevRes[] = {
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/* name cs width freq mode */
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{ "spiDev", 0, 8, 5000000, 3},
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};
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struct hcfResource spiResources0[] = {
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{ "regBase", HCF_RES_INT, { (void *)(FTSPI0_BASE) } },
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{ "clkFreq", HCF_RES_INT, { (void *)(FT2000_SPI_CLK) } },
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{ "speed", HCF_RES_INT, { (void *)(4000000) } },
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{ "mode", HCF_RES_INT, { (void *)3} },
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{ "spiDev", HCF_RES_ADDR, { (void *)&spiRawDevRes[0]} },
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{ "spiDevNum", HCF_RES_INT, { (void *)NELEMENTS(spiRawDevRes)}},
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};
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#define spiNum0 NELEMENTS(spiResources0)
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struct hcfResource spiResources1[] = {
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{ "regBase", HCF_RES_INT, { (void *)(FTSPI1_BASE) } },
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{ "clkFreq", HCF_RES_INT, { (void *)(FT2000_SPI_CLK) } },
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{ "speed", HCF_RES_INT, { (void *)(16000000) } },
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{ "mode", HCF_RES_INT, { (void *)3} },
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{ "spiDev", HCF_RES_ADDR, { (void *)&sm2130DevRes[0]} },
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{ "spiDevNum", HCF_RES_INT, { (void *)NELEMENTS(sm2130DevRes)}},
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};
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#define spiNum1 NELEMENTS(spiResources1)
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#endif /* DRV_FTSPI */
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#ifdef DRV_FTI2C
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LOCAL struct i2cDevInputs i2cDev0Input[] = {
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/* Name */ /* Addr (7-bit) */ /* flag */
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#ifdef DRV_I2C_EEPROM
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{ "eeprom_at24c32", (0x57), I2C_WORDADDR },
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#endif
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};
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struct hcfResource i2cDev0Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)REG_I2C0_BASE} },
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{ "irq", HCF_RES_INT, {(void *)I2C_0_INTR_IRQ} },
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{ "clkFreq", HCF_RES_INT,{(void *)FT2000_I2C_CLK} },
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{ "busSpeed", HCF_RES_INT,{(void *)400000} },
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{ "polling", HCF_RES_INT,{(void *)TRUE} },
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{ "i2cDev", HCF_RES_ADDR, {(void *)&i2cDev0Input[0] } },
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{ "i2cDevNum", HCF_RES_INT,{(void *)NELEMENTS(i2cDev0Input)} },
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/* I2C0 pin default is I2C0. Need not DeMux.
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{ "pinDemuxReg", HCF_RES_INT,{(void *)0} },
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{ "pinDemuxBit", HCF_RES_INT,{(void *)0} },
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*/
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};
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#define i2cDev0Num NELEMENTS(i2cDev0Resources)
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LOCAL struct i2cDevInputs i2cDev1Input[] = {
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/* Name */ /* Addr (7-bit) */ /* flag */
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#ifdef DRV_I2C_RTC
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{ "rtc_ds1339", (0xD0>>1), 0 },
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#endif
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};
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struct hcfResource i2cDev1Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)REG_I2C1_BASE} },
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{ "irq", HCF_RES_INT, {(void *)I2C_1_INTR_IRQ} },
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{ "clkFreq", HCF_RES_INT,{(void *)FT2000_I2C_CLK} },
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{ "busSpeed", HCF_RES_INT,{(void *)400000} },
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{ "polling", HCF_RES_INT,{(void *)TRUE} },
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{ "i2cDev", HCF_RES_ADDR, {(void *)&i2cDev1Input[0] } },
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{ "i2cDevNum", HCF_RES_INT,{(void *)NELEMENTS(i2cDev1Input)} },
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{ "pinDemuxReg", HCF_RES_INT,{(void *)0x28180200} }, /* pin MUX/DEMUX register */
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{ "pinDemuxBit", HCF_RES_INT,{(void *)0x22000000} }, /* pin MUX/DEMUX bit value */
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};
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#define i2cDev1Num NELEMENTS(i2cDev1Resources)
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LOCAL struct i2cDevInputs i2cDev2Input[] = {
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};
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struct hcfResource i2cDev2Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)REG_I2C2_BASE} },
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{ "irq", HCF_RES_INT, {(void *)I2C_2_INTR_IRQ} },
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{ "clkFreq", HCF_RES_INT,{(void *)FT2000_I2C_CLK} },
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{ "busSpeed", HCF_RES_INT,{(void *)400000} },
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{ "polling", HCF_RES_INT,{(void *)TRUE} },
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{ "i2cDev", HCF_RES_ADDR, {(void *)&i2cDev2Input[0] } },
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{ "i2cDevNum", HCF_RES_INT,{(void *)NELEMENTS(i2cDev2Input)} },
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{ "pinDemuxReg", HCF_RES_INT,{(void *)0x28180204} }, /* pin MUX/DEMUX register */
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{ "pinDemuxBit", HCF_RES_INT,{(void *)0x00000220} }, /* pin MUX/DEMUX bit value */
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};
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#define i2cDev2Num NELEMENTS(i2cDev2Resources)
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LOCAL struct i2cDevInputs i2cDev3Input[] = {
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};
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struct hcfResource i2cDev3Resources[] = {
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{ "regBase", HCF_RES_INT, {(void *)REG_I2C3_BASE} },
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{ "irq", HCF_RES_INT, {(void *)I2C_3_INTR_IRQ} },
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{ "clkFreq", HCF_RES_INT,{(void *)FT2000_I2C_CLK} },
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{ "busSpeed", HCF_RES_INT,{(void *)400000} },
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{ "polling", HCF_RES_INT,{(void *)TRUE} },
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{ "i2cDev", HCF_RES_ADDR, {(void *)&i2cDev3Input[0] } },
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{ "i2cDevNum", HCF_RES_INT,{(void *)NELEMENTS(i2cDev3Input)} },
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{ "pinDemuxReg", HCF_RES_INT,{(void *)0x28180204} }, /* pin MUX/DEMUX register */
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{ "pinDemuxBit", HCF_RES_INT,{(void *)0x00000002} }, /* pin MUX/DEMUX bit value */
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{ "pinDemuxRegEx", HCF_RES_INT,{(void *)0x28180208} }, /* pin MUX/DEMUX register */
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{ "pinDemuxBitEx", HCF_RES_INT,{(void *)0x20000000} }, /* pin MUX/DEMUX bit value */
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};
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#define i2cDev3Num NELEMENTS(i2cDev3Resources)
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#endif
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#ifdef DRV_FTGPIO
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/*This table is used to set the default pin mode of portA*/
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LOCAL UINT8 gpio0PortAModeTable[] = {
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/*pin of portA can be used as interrupt mode*/
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/*portA-pinX: 0 1 2 3 4 5 6 7 */
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0, 2, 0, 1, 0, 1, 1, 0 /* 0:GPIO_MODE_NOT_USED 1:GPIO_MODE_IN
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2:GPIO_MODE_OUT 3:GPIO_MODE_INT*/ /* GPIO0_A3, GPIO0_A5, GPIO0_A6 as uart irq */
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};
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/*This table is used to set the default pin mode of portB*/
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LOCAL UINT8 gpio0PortBModeTable[] = {
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/*pin of portB can not be used as interrupt mode*/
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/*portB-pinX: 0 1 2 3 4 5 6 7 */
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0, 0, 0, 0, 0, 0, 2, 1 /* GPIO0_B6: SM2130_ACKIRQ; GPIO0_B7: SM2130_READY */
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};
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struct hcfResource gpioDev0Resources[] = {
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{ "regBase", HCF_RES_INT, { (void *)GPIO_0_BASE_ADR } },
|
|
{ "portAModeTable", HCF_RES_ADDR, { (void *)&gpio0PortAModeTable[0] } },
|
|
{ "portAModeTableNum", HCF_RES_INT, { (void *)NELEMENTS(gpio0PortAModeTable)} },
|
|
{ "portBModeTable", HCF_RES_ADDR, { (void *)&gpio0PortBModeTable[0] } },
|
|
{ "portBModeTableNum", HCF_RES_INT, { (void *)NELEMENTS(gpio0PortBModeTable)} },
|
|
{ "trigger", HCF_RES_INT, { (void *)VXB_INTR_TRIG_RISING_EDGE } },
|
|
};
|
|
#define gpioDev0Num NELEMENTS(gpioDev0Resources)
|
|
|
|
LOCAL UINT8 gpio1PortAModeTable[] = {
|
|
/*portA-pinX: 0 1 2 3 4 5 6 7 */
|
|
0, 0, 0, 0, 3, 0, 0, 0 /* 0:GPIO_MODE_NOT_USED 1:GPIO_MODE_IN
|
|
2:GPIO_MODE_OUT 3:GPIO_MODE_INT*/ /* GPIO1_A4: SM2130_IRQ */
|
|
};
|
|
LOCAL UINT8 gpio1PortBModeTable[] = {
|
|
/*portB-pinX: 0 1 2 3 4 5 6 7 */
|
|
0, 0, 0, 0, 0, 0, 0, 2 /* GPIO1_B7: SM2130_MR */
|
|
};
|
|
struct hcfResource gpioDev1Resources[] = {
|
|
{ "regBase", HCF_RES_INT, { (void *)GPIO_1_BASE_ADR } },
|
|
{ "portAModeTable", HCF_RES_ADDR, { (void *)&gpio1PortAModeTable[0] } },
|
|
{ "portAModeTableNum", HCF_RES_INT, { (void *)NELEMENTS(gpio1PortAModeTable)} },
|
|
{ "portBModeTable", HCF_RES_ADDR, { (void *)&gpio1PortBModeTable[0] } },
|
|
{ "portBModeTableNum", HCF_RES_INT, { (void *)NELEMENTS(gpio1PortBModeTable)} },
|
|
{ "trigger", HCF_RES_INT, { (void *)VXB_INTR_TRIG_FALLING_EDGE } },
|
|
};
|
|
#define gpioDev1Num NELEMENTS(gpioDev1Resources)
|
|
#endif
|
|
|
|
#ifdef DRV_ARM_GEN_SYS_TIMER
|
|
struct hcfResource armGenSysTimerResources[] = {
|
|
{ "regBase", HCF_RES_INT, {(void *)0xeeee0000 } },
|
|
{ "irq", HCF_RES_INT, {(void *)GEN_TIMER_IRQ } },
|
|
{ "clkFreq", HCF_RES_INT, {(void *)SYS_CLK_FREQ } },
|
|
{ "minClkRate", HCF_RES_INT, {(void *)SYS_CLK_RATE_MIN} },
|
|
{ "maxClkRate", HCF_RES_INT, {(void *)SYS_CLK_RATE_MAX} },
|
|
};
|
|
#define armGenSysTimerNum NELEMENTS(armGenSysTimerResources)
|
|
#endif /* DRV_ARM_GEN_SYS_TIMER */
|
|
|
|
#ifdef DRV_ARM_GEN_AUX_TIMER
|
|
struct hcfResource armAuxGenTimerResources[] = {
|
|
{ "regBase", HCF_RES_INT, {(void *)AUX_CLK_REG_BASE } },
|
|
{ "irq", HCF_RES_INT, {(void *)AUX_GEN_TIMER_IRQ } },
|
|
{ "clkFreq", HCF_RES_INT, {(void *)AUX_CLK_FREQ } },
|
|
{ "minClkRate", HCF_RES_INT, {(void *)SYS_CLK_RATE_MIN} },
|
|
{ "maxClkRate", HCF_RES_INT, {(void *)SYS_CLK_RATE_MAX} },
|
|
};
|
|
#define armAuxGenTimerNum NELEMENTS(armAuxGenTimerResources)
|
|
#endif /* DRV_ARM_GEN_SYS_TIMER */
|
|
|
|
#ifdef DRV_PCIBUS_FT
|
|
IMPORT STATUS sysPciExAutoconfigInclude(PCI_SYSTEM *, PCI_LOC *, UINT);
|
|
IMPORT UCHAR sysPciExAutoconfigIntrAssign(PCI_SYSTEM *, PCI_LOC *, UCHAR);
|
|
IMPORT VOID sysPciPirqEnable (BOOL enable);
|
|
const struct hcfResource ftPci0Resources[] = {
|
|
{ "regBase", HCF_RES_INT, { (void *)(FT_PCI_CONFIG_ADDR) } },
|
|
{ "memIo32Addr", HCF_RES_ADDR, { (void *)0x58000000 } },
|
|
{ "memIo32Size", HCF_RES_INT, { (void *)0x27f00000 } },
|
|
{ "io32Addr", HCF_RES_ADDR, { (void *)0x50000000 } },
|
|
{ "io32Size", HCF_RES_INT, { (void *)0x08000000 } },
|
|
|
|
{ "io16Addr", HCF_RES_ADDR, { (void *)0x1000 } },
|
|
{ "io16Size", HCF_RES_INT, { (void *)0x0ffff000 } },
|
|
|
|
{ "ioStart", HCF_RES_ADDR, { (void *)0x50000000} },
|
|
|
|
{ "fbbEnable", HCF_RES_INT, { (void *)TRUE } },
|
|
{ "cacheSize", HCF_RES_INT, { (void *)(8) } },
|
|
{ "maxLatAllSet", HCF_RES_INT, { (void *)0x40 } },
|
|
{ "autoIntRouteSet", HCF_RES_INT, { (void *)FALSE } },
|
|
|
|
{ "includeFuncSet", HCF_RES_ADDR, { (void *)sysPciExAutoconfigInclude } },
|
|
{ "intAssignFuncSet", HCF_RES_ADDR, { (void *)sysPciExAutoconfigIntrAssign } },
|
|
{ "funcPirqEnable", HCF_RES_ADDR, { (void *)sysPciPirqEnable}},
|
|
{ "maxBusSet", HCF_RES_INT, { (void *)32 } },
|
|
|
|
/* Window Attributes - Defaults to 8540 type if none given */
|
|
|
|
{ "autoConfig", HCF_RES_INT, { (void *)(FALSE) } },
|
|
|
|
#ifdef INCLUDE_INTCTLR_DYNAMIC_LIB
|
|
{ "msiEnable", HCF_RES_INT, { (void *)(TRUE) } },
|
|
{ "dynamicInterrupts", HCF_RES_INT, { (void *)(TRUE) } }
|
|
#else
|
|
{ "msiEnable", HCF_RES_INT, { (void *)(FALSE) } },
|
|
{ "dynamicInterrupts", HCF_RES_INT, { (void *)(FALSE) } }
|
|
#endif /* INCLUDE_INTCTLR_DYNAMIC_LIB */
|
|
};
|
|
#define ftPci0Num NELEMENTS(ftPci0Resources)
|
|
#endif /* DRV_PCIBUS_M85XX */
|
|
|
|
LOCAL struct hcfResource ftSdhc0Resources[] = {
|
|
{ "regBase", HCF_RES_INT, {(void *)FT_SDHC0_BASE} },
|
|
{ "clkFreq", HCF_RES_ADDR, {(void *)sysSdhcClkFreqGet} },
|
|
{ "polling", HCF_RES_INT, {(void *)TRUE} } /* interrupt mode dose not support*/
|
|
};
|
|
#define ftSdhc0Num NELEMENTS(ftSdhc0Resources)
|
|
|
|
#ifdef DRV_VXBEND_FTGMAC
|
|
|
|
#define PHYADDR_OF_GMAC0 1
|
|
#define PHYADDR_OF_AUTO -1 /* auto probe when start */
|
|
|
|
struct hcfResource gmac0Resources[] = {
|
|
{ "regBase", HCF_RES_INT, {(void *)0x2820c000} },
|
|
{ "phyAddr", HCF_RES_INT, {(void *)PHYADDR_OF_GMAC0} },
|
|
{ "macAddrSet", HCF_RES_ADDR, {(void *)sysGmacAddrSet} },
|
|
{ "miiIfName", HCF_RES_STRING, {(void *)"gmac"} },
|
|
{ "miiIfUnit", HCF_RES_INT, {(void *)0} },
|
|
/*
|
|
* The clkMDC resource specifies the CSR clock range. Use clk_csr_i frequency
|
|
* to compute MDC clock frequency. To be sure MDC clock is in [1.0MHz ~2.5MHz] }
|
|
* Table GMII Address Register
|
|
* bit[5:2] clk_csr_i MDC clock
|
|
* 0000 60-100MHz clk_csr_i
|
|
* 0001 100-150 MHz clk_csr_i/62
|
|
* 0010 20-35 MHz clk_csr_i/16
|
|
* 0011 35-60 MHz clk_csr_i/26
|
|
* 0100 150-250 MHz clk_csr_i/102
|
|
* 0101 250-300 MHz clk_csr_i/124 <==
|
|
* 0110, 0111 Reserved
|
|
*/
|
|
{ "clkMDC", HCF_RES_INT, {(void *)0x5} }
|
|
};
|
|
#define gmac0Num NELEMENTS(gmac0Resources)
|
|
|
|
struct hcfResource gmac1Resources[] = {
|
|
{ "regBase", HCF_RES_INT, {(void *)0x28210000} },
|
|
{ "phyAddr", HCF_RES_INT, {(void *)PHYADDR_OF_AUTO} },
|
|
{ "macAddrSet", HCF_RES_ADDR, {(void *)sysGmacAddrSet} },
|
|
{ "miiIfName", HCF_RES_STRING, {(void *)"gmac"} },
|
|
{ "miiIfUnit", HCF_RES_INT, {(void *)1} },
|
|
{ "clkMDC", HCF_RES_INT, {(void *)0x5} }
|
|
};
|
|
#define gmac1Num NELEMENTS(gmac1Resources)
|
|
#endif /* DRV_VXBEND_FTGMAC */
|
|
|
|
#ifdef DRV_FS_LITTLEFS
|
|
struct hcfResource lfsResources[] = {
|
|
{ "mountPoint" , HCF_RES_STRING, {(void *)TFFS_FLASH_MOUNT_POINTOT}},
|
|
{ "flashName" , HCF_RES_STRING, {(void *)TFFS_PART0_FLASH_NAME}},
|
|
{ "flashOffset", HCF_RES_INT, {(void *)(TFFS_PART0_FLASH_BOOT_SIZE)}},
|
|
{ "autoFormat", HCF_RES_INT, {(void *)(1)}},
|
|
};
|
|
#define lfsResNum NELEMENTS(lfsResources)
|
|
#endif
|
|
|
|
IMPORT void bspSm1553bIrqConnect(void *data, void (*isr)(void *data));
|
|
IMPORT int bspSm1553bChipReady(void);
|
|
IMPORT void bspSm1553bAckIrq(BOOL);
|
|
IMPORT void bspSm1553bReset(BOOL);
|
|
|
|
struct hcfResource sm2130Resources[] = {
|
|
{ "devName" , HCF_RES_STRING, {(void *)"/sm1553b" } },
|
|
{ "funcReqIsr" , HCF_RES_ADDR, {(void *)bspSm1553bIrqConnect } },
|
|
{ "funcIsReady" , HCF_RES_ADDR, {(void *)bspSm1553bChipReady } },
|
|
{ "funcAckIrq" , HCF_RES_ADDR, {(void *)bspSm1553bAckIrq } },
|
|
{ "funcReset" , HCF_RES_ADDR, {(void *)bspSm1553bReset } },
|
|
};
|
|
#define sm2130ResNum NELEMENTS(sm2130Resources)
|
|
|
|
const struct hcfDevice hcfDeviceList[] = {
|
|
#ifdef DRV_ARM_GICV3
|
|
{ "armGicDev", 0, VXB_BUSID_PLB, 0, armGICv3Num, armGICv3Resources},
|
|
#endif /* DRV_ARM_GIC */
|
|
{ "primeCellSioDev", 0, VXB_BUSID_PLB, 0, primeCellSioDev0Num , primeCellSioDev0Resources },
|
|
{ "primeCellSioDev", 1, VXB_BUSID_PLB, 0, primeCellSioDev1Num , primeCellSioDev1Resources },
|
|
|
|
#ifdef DRV_VXBEND_FTGMAC
|
|
{ "gmac", 0, VXB_BUSID_PLB, 0, gmac0Num, gmac0Resources},
|
|
// { "gmac", 1, VXB_BUSID_PLB, 0, gmac1Num, gmac1Resources},
|
|
#endif
|
|
|
|
#ifdef DRV_ARM_GEN_SYS_TIMER
|
|
{ "armGenTimer", 0, VXB_BUSID_PLB, 0, armGenSysTimerNum, armGenSysTimerResources },
|
|
#endif /* DRV_ARM_GEN_SYS_TIMER */
|
|
|
|
#ifdef DRV_ARM_GEN_AUX_TIMER
|
|
{ "armAuxTimer", 0, VXB_BUSID_PLB, 0, armAuxGenTimerNum, armAuxGenTimerResources },
|
|
#endif /* DRV_ARM_GEN_SYS_TIMER */
|
|
|
|
|
|
#ifdef DRV_PCIBUS_FT
|
|
{ "ftPcie", 0, VXB_BUSID_PLB, 0, ftPci0Num, ftPci0Resources },
|
|
#endif /* DRV_PCIBUS_M85XX */
|
|
|
|
#ifdef DRV_FTCAN
|
|
{ "ftCan", 0, VXB_BUSID_PLB, 0, ftCanDev0Num, ftCanDev0Resources },
|
|
{ "ftCan", 1, VXB_BUSID_PLB, 0, ftCanDev1Num, ftCanDev1Resources },
|
|
/*{ "ftCan", 2, VXB_BUSID_PLB, 0, ftCanDev2Num, ftCanDev2Resources },*/
|
|
#endif
|
|
|
|
#ifdef INCLUDE_FT_SD
|
|
{ "ftSdhci",0,VXB_BUSID_PLB, 0,ftSdhc0Num, ftSdhc0Resources },
|
|
#endif
|
|
|
|
#ifdef DRV_FTI2C
|
|
{ "ftI2c", 0, VXB_BUSID_PLB, 0, i2cDev0Num, i2cDev0Resources },
|
|
{ "ftI2c", 1, VXB_BUSID_PLB, 0, i2cDev1Num, i2cDev1Resources },
|
|
/* CAN1,CAN2 & I2C_2: ONLY choose ONE. (pad pin demux) */
|
|
/*
|
|
{ "ftI2c", 2, VXB_BUSID_PLB, 0, i2cDev2Num, i2cDev2Resources },
|
|
{ "ftI2c", 3, VXB_BUSID_PLB, 0, i2cDev3Num, i2cDev3Resources },
|
|
*/
|
|
#endif
|
|
#ifdef DRV_FTQSPI
|
|
{ FT_QSPI_NAME, 0, VXB_BUSID_PLB, 0, qspiNum, qspiResources },
|
|
#endif
|
|
|
|
#ifdef DRV_FTSPI
|
|
{ FT_SPI_NAME, 0, VXB_BUSID_PLB, 0, spiNum0, spiResources0 },
|
|
{ FT_SPI_NAME, 1, VXB_BUSID_PLB, 0, spiNum1, spiResources1 },
|
|
#endif
|
|
|
|
#ifdef DRV_FTGPIO
|
|
{ "ftGpio", 0, VXB_BUSID_PLB, 0, gpioDev0Num, gpioDev0Resources },
|
|
{ "ftGpio", 1, VXB_BUSID_PLB, 0, gpioDev1Num, gpioDev1Resources },
|
|
#endif
|
|
#ifdef DRV_FS_LITTLEFS
|
|
{ "littlefs", 0, VXB_BUSID_PLB, 0, lfsResNum, lfsResources},
|
|
#endif
|
|
{ "SM2130", 0, VXB_BUSID_SPI, 0, sm2130ResNum, sm2130Resources},
|
|
};
|
|
|
|
const int hcfDeviceNum = NELEMENTS(hcfDeviceList);
|
|
|
|
VXB_INST_PARAM_OVERRIDE sysInstParamTable[] =
|
|
{
|
|
{ NULL, 0, NULL, VXB_PARAM_END_OF_LIST, {(void *)0} }
|
|
};
|
|
|
|
|
|
|