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!163 update_2024_07_01

Fixed spi sending and receiving bugs
pull/164/head
liyilun 4 months ago
committed by huanghe
parent
commit
3a353d48ee
  1. 8
      doc/ChangeLog.md
  2. 4
      doc/reference/driver/fspim.md
  3. 48
      drivers/spi/fspim/fspim.c
  4. 4
      drivers/spi/fspim/fspim.h
  5. 5
      drivers/spi/fspim/fspim_intr.c

8
doc/ChangeLog.md

@ -1,3 +1,11 @@
#Phytium Standalone SDK 2024-06-28 ChangeLog
Change Log since 2024-06-26
## drivers
- repair spim driver bug
# Phytium Standalone SDK 2024-06-26 ChangeLog
Change Log since 2024-06-26

4
doc/reference/driver/fspim.md

@ -91,12 +91,12 @@ typedef struct
u32 length; /* Data length in transfer */
const void *tx_buff; /* Tx buffer beg */
void *rx_buff; /* Rx buffer beg */
const void *tx_buff_end; /* Tx buffer end */
void *rx_buff_end; /* Rx buffer end */
u32 tx_fifo_len; /* Depth of tx fifo */
u32 rx_fifo_len; /* Depth of rx fifo */
FSpimEvtHandler evt_handler[FSPIM_INTR_EVT_NUM]; /* event handler for interrupt */
void *evt_param[FSPIM_INTR_EVT_NUM]; /* parameters ptr of event handler */
u32 tx_count; /*transferred data in fifo*/
u32 rx_count; /*received data in fifo*/
} FSpim;
```

48
drivers/spi/fspim/fspim.c

@ -371,16 +371,19 @@ static fsize_t FSpimGetTxRound(FSpim *instance_p)
uintptr base_addr = instance_p->config.base_addr;
fsize_t tx_left_round, tx_fifo_room, rx_tx_gap;
tx_left_round = (fsize_t)(instance_p->tx_buff_end - instance_p->tx_buff) / data_width;
tx_left_round = (fsize_t)(instance_p->length - instance_p->tx_count) / data_width;
tx_fifo_room = instance_p->tx_fifo_len -
FSpimGetTxFifoLevel(base_addr);
rx_tx_gap = ((fsize_t)(instance_p->rx_buff_end - instance_p->rx_buff) -
(fsize_t)(instance_p->tx_buff_end - instance_p->tx_buff)) / data_width;
FSPIM_DEBUG("tx_left_round: %d, tx_fifo_room: %d, gap: %d",
rx_tx_gap = ((fsize_t)(instance_p->length - instance_p->rx_count) -
(fsize_t)(instance_p->length - instance_p->tx_count)) / data_width;
FSPIM_DEBUG("tx_left_round: %d, tx_fifo_room: %d, gap: %d, instance_p->tx_count: %ld",
tx_left_round,
tx_fifo_room,
((fsize_t)(instance_p->tx_fifo_len) - rx_tx_gap));
((fsize_t)(instance_p->tx_fifo_len) - rx_tx_gap),
instance_p->tx_count);
return min3(tx_left_round,
tx_fifo_room,
((fsize_t)(instance_p->tx_fifo_len) - rx_tx_gap));
@ -432,10 +435,9 @@ void FSpimFifoTx(FSpim *instance_p)
{
FASSERT(0);
}
instance_p->tx_buff += data_width;
}
instance_p->tx_count += data_width;
FSpimWriteData(base_addr, data);
FSPIM_DEBUG(" send 0x%x", data);
tx_round--;
@ -453,9 +455,9 @@ static fsize_t FSpimGetRxRound(FSpim *instance_p)
fsize_t data_width = instance_p->config.n_bytes;
uintptr base_addr = instance_p->config.base_addr;
fsize_t rx_left_round = (fsize_t)(instance_p->rx_buff_end - instance_p->rx_buff) / data_width;
FSPIM_DEBUG("left round %d, rx level %d", rx_left_round, FSpimGetRxFifoLevel(base_addr));
fsize_t rx_left_round = (fsize_t)(instance_p->length - instance_p->rx_count) / data_width;
FSPIM_DEBUG("left round %d, rx level %d,instance_p->rx_count %ld", rx_left_round, FSpimGetRxFifoLevel(base_addr),instance_p->rx_count);
return min(rx_left_round, (fsize_t)FSpimGetRxFifoLevel(base_addr));
}
@ -473,11 +475,10 @@ void FSpimFifoRx(FSpim *instance_p)
uintptr base_addr = instance_p->config.base_addr;
u32 data_width = instance_p->config.n_bytes;
u16 data;
while (rx_round)
{
data = FSpimReadData(base_addr);
if(instance_p->rx_buff)
if(instance_p->rx_buff)
{
if (FSPIM_1_BYTE == data_width)
{
@ -499,10 +500,9 @@ void FSpimFifoRx(FSpim *instance_p)
{
FASSERT(0);
}
instance_p->rx_buff += data_width;
}
instance_p->rx_buff += data_width;
instance_p->rx_count += data_width;
rx_round--;
}
@ -534,7 +534,7 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
FSPIM_ERROR("The device is not initialized!!!");
return FSPIM_ERR_NOT_READY;
}
FSPIM_DEBUG("buff address rx= %x, tx=%x\r\n", rx_buf,tx_buf);
FSpimSetEnable(base_addr, FALSE);
reg_val = FSpimGetCtrlR0(base_addr);
@ -559,12 +559,11 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
FSpimSetCtrlR0(base_addr, reg_val);
FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
instance_p->tx_count = 0;
instance_p->rx_count = 0;
instance_p->length = len;
instance_p->tx_buff = tx_buf;
instance_p->tx_buff_end = tx_buf + len;
instance_p->rx_buff = rx_buf;
instance_p->rx_buff_end = rx_buf + len;
FSPIM_DEBUG("tx buff@%p-%d, rx buff@%p-%d",
instance_p->tx_buff, len,
instance_p->rx_buff, len);
@ -572,12 +571,11 @@ FError FSpimTransferPollFifo(FSpim *instance_p, const void *tx_buf, void *rx_buf
FSpimSetEnable(base_addr, TRUE);
do
{
{
FSpimFifoTx(instance_p);
FSpimFifoRx(instance_p);
}
while (instance_p->rx_buff_end > instance_p->rx_buff);
while(instance_p->tx_count < len || instance_p->rx_count < len);
return ret;
}
@ -628,13 +626,11 @@ FError FSpimTransferByInterrupt(FSpim *instance_p, const void *tx_buf, void *rx_
FSpimSetCtrlR0(base_addr, reg_val);
FSpimMaskIrq(base_addr, FSPIM_IMR_ALL_BITS);
instance_p->tx_count = 0;
instance_p->rx_count = 0;
instance_p->length = len;
instance_p->tx_buff = tx_buf;
instance_p->tx_buff_end = instance_p->tx_buff + len;
instance_p->rx_buff = rx_buf;
instance_p->rx_buff_end = instance_p->rx_buff + len;
/* 设置中断触发的时机,fifo填满一半,或者所有的数据填完 */
tx_level = min(instance_p->tx_fifo_len / 2, instance_p->length / data_width);
FSpimSetTxFifoThreshold(base_addr, tx_level);

4
drivers/spi/fspim/fspim.h

@ -164,12 +164,12 @@ typedef struct
u32 length; /* Data length in transfer */
const void *tx_buff; /* Tx buffer beg */
void *rx_buff; /* Rx buffer beg */
const void *tx_buff_end; /* Tx buffer end */
void *rx_buff_end; /* Rx buffer end */
u32 tx_fifo_len; /* Depth of tx fifo */
u32 rx_fifo_len; /* Depth of rx fifo */
FSpimEvtHandler evt_handler[FSPIM_INTR_EVT_NUM]; /* event handler for interrupt */
void *evt_param[FSPIM_INTR_EVT_NUM]; /* parameters ptr of event handler */
u32 tx_count;
u32 rx_count;
} FSpim;
/************************** Variable Definitions *****************************/

5
drivers/spi/fspim/fspim_intr.c

@ -70,7 +70,6 @@ void FSpimInterruptHandler(s32 vector, void *param)
FSpim *instance_p = (FSpim *)param;
uintptr base_addr = instance_p->config.base_addr;
u32 intr_status = FSPIM_RIS_R_ALL_BITS & FSPIM_READ_REG32(base_addr, FSPIM_RIS_R_OFFSET);
if (0 == intr_status)
{
return;
@ -99,8 +98,7 @@ void FSpimInterruptHandler(s32 vector, void *param)
}
FSpimFifoRx(instance_p); /* 检查 RX Fifo是否为空,如果不为空则接收数据 */
if (instance_p->rx_buff_end == instance_p->rx_buff) /* RX 缓冲区已满,停止填入发送数据 */
if(instance_p->rx_count >= instance_p->length) /* RX 缓冲区已满,停止填入发送数据 */
{
FSpimMaskIrq(base_addr, FSPIM_IMR_TXEIS);
FSPIM_CALL_INTR_EVT_HANDLDER(instance_p, FSPIM_INTR_EVT_RX_DONE);
@ -113,7 +111,6 @@ void FSpimInterruptHandler(s32 vector, void *param)
FSpimFifoTx(instance_p);
FSpimUmaskIrq(base_addr, FSPIM_IMR_TXEIS);
}
return;
}

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