Browse Source

!157 solve the i2c bug without device

pull/158/head
wangzongqiang 5 months ago
committed by wangxiaodong
parent
commit
57e28e517e
  1. 4
      arch/armv8/aarch32/funwind.c
  2. 2
      arch/armv8/aarch64/fexception.c
  3. 11
      arch/armv8/aarch64/fmmu.c
  4. 2
      arch/armv8/common/fpmu_perf.c
  5. 10
      arch/armv8/common/fpsci.c
  6. 33
      common/felf.c
  7. 5
      common/finterrupt.c
  8. 2
      common/fprintk.c
  9. 1
      common/ftypes.h
  10. 18
      doc/ChangeLog.md
  11. 2
      drivers/dma/fddma/fddma.c
  12. 2
      drivers/eth/fgmac/fgmac.c
  13. 2
      drivers/i2c/fi2c/fi2c.c
  14. 9
      drivers/i2c/fi2c/fi2c.h
  15. 24
      drivers/i2c/fi2c/fi2c_hw.c
  16. 25
      drivers/i2c/fi2c/fi2c_hw.h
  17. 24
      drivers/i2c/fi2c/fi2c_intr.c
  18. 43
      drivers/i2c/fi2c/fi2c_master.c
  19. 3
      drivers/i2s/fes8336/fes8336.c
  20. 2
      drivers/i2s/fi2s/fi2s.c
  21. 2
      drivers/i3c/fi3c/fi3c_master.c
  22. 6
      drivers/iomux/fioctrl/fioctrl.c
  23. 10
      drivers/iomux/fiopad/fiopad_hw.h
  24. 1
      drivers/ipc/fsemaphore/fsemaphore_hw.h
  25. 2
      drivers/mio/fmio/fmio.c
  26. 1
      drivers/mmc/fsdmmc/fsdmmc.c
  27. 2
      drivers/nand/fnand/fnand_bbm.c
  28. 1
      drivers/nand/fnand/fnand_common_cmd.c
  29. 1
      drivers/nand/fnand/fnand_id.c
  30. 2
      drivers/nand/fnand/fnand_intr.c
  31. 1
      drivers/nand/fnand/fnand_option.c
  32. 2
      drivers/pwm/fpwm/fpwm.c
  33. 1
      drivers/pwm/fpwm/fpwm_intr.c
  34. 11
      drivers/qspi/fqspi/fqspi_flash.c
  35. 1
      drivers/qspi/fqspi/fqspi_hw.c
  36. 8
      drivers/sata/fsata/fsata.c
  37. 3
      drivers/sata/fsata/fsata_intr.c
  38. 3
      drivers/scmi/fscmi_mhu/fscmi_base.c
  39. 3
      drivers/scmi/fscmi_mhu/fscmi_perf.c
  40. 5
      drivers/scmi/fscmi_mhu/fscmi_sensors.c
  41. 2
      drivers/serial/fpl011/fpl011_options.c
  42. 1
      drivers/timer/ftimer_tacho/ftimer.c
  43. 2
      example/media/lvgl_demo_test/src/cmd_lvgl.c
  44. 8
      example/media/lvgl_demo_test/src/lvgl_disp_test.c
  45. 9
      example/media/media_test/src/media_test_example.c
  46. 1
      example/peripherals/can/can/src/can_box_example.c
  47. 2
      example/peripherals/can/canfd/inc/canfd_id_filter_example.h
  48. 2
      example/peripherals/can/canfd/inc/canfd_intr_loopback_mode_example.h
  49. 2
      example/peripherals/can/canfd/inc/canfd_polled_loopback_mode_example.h
  50. 2
      example/peripherals/can/canfd/main.c
  51. 5
      example/peripherals/can/canfd/src/canfd_box_example.c
  52. 2
      example/peripherals/can/canfd/src/canfd_id_filter_example.c
  53. 2
      example/peripherals/can/canfd/src/canfd_intr_loopback_mode_example.c
  54. 2
      example/peripherals/can/canfd/src/canfd_polled_loopback_mode_example.c
  55. 1
      example/peripherals/generic_timer/src/cmd_timer.c
  56. 2
      example/peripherals/generic_timer/src/physical_counter.c
  57. 2
      example/peripherals/generic_timer/src/virtual_counter.c
  58. 2
      example/peripherals/i2c/README.md
  59. 16
      example/peripherals/i2c/configs/pd2308_aarch64_demo_i2c.config
  60. 4
      example/peripherals/i2c/configs/phytiumpi_aarch32_firefly_i2c.config
  61. 6
      example/peripherals/i2c/configs/phytiumpi_aarch64_firefly_i2c.config
  62. 2
      example/peripherals/i2c/sdkconfig
  63. 2
      example/peripherals/i2c/sdkconfig.h
  64. 28
      example/peripherals/i2c/src/cmd_i2c.c
  65. 5
      example/peripherals/i2c/src/i2c_ds1339_rtc_example.c
  66. 67
      example/peripherals/i2c/src/i2c_master_slave_example.c
  67. 1
      example/peripherals/i2s/i2s_board/src/i2s_rx_example.c
  68. 1
      example/peripherals/i2s/i2s_board/src/i2s_tx_example.c
  69. 1
      example/peripherals/i2s/i2s_dp/src/i2s_dp_rx_example.c
  70. 1
      example/peripherals/i2s/i2s_dp/src/i2s_dp_tx_example.c
  71. 1
      example/peripherals/i3c/src/i3c_at24c04_eeprom_example.c
  72. 2
      example/peripherals/i3c/src/i3c_ds1339_rtc_example.c
  73. 2
      example/peripherals/iopad/src/iopad_set_config_example.c
  74. 5
      example/peripherals/pin/README.md
  75. 0
      example/peripherals/pin/figs/firefly_three_gpio.png
  76. 2
      example/peripherals/pin/src/pin_gpio_low_level_example.c
  77. 4
      example/peripherals/pin/src/pin_gpio_pwm_example.c
  78. 5
      example/peripherals/pmbus/src/pmbus_mp_detect_example.c
  79. 5
      example/peripherals/pmbus/src/pmbus_mp_voltage_example.c
  80. 2
      example/peripherals/pwm/main.c
  81. 1
      example/peripherals/qspi/src/qspi_dual_flash_stack_example.c
  82. 2
      example/peripherals/sata/sata_pcie/src/sata_pcie_common.c
  83. 2
      example/peripherals/sd/src/sdif/sdif_tf_read_write_example.c
  84. 7
      example/peripherals/spi/src/spim_common.c
  85. 5
      example/peripherals/timer/tacho/src/tacho_common.c
  86. 1
      example/storage/fatfs/src/cmd_fatfs.c
  87. 1
      example/storage/memory_pool_test/src/memory_pool_basic_example.c
  88. 1
      example/system/amp/libmetal_test/apu_running/src/ipi_shmem_demo.c
  89. 1
      example/system/amp/libmetal_test/apu_running/src/ipi_waking_up_demo.c
  90. 1
      example/system/amp/libmetal_test/apu_running/src/shmem_latency_demo.c
  91. 1
      example/system/amp/libmetal_test/apu_running/src/shmem_throughput_demo.c
  92. 3
      example/system/amp/libmetal_test/rpu_running/main.c
  93. 1
      example/system/amp/libmetal_test/rpu_running/src/ipi_shmem_demod.c
  94. 1
      example/system/amp/libmetal_test/rpu_running/src/ipi_waking_up_demod.c
  95. 1
      example/system/amp/libmetal_test/rpu_running/src/shmem_atomic_demod_rpu.c
  96. 1
      example/system/amp/libmetal_test/rpu_running/src/shmem_latency_demod.c
  97. 3
      example/system/amp/libmetal_test/rpu_running/src/shmem_throughput_demod.c
  98. 1
      example/system/cxx/cryptopp/src/cmd_cyptopp.c
  99. 3
      example/system/nested_interrupt/src/nested_interrupt_timer_example.c
  100. 9
      example/system/newlib_test/src/math.c

4
arch/armv8/aarch32/funwind.c

@ -66,9 +66,6 @@ extern u32 __undef_stack;
(u32)(ptr) + offset; \
})
static const struct FUnwindIndexEntries * __origin_unwind_idx = NULL ;
// const struct FUnwindIndexEntries * origin = NULL ;
extern const struct FUnwindIndexEntries __exidx_start[] ;
extern const struct FUnwindIndexEntries __exidx_end[] ;
@ -361,7 +358,6 @@ static const struct FUnwindIndexEntries *FUnwindSearchIndex(uintptr addr,
const struct FUnwindIndexEntries ** origin,
const struct FUnwindIndexEntries * stop)
{
uintptr addr_prel31 ;
const struct FUnwindIndexEntries * idx ;
if(*origin == NULL)

2
arch/armv8/aarch64/fexception.c

@ -207,7 +207,7 @@ static void FExcPrintEcCause(u32 ec)
f_printk("\r\n");
}
static void FExcPrintIssDfsc(u32 dfsc)
_UNUSED static void FExcPrintIssDfsc(u32 dfsc)
{
switch (dfsc)
{

11
arch/armv8/aarch64/fmmu.c

@ -224,7 +224,7 @@ static inline unsigned int TableIndex(u64 *pte)
{
unsigned int i = (pte - xlat_tables) / LN_XLAT_NUM_ENTRIES;
FASSERT_MSG(i < CONFIG_MAX_XLAT_TABLES, "table %x out of range", pte);
FASSERT_MSG(i < CONFIG_MAX_XLAT_TABLES, "table %p out of range", pte);
return i;
}
@ -368,7 +368,7 @@ static u64 *ExpandToTable(u64 *pte, unsigned int level)
MMU_DEBUG("expanding PTE 0x%016llx into table [%d]%x\r\n",
desc, TableIndex(table), table);
FASSERT_MSG(IsBlockDesc(desc), "");
FASSERT_MSG(IsBlockDesc(desc), " ");
if (level + 1 == XLAT_LAST_LEVEL)
{
@ -683,8 +683,6 @@ static u64 GetTcr(int el)
static void EnableMmuEl1(struct ArmMmuPtables *ptables, unsigned int flags)
{
u64 val;
/* Set MAIR, TCR and TBBR registers */
__asm__ volatile("msr mair_el1, %0"
:
@ -777,7 +775,7 @@ static fsize_t MemRegionAlign(uintptr *aligned_addr, fsize_t *aligned_size,
*aligned_addr = rounddown(addr, align) ;
addr_offset = addr - *aligned_addr ;
*aligned_size = roundup(size +, align);
*aligned_size = roundup(size, align);
return addr_offset;
}
@ -793,7 +791,7 @@ static fsize_t MemRegionAlign(uintptr *aligned_addr, fsize_t *aligned_size,
*/
void FSetTlbAttributes(uintptr addr, fsize_t size, u32 attrib)
{
uintptr_t aligned_phys, addr_offset;
uintptr_t aligned_phys;
size_t aligned_size;
MemRegionAlign(&aligned_phys, &aligned_size,
addr, size, CONFIG_MMU_PAGE_SIZE);
@ -825,7 +823,6 @@ void ArchMemUnmap(uintptr addr, fsize_t size)
int ArchPagePhysGet(uintptr virt, uintptr *phys)
{
u64 par;
int key;
__asm__ volatile("at S1E1R, %0"
:

2
arch/armv8/common/fpmu_perf.c

@ -154,7 +154,6 @@ void FPmuFeatureProbeDebugPrint(const FPmu *instance_p)
*/
static FError FPmuFeatureProbe(FPmu *instance_p)
{
int pmuver ;
u32 pmceid[2] ;
@ -451,7 +450,6 @@ void FPmuIrqHandler(s32 vector, void *args)
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
u32 overflowed_flg ;
u32 i ;
/*
* Get and reset the IRQ flags
*/

10
arch/armv8/common/fpsci.c

@ -182,13 +182,6 @@ int FPsciAffinityInfo(unsigned long target_affinity, u32 lowest_affinity_level)
struct FSmcccRes res;
FASSERT((fpsci_support_bit_flg & (FPSCI_AFFINITY_INFO_AARCH32_BIT|FPSCI_AFFINITY_INFO_AARCH64_BIT)) != 0);
FASSERT((*f_psci_invoke));
unsigned long cpu_on_id ;
#if defined(FAARCH64_USE)
cpu_on_id = FPSCI_CPU_ON_AARCH64 ;
#else
cpu_on_id = FPSCI_CPU_ON_AARCH32;
#endif
(*f_psci_invoke)(FPSCI_FAFFINITY_INFO_AARCH32, target_affinity, lowest_affinity_level, 0, 0, 0, 0, 0, &res);
return res.a0;
@ -213,7 +206,7 @@ void FPsciSystemReset(u32 reset_type) {
* @msg: This function checks for the availability of various PSCI features and sets the corresponding bits in the 'fpsci_support_bit_flg' global flag accordingly.
* @return: This function does not return a value.
*/
static void FPsciCheckFeatures(void)
_UNUSED static void FPsciCheckFeatures(void)
{
FPSCI_INFO("Checking PSCI features...\r\n");
fpsci_support_bit_flg = 0 ;
@ -336,7 +329,6 @@ static void FSmccInit(int method) {
}
int FPsciInit(void) {
int psci_version = 0;
FSmccInit(0);
#if defined(FAARCH64_USE)
fpsci_support_bit_flg |= FPSCI_AARCH64_INIT_STATE;

33
common/felf.c

@ -761,18 +761,6 @@ static unsigned long ElfLoadElf64ImagePhdr(unsigned long addr)
++phdr;
}
if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags & EF_PPC64_ELFV1_ABI))
{
/*
* For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
* descriptor pointer with the first double word being the
* address of the entry point of the function.
*/
uintptr_t addr = ehdr->e_entry;
return *(Elf64_Addr *)addr;
}
return ehdr->e_entry;
}
@ -832,19 +820,6 @@ static unsigned long ElfLoadElf64ImageShdr(unsigned long addr)
FCacheDCacheFlushRange((uintptr)shdr->sh_addr, shdr->sh_size);
}
if (ehdr->e_machine == EM_PPC64 && (ehdr->e_flags &
EF_PPC64_ELFV1_ABI))
{
/*
* For the 64-bit PowerPC ELF V1 ABI, e_entry is a function
* descriptor pointer with the first double word being the
* address of the entry point of the function.
*/
uintptr addr = ehdr->e_entry;
return *(Elf64_Addr *)addr;
}
return ehdr->e_entry;
}
@ -1036,7 +1011,7 @@ static FError Elf64GetTargetSection(unsigned long addr,char *section_name ,u8 *d
continue;
}
if(strcmp(section_name, &strtab[shdr->sh_name]) == 0)
if(strcmp(section_name, (const char *)&strtab[shdr->sh_name]) == 0)
{
f_printk("%sing %s @ 0x%08lx (%ld bytes) \r\n",
(shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
@ -1116,7 +1091,7 @@ static FError Elf32GetTargetSection(unsigned long addr,char *section_name ,u8 *d
continue;
}
if (strcmp(section_name, &strtab[shdr->sh_name]) == 0)
if (strcmp(section_name, (const char *)&strtab[shdr->sh_name]) == 0)
{
printf("%sing %s @ 0x%08lx (%ld bytes)",
(shdr->sh_type == SHT_NOBITS) ? "Clear" : "Load",
@ -1161,10 +1136,6 @@ static FError Elf32GetTargetSection(unsigned long addr,char *section_name ,u8 *d
FError ElfGetSection(unsigned long addr, char *section_name, u8 *data_get, u32 *length_p)
{
Elf32_Ehdr *ehdr; /* ELF 文件头指针 */
Elf32_Shdr *shdr; /* 节头指针 */
unsigned char *strtab = 0; /* 字符串表指针 */
unsigned char *image; /* 二进制映像指针 */
int i; /* 循环计数器 */
/* 检查 ELF 文件的类型 */
ehdr = (Elf32_Ehdr *)addr;

5
common/finterrupt.c

@ -91,7 +91,6 @@ FError InterruptSetTargetCpus(int int_id, u32 cpu_id)
{
u64 cluster, temp_cluster;
FError ret;
u32 cluster_id, target_list;
FASSERT_MSG(interrupt_handler_p != NULL, "Please init interrupt component");
@ -217,7 +216,6 @@ void InterruptSetPriority(int int_id, unsigned int priority)
*/
unsigned int InterruptGetPriority(int int_id)
{
u32 priority;
FASSERT_MSG(interrupt_handler_p != NULL, "Please init interrupt component");
return FGicGetPriority(interrupt_handler_p, int_id);
}
@ -311,12 +309,9 @@ unsigned int InterruptGetPriorityGroupBits(void)
*/
void InterruptInstall(int int_id, IrqHandler handler, void *param, const char *name)
{
IrqHandler old_handler = NULL;
(void)name;
if (int_id < MAX_HANDLERS)
{
old_handler = isr_table[int_id].handler;
if (handler != NULL)
{
isr_table[int_id].handler = handler;

2
common/fprintk.c

@ -396,7 +396,7 @@ start:
}
}
static int f_vprintf(const char *restrict format, va_list vargs)
static void f_vprintf(const char *restrict format, va_list vargs)
{
struct str_context ctx = {0};
cbvprintf(char_out, &ctx, format, vargs);

1
common/ftypes.h

@ -80,6 +80,7 @@ typedef u32 tick_t;
#define _INLINE inline
#define _ALWAYS_INLINE inline __attribute__((always_inline))
#define _WEAK __attribute__((weak))
#define _UNUSED __attribute__((unused))
#define FUNUSED(x) ((void)x)

18
doc/ChangeLog.md

@ -1,3 +1,21 @@
# Phytium Standalone SDK 2024-05-31 ChangeLog
Change Log since 2024-05-23
## example
- add i2c example for solving i2c communication problem without device
## drivers
- add some config for adding abort status
# Phytium Standalone SDK 2024-05-23 ChangeLog
Change Log since 2024-05-23
- Eliminating Partial Compilation Warnings
# Phytium Standalone SDK 2024-05-23 ChangeLog
Change Log since 2024-05-23

2
drivers/dma/fddma/fddma.c

@ -155,7 +155,6 @@ FError FDdmaChanConfigure(FDdma *const instance_p, FDdmaChanIndex channel_id , c
FError ret = FDDMA_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
u32 reg_val;
if (FDdmaIsChanRunning(base_addr, channel_id))
{
@ -325,7 +324,6 @@ void FDdmaStart(FDdma *const instance_p)
void FDdmaStop(FDdma *const instance_p)
{
FASSERT(instance_p);
FError ret = FDDMA_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
FDdmaDisable(base_addr);

2
drivers/eth/fgmac/fgmac.c

@ -193,8 +193,6 @@ static FError FGmacReset(FGmac *instance_p)
FGmacMacAddr mac_addr;
uintptr base_addr = instance_p->config.base_addr;
FError ret = FGMAC_SUCCESS;
u32 reg_val;
/* backup mac address before software reset */
memset(mac_addr, 0, sizeof(mac_addr));

2
drivers/i2c/fi2c/fi2c.c

@ -180,7 +180,7 @@ static FError FI2cReset(FI2c *instance_p)
const char *FI2cErrorToMessage(FError error)
{
const char *msg = NULL;
if (FI2C_SUCCESS != error && (FI2C_ERR_CODE_PREFIX != error & (FT_ERRCODE_SYS_MODULE_MASK | FT_ERRCODE_SUB_MODULE_MASK)))
if (FI2C_SUCCESS != error && ((FI2C_ERR_CODE_PREFIX != error) & (FT_ERRCODE_SYS_MODULE_MASK | FT_ERRCODE_SUB_MODULE_MASK)))
{
/* if input error do not belong to this module */
return msg;

9
drivers/i2c/fi2c/fi2c.h

@ -46,9 +46,10 @@ extern "C"
#define FI2C_ERR_TIMEOUT FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 3)
#define FI2C_ERR_NOT_SUPPORT FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 4)
#define FI2C_ERR_INVAL_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 5)
#define FI2C_ERR_TRANS_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 6)
/* add up new error code above and plust FI2C_ERR_CODE_MAX by ONE*/
#define FI2C_ERR_CODE_MAX FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 6)
#define FI2C_ERR_CODE_MAX FT_MAKE_ERRCODE(ErrModBsp, ErrBspI2c, 7)
#define FI2C_ERR_CODE_PREFIX FI2C_ERR_CODE_MAX & (FT_ERRCODE_SYS_MODULE_MASK | FT_ERRCODE_SUB_MODULE_MASK)
#define FI2C_NUM_OF_ERR_CODE FI2C_ERR_CODE_MAX & FT_ERRCODE_TAIL_VALUE_MASK
@ -58,7 +59,7 @@ extern "C"
#define STATUS_IDLE 0x0
#define STATUS_WRITE_IN_PROGRESS 0x1
#define STATUS_READ_IN_PROGRESS 0x2
#define STATUS_ERROR 0x3
enum
{
FI2C_MASTER = 0, /* i2c主设备 */
@ -88,6 +89,7 @@ enum/*slave模式回调函数事件值*/
FI2C_EVT_SLAVE_READ_PROCESSED, /*在Slave发送模式下,发送完数据的最后一个字节后,在规定时间内没有收到 Master 端的回应*/
FI2C_EVT_SLAVE_WRITE_RECEIVED, /*Slave收到主机发送的数据,需要存下*/
FI2C_EVT_SLAVE_STOP, /*I2C总线接口上是否产生了STOP。与控制器工作在Master模式还是 Slave 模式无关。*/
FI2C_EVT_SLAVE_ABORT, /*I2C总线接口上是否产生了ABORT*/
FI2C_SLAVE_INTR_EVT_NUM
}; /* slave mode evt */
@ -197,6 +199,9 @@ void FI2cSlaveIntrHandler(s32 vector, void *param);
/* 注册I2C从机中断事件函数 */
void FI2cSlaveRegisterIntrHandler(FI2c *instance_p, u32 evt, FI2cEvtHandler handler);
/* 主机模式发送数据 */
FError FI2cMasterStartTrans(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u16 flag);
#ifdef __cplusplus
}
#endif

24
drivers/i2c/fi2c/fi2c_hw.c

@ -129,7 +129,7 @@ static FError FI2cCalcTiming(u32 bus_clk_hz, u32 spk_cnt, FI2cSpeedCfg *speed_cf
const FI2cSpeedModeInfo *info_p = &I2C_SPEED_CFG[speed_mode];
int fall_cnt, rise_cnt, min_t_low_cnt, min_t_high_cnt;
int hcnt, lcnt, period_cnt, diff, tot;
int sda_hold_time_ns, scl_rise_time_ns, scl_fall_time_ns;
int scl_rise_time_ns, scl_fall_time_ns;
period_cnt = bus_clk_hz / info_p->speed;
scl_rise_time_ns = info_p->def_risetime_ns;
@ -320,7 +320,6 @@ FError FI2cWaitStatus(uintptr addr, u32 stat_bit)
*/
FError FI2cWaitBusBusy(uintptr addr)
{
u32 timeout = FI2C_TIMEOUT;
u32 ret = FI2C_SUCCESS;
if (((FI2C_READ_REG32(addr, FI2C_STATUS_OFFSET)) & FI2C_STATUS_MST_ACTIVITY) &&
@ -344,7 +343,6 @@ FError FI2cSetTar(uintptr addr, u32 tar_addr)
{
u32 enable_status = FI2cGetEnable(addr);
u32 ret = FI2C_SUCCESS;
u32 reg_val = 0;
if (FI2C_IC_ENABLE == enable_status)
{
@ -375,7 +373,6 @@ FError FI2cSetSar(uintptr addr, u32 sar_addr)
{
u32 enable_status = FI2cGetEnable(addr);
u32 ret = FI2C_SUCCESS;
u32 reg_val = 0;
if (FI2C_IC_ENABLE == enable_status)
{
@ -484,4 +481,23 @@ u32 FI2cClearIntrBits(uintptr addr, u32 *last_err_p)
}
return stat;
}
void FI2cClearAbort(uintptr addr)
{
u32 reg_val;
u32 timeout = FI2C_TIMEOUT;
do
{
FI2C_CLEAR_INTR_STATUS(addr);
if ((FI2C_READ_REG32(addr, FI2C_TX_ABRT_SOURCE_OFFSET)) == 0)
{
return;
}
}
while (0 != timeout--);
FI2C_ERROR("Timeout when clear abort.");
return;
}

25
drivers/i2c/fi2c/fi2c_hw.h

@ -206,6 +206,30 @@ extern "C"
#define FI2C_SLV_DISABLED_WHILE_BUSY (0x1 << 1)
#define FI2C_SLV_RX_DATA_LOST (0x1 << 2)
/** @name FI2C_DMA_CR_OFFSET Register
*/
#define FI2C_DMA_CR_TDMA_EN (0x1 << 0)
#define FI2C_DMA_CR_RDMA_EN (0x1 << 1)
/** @name FI2C_TX_ABRT_SOURCE_OFFSET Register
*/
#define FI2C_ABRT_7B_ADDR_NOACK (0x1 << 0) /*7位地址模式下,地址发送没有被任何从机承认*/
#define FI2C_ABRT_10ADDR1_NOACK (0x1 << 1) /*10位地址模式下,第一个地址发送没有被任何从机承认*/
#define FI2C_ABRT_10ADDR2_NOACK (0x1 << 2) /*10位地址模式下,第二个地址发送没有被任何从机承认*/
#define FI2C_ABRT_TXDATA_NOACK (0x1 << 3) /*数据发送没有被任何从机承认*/
#define FI2C_ABRT_GCALL_NOACK (0x1 << 4) /*General Call格式的I2C通信没有被任何从机承认*/
#define FI2C_ABRT_GCALL_READ (0x1 << 5) /*General Call格式的I2C通信,但用户在CALL之后的字节被编程为读*/
#define FI2C_ABRT_HS_ACKDET (0x1 << 6) /*高速模式下,从机响应超时,或主机未响应*/
#define FI2C_ABRT_SBYTE_ACKDET (0x1 << 7)/*主机发送一个start字节,但start字节已被发送*/
#define FI2C_ABRT_HS_NORSTRT (0x1 << 8)/*高速模式下,主机未产生START或RESTART信号*/
#define FI2C_ABRT_SBYTE_NORSTRT (0x1 << 9) /*restart信号未被发送*/
#define FI2C_ABRT_10B_RD_NORSTRT (0x1 << 10) /*10位地址模式下,从机未产生START或RESTART信号*/
#define FI2C_ABRT_MASTER_DIS (0x1 << 11)/*主机禁止I2C通信*/
#define FI2C_ABRT_LOST (0x1 << 12) /*I2C总线忙,无法响应I2C命令,失去仲裁*/
#define FI2C_ABRT_SLVFLUSH_TXFIFO (0x1 << 13) /*从机收到读命令并且发送fifo中有数据,从设备发出TX_ABRT中断刷新发送fifo*/
#define FI2C_ABRT_SLV_ARBLOST (0x1 << 14)/*从机丢失仲裁,无法响应I2C命令*/
#define FI2C_ABRT_SLVRD_INTX (0x1 << 15) /*从模式下,请求将数据传到主机,用户在DATA数据寄存器写1*/
/* High and low times in different speed modes (in ns) */
#define FI2C_MIN_SS_SCL_HIGHTIME 4000
#define FI2C_MIN_SS_SCL_LOWTIME 4700
@ -267,6 +291,7 @@ FError FI2cSetTar(uintptr addr, u32 tar_addr);
FError FI2cSetSar(uintptr addr, u32 sar_addr);
FError FI2cFlushRxFifo(uintptr addr);
u32 FI2cClearIntrBits(uintptr addr, u32 *last_err_p);
void FI2cClearAbort(uintptr addr);
#ifdef __cplusplus
}

24
drivers/i2c/fi2c/fi2c_intr.c

@ -98,18 +98,17 @@ static void FI2cMasterIntrTxEmptyHandler(FI2c *instance_p)
{
FASSERT(instance_p);
uintptr base_addr = instance_p->config.base_addr;
const u8 *buf_p = instance_p->txframe.data_buff;
u32 intr_mask;
u32 buf_len;
u32 reg_val;
u32 reg_val = 0;
u32 rx_limit, tx_limit;
buf_len = instance_p->txframe.tx_total_num - instance_p->txframe.tx_cnt;
rx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
tx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_TXFLR_OFFSET);
while (buf_len > 0 & rx_limit > 0 & tx_limit > 0)
while ((buf_len > 0) && (rx_limit > 0) && (tx_limit > 0))
{
if (1 == buf_len)
{
@ -171,8 +170,7 @@ static void FI2cMasterIntrRxFullHandler(FI2c *instance_p)
u32 intr_mask;
uintptr base_addr = instance_p->config.base_addr;
u8 emptyfifo = FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
u32 i = 0u;
u32 reg_val;
u32 i = 0U;
for (i = 0; i < emptyfifo; i++)
{
*((u8 *)(instance_p->rxframe.data_buff++)) = FI2C_READ_DATA(base_addr);
@ -215,8 +213,8 @@ void FI2cMasterIntrHandler(s32 vector, void *param)
if (stat & FI2C_INTR_TX_ABRT) /* trans abort error */
{
FI2C_ERROR("last error: 0x%x", last_err);
FI2C_ERROR("abort source: 0x%x", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
instance_p->status = STATUS_IDLE;
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
instance_p->status = STATUS_ERROR;
FI2C_SET_INTRRUPT_MASK(base_addr, 0); /* disable all intr */
FI2C_READ_REG32(base_addr, FI2C_CLR_TX_ABRT_OFFSET);
FI2C_WRITE_REG32(base_addr, FI2C_ENABLE_OFFSET, 1);
@ -299,8 +297,8 @@ FError FI2cMasterSetupIntr(FI2c *instance_p, u32 mask)
return FI2C_ERR_INVAL_STATE;
}
/* disable all i2c irq */
FI2C_CLEAR_INTR_STATUS(base_addr);
/* disable all i2c irq and abort*/
FI2cClearAbort(base_addr);
for (evt = FI2C_EVT_MASTER_TRANS_ABORTED; evt < FI2C_MASTER_INTR_EVT_NUM; evt++)
{
@ -382,8 +380,10 @@ void FI2cSlaveIntrHandler(s32 vector, void *param)
if (stat & FI2C_INTR_TX_ABRT) /* trans abort error */
{
instance_p->status = STATUS_ERROR;
FI2cSlaveCallEvtHandler(instance_p, FI2C_EVT_SLAVE_ABORT, &val);
FI2C_ERROR("last error: 0x%x", last_err);
FI2C_ERROR("abort source: 0x%x", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
}
return;
@ -429,8 +429,8 @@ FError FI2cSlaveSetupIntr(FI2c *instance_p)
return FI2C_ERR_INVAL_STATE;
}
/* disable all i2c irq */
FI2C_CLEAR_INTR_STATUS(base_addr);
/* disable all i2c irq and abort*/
FI2cClearAbort(base_addr);
for (evt = FI2C_EVT_SLAVE_READ_REQUESTED; evt < FI2C_SLAVE_INTR_EVT_NUM; evt++)
{

43
drivers/i2c/fi2c/fi2c_master.c

@ -55,7 +55,7 @@
* @param {u8} mem_byte_len, Size of internal memory address 1->8bit ~ 4->32bit
* @param {u8} flag ,for cmd reg STOP,RESTART.
*/
static FError FI2cMasterStartTrans(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u16 flag)
FError FI2cMasterStartTrans(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u16 flag)
{
FASSERT(instance_p);
uintptr base_addr = instance_p->config.base_addr;
@ -79,6 +79,12 @@ static FError FI2cMasterStartTrans(FI2c *instance_p, u32 mem_addr, u8 mem_byte_l
{
break;
}
if (FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET) != 0)
{
ret = FI2C_ERR_TRANS_STATE;
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
break;
}
if (FI2C_GET_STATUS(base_addr) & FI2C_STATUS_TFNF)
{
addr_len--;
@ -108,7 +114,7 @@ static FError FI2cMasterStopTrans(FI2c *instance_p)
FASSERT(instance_p);
FError ret = FI2C_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
u32 reg_val;
u32 reg_val = 0;
u32 timeout = 0;
FI2C_INFO("GET MASTER STOP, stat: 0x%x, 0x%x", FI2C_READ_INTR_STAT(base_addr),
@ -150,7 +156,6 @@ FError FI2cMasterReadPoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
{
FError ret = FI2C_SUCCESS;
FASSERT(instance_p);
u32 mask;
u32 reg_val;
u32 tx_len = buf_len;
u32 rx_len = buf_len;
@ -178,11 +183,17 @@ FError FI2cMasterReadPoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
/*for trigger rx intr*/
while (tx_len > 0 || rx_len > 0)
{
if (FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET) != 0)
{
ret = FI2C_ERR_TRANS_STATE;
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
break;
}
/* code */
rx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
tx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_TXFLR_OFFSET);
while (tx_len > 0 & rx_limit > 0 & tx_limit > 0)
while ((tx_len > 0) && (rx_limit > 0) && (tx_limit > 0))
{
/* code */
if (tx_len == 1)
@ -202,7 +213,7 @@ FError FI2cMasterReadPoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
}
u8 rx_tem = FI2C_READ_REG32(base_addr, FI2C_RXFLR_OFFSET);
while (rx_tem > 0 & rx_len > 0)
while ((rx_tem > 0) && (rx_len > 0))
{
/* code */
if (FI2C_GET_STATUS(base_addr) & FI2C_STATUS_RFNE)
@ -266,8 +277,14 @@ FError FI2cMasterWritePoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
}
while (buf_idx)
{
if (FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET) != 0)
{
ret = FI2C_ERR_TRANS_STATE;
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
break;
}
tx_limit = FI2C_IIC_FIFO_MAX_LV - FI2C_READ_REG32(base_addr, FI2C_TXFLR_OFFSET);
while (tx_limit > 0 & buf_idx > 0)
while ((tx_limit > 0) && (buf_idx > 0))
{
if (FI2C_GET_STATUS(base_addr) & FI2C_STATUS_TFNF)
{
@ -295,6 +312,7 @@ FError FI2cMasterWritePoll(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
FI2C_ERROR("Timeout in i2c master write.");
break;
}
}
}
if (FI2C_SUCCESS == ret)
@ -319,7 +337,6 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
FError ret = FI2C_SUCCESS;
FASSERT(instance_p);
u32 mask;
u32 reg_val;
u32 trans_timeout = 0;
if (FT_COMPONENT_IS_READY != instance_p->is_ready)
@ -332,7 +349,11 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
FI2C_ERROR("i2c work mode shall be master.");
return FI2C_ERR_INVAL_STATE;
}
if (instance_p->status == STATUS_ERROR)
{
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(instance_p->config.base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
return FI2C_ERR_TRANS_STATE;
}
while (instance_p->status != STATUS_IDLE)
{
/* code */
@ -344,6 +365,7 @@ FError FI2cMasterReadIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, u8 *b
break;
}
}
instance_p->rxframe.data_buff = buf_p;
instance_p->rxframe.rx_total_num = buf_len;
instance_p->txframe.tx_total_num = buf_len;
@ -392,6 +414,11 @@ FError FI2cMasterWriteIntr(FI2c *instance_p, u32 mem_addr, u8 mem_byte_len, cons
FI2C_ERROR("i2c work mode shall be master.");
return FI2C_ERR_INVAL_STATE;
}
if (instance_p->status == STATUS_ERROR)
{
FI2C_ERROR("abort source: 0x%x,please see the FI2C_TX_ABRT_SOURCE_OFFSET register", FI2C_READ_REG32(instance_p->config.base_addr, FI2C_TX_ABRT_SOURCE_OFFSET));
return FI2C_ERR_TRANS_STATE;
}
while (instance_p->status != STATUS_IDLE)
{
/* code */

3
drivers/i2s/fes8336/fes8336.c

@ -242,7 +242,6 @@ void FEs8336Reset(void)
*/
void FEs8336RegsProbe(void)
{
u8 value = 0;
FEs8336Reset();
FEs8336InitRegs();
FEs8336WriteByte(ES8336_GPIO_SEL_REG4D, 0x02);
@ -272,7 +271,6 @@ void FEs8336RegsProbe(void)
void FEs8336Startup(void)
{
FError ret = FES8336_SUCCESS;
FEs8336WriteByte(ES8336_RESET_REG00, 0xC0);
FEs8336WriteByte(ES8336_SYS_PDN_REG0D, 0x00);
FEs8336WriteByte(ES8336_CLKMGR_CLKSW_REG01, 0x7f); //set the clock
@ -334,7 +332,6 @@ FError FEs8336ShutDown(void)
FError FEs8336MuteDown(u32 mute)
{
FError ret = FES8336_SUCCESS;
u8 value = 0;
if (mute)
{
FEs8336WriteByte(ES8336_DAC_SET1_REG30, 0x20);

2
drivers/i2s/fi2s/fi2s.c

@ -48,7 +48,6 @@ FError FI2sCfgInitialize(FI2s *instance, const FI2sConfig *config_p)
{
FASSERT(instance && config_p);
FError ret = FI2S_SUCCESS;
u32 reg;
if (FT_COMPONENT_IS_READY == instance->is_ready)
{
FI2S_ERROR("Device is already initialized!!!");
@ -217,7 +216,6 @@ void FI2sDeInitialize(FI2s *instance)
FError FI2sClkOutDiv(FI2s *instance)
{
FASSERT(instance != NULL);
FError ret = FI2S_SUCCESS;
u64 fix, point;
u32 reg, cfg;

2
drivers/i3c/fi3c/fi3c_master.c

@ -643,7 +643,7 @@ FError FI3cMasterDisableIBI(FI3c *instance_p, u32 dev_id)
FASSERT(instance_p);
FError ret = FI3C_SUCCESS;
uintptr base_addr = instance_p->config.base_addr;
u32 sir_map_reg = 0, sir_config = 0;
u32 sir_map_reg = 0;
FI3cMasterSendCCC(instance_p, FI3C_DISEC_DC_CCC_CMD, instance_p->dev[dev_id].dev_cfg.slave_addr, 0, 0, NULL, 0);
if (ret != FI3C_SUCCESS)

6
drivers/iomux/fioctrl/fioctrl.c

@ -280,7 +280,7 @@ FIOCtrlDelay FIOCtrlGetDelay(FIOCtrl *instance_p, const FIOCtrlPinIndex pin, FIO
u8 delay = 0;
uintptr base_addr = instance_p->config.base_address;
const u32 reg_val = FtIn32(base_addr + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
u32 delay_beg = 0;
if (FIOCTRL_OUTPUT_DELAY == dir)
{
@ -329,7 +329,7 @@ FError FIOCtrlSetDelay(FIOCtrl *instance_p, const FIOCtrlPinIndex pin, FIOCtrlDe
FIOCTRL_ASSERT_DELAY(delay);
uintptr base_addr = instance_p->config.base_address;
u32 reg_val = FtIn32(base_addr + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
u32 delay_beg = 0;
if (FIOCTRL_OUTPUT_DELAY == dir)
{
@ -378,7 +378,7 @@ FError FIOCtrlSetDelayEn(FIOCtrl *instance_p, const FIOCtrlPinIndex pin, FIOCtrl
FIOCTRL_ASSERT_DELAY_REG_OFF(pin);
uintptr base_addr = instance_p->config.base_address;
u32 reg_val = FtIn32(base_addr + pin.reg_off);
u32 delay_beg = 0, delay_end = 0;
u32 delay_beg = 0;
if (FIOCTRL_OUTPUT_DELAY == dir)
{

10
drivers/iomux/fiopad/fiopad_hw.h

@ -66,12 +66,12 @@ extern "C"
#define FIOPAD_REG1_IN_DELAY_ROUGH_GET(x) GET_REG32_BITS((x), 6, 4) /* 延时粗调 */
#define FIOPAD_REG1_IN_DELAY_ROUGH_SET(x) SET_REG32_BITS((x), 6, 4)
#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_REG0_END_OFFSET >= pin), "invalid reg0 offset @0x%x\r\n", (pin))
#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FIOPAD_NUM_OF_FUNC), "invalid func as %d\r\n", (func))
#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FIOPAD_NUM_OF_PULL), "invalid pull as %d\r\n", (pull))
#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FIOPAD_NUM_OF_DRIVE), "invalid pull as %d\r\n", (drive))
#define FIOPAD_ASSERT_REG0_OFF(pin) FASSERT_MSG((FIOPAD_REG0_END_OFFSET >= pin), "invalid reg0 offset @0x%x\r\n", (unsigned int)(pin))
#define FIOPAD_ASSERT_FUNC(func) FASSERT_MSG((func < FIOPAD_NUM_OF_FUNC), "invalid func as %d\r\n", (unsigned int)(func))
#define FIOPAD_ASSERT_PULL(pull) FASSERT_MSG((pull < FIOPAD_NUM_OF_PULL), "invalid pull as %d\r\n", (unsigned int)(pull))
#define FIOPAD_ASSERT_DRIVE(drive) FASSERT_MSG((drive < FIOPAD_NUM_OF_DRIVE), "invalid pull as %d\r\n", (unsigned int)(drive))
#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_REG1_BEG_OFFSET <= pin) && (FIOPAD_REG1_END_OFFSET >= pin)), "invalid reg1 offset @0x%x\r\n", (pin))
#define FIOPAD_ASSERT_REG1_OFF(pin) FASSERT_MSG(((FIOPAD_REG1_BEG_OFFSET <= pin) && (FIOPAD_REG1_END_OFFSET >= pin)), "invalid reg1 offset @0x%x\r\n", (unsigned int)(pin))
#define FIOPAD_ASSERT_DELAY(delay) FASSERT_MSG((delay < FIOPAD_NUM_OF_DELAY), "invalid delay as %d\r\n", (delay))
#define FIOPAD_DELAY_MAX 15

1
drivers/ipc/fsemaphore/fsemaphore_hw.h

@ -136,7 +136,6 @@ static inline boolean FSemaHwGetStatus(uintptr base_addr, u32 locker_idx)
*/
static inline boolean FSemaTryLockOnce(uintptr base_addr, u32 locker_idx)
{
boolean lock_success = FALSE;
u32 reg_val = FSemaReadReg(base_addr, FSEMA_RLOCK_X_REG_OFFSET(locker_idx)); /* 读寄存器,尝试上锁 */
/* 读返回 1:信号量之前已经被锁定,本次锁定失败

2
drivers/mio/fmio/fmio.c

@ -95,7 +95,6 @@ FError FMioFuncDeinit(FMioCtrl *instance_p)
uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type)
{
FASSERT(instance_p);
FError ret = FMIO_SUCCESS;
if (instance_p->is_ready != FT_COMPONENT_IS_READY)
{
@ -121,7 +120,6 @@ uintptr FMioFuncGetAddress(FMioCtrl *instance_p,u32 mio_type)
u32 FMioFuncGetIrqNum(FMioCtrl *instance_p,u32 mio_type)
{
FASSERT(instance_p);
FError ret = FMIO_SUCCESS;
if (instance_p->is_ready != FT_COMPONENT_IS_READY)
{

1
drivers/mmc/fsdmmc/fsdmmc.c

@ -333,7 +333,6 @@ static FError FSdmmcTransferDataPoll(uintptr base_addr, FSdmmcCmd *cmd_p)
{
FASSERT(cmd_p);
FError ret = FSDMMC_SUCCESS;
FSdmmcData *dat_p = cmd_p->data_p;
const boolean read = (FSDMMC_CMD_FLAG_READ_DATA == (cmd_p->flag & FSDMMC_CMD_FLAG_READ_DATA));
ret = FSdmmcSendData(base_addr, read, cmd_p);

2
drivers/nand/fnand/fnand_bbm.c

@ -260,7 +260,6 @@ static FError FNandWriteBbt(FNand *instance_p,
FNandBbtDesc *mirror_desc_p,
u32 chip_addr)
{
u64 offset;
u32 block = instance_p->nand_geometry[chip_addr].num_blocks - 1;
u8 buf[FNAND_MAX_BLOCKS >> FNAND_BBT_BLOCK_SHIFT];
u8 sparebuf[FNAND_MAX_SPARE_SIZE];
@ -528,7 +527,6 @@ FError FNandSearchBbt(FNand *instance_p, FNandBbtDesc *desc, u32 chip_addr)
*/
FError FNandReadBbt(FNand *instance_p, u32 chip_addr)
{
u64 offset;
u8 buf[FNAND_MAX_BLOCKS >> FNAND_BBT_BLOCK_SHIFT];
FError status1;
FError status2;

1
drivers/nand/fnand/fnand_common_cmd.c

@ -471,7 +471,6 @@ static FError FNandPageReadHwEcc(FNand *instance_p, u32 page_addr, u8 *buf, u32
u32 nand_state = 0;
u8 addr_buf[5] = {0};
u32 memcpy_length = 0;
volatile u32 wait_cnt;
/* read operation */
addr_buf[2] = page_addr;
addr_buf[3] = page_addr >> 8;

1
drivers/nand/fnand/fnand_id.c

@ -135,7 +135,6 @@ const FNandManuFacturer *FNandGetManuFacturer(u8 id)
static FError FNandIdDetect(FNand *instance_p, u32 chip_addr)
{
FError ret;
u32 i;
FNandId nand_id;
u8 *id_data = (u8 *)&nand_id.data;
u8 maf_id, dev_id;

2
drivers/nand/fnand/fnand_intr.c

@ -46,7 +46,6 @@
*/
void FNandIsrEnable(FNand *instance_p, u32 int_mask)
{
u32 reg_value;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FNandConfig *config_p;
@ -65,7 +64,6 @@ void FNandIsrEnable(FNand *instance_p, u32 int_mask)
*/
void FNandIrqDisable(FNand *instance_p, u32 int_mask)
{
u32 reg_value;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FNandConfig *config_p;

1
drivers/nand/fnand/fnand_option.c

@ -37,7 +37,6 @@
*/
FError FNandSetOption(FNand *instance_p, u32 options, u32 value)
{
u32 reg_value;
FNandConfig *config_p;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);

2
drivers/pwm/fpwm/fpwm.c

@ -223,7 +223,6 @@ static void FPwmPeriodSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_period)
{
FASSERT(pctrl != NULL);
u32 reg_val = 0;
u64 cycles = 0;
uintptr base_addr = pctrl->config.pwm_base_addr + FPWM_N(channel);
reg_val = FPWM_READ_REG32(base_addr, FPWM_PERIOD_OFFSET);
@ -280,7 +279,6 @@ FError FPwmPulseSet(FPwmCtrl *pctrl, u32 channel, u16 pwm_ccr)
FASSERT(pctrl != NULL);
FASSERT(channel < FPWM_CHANNEL_NUM);
u32 reg_val = 0;
u64 cycles = 0;
u32 state = 0;
u16 pwm_period_ccr = 0;

1
drivers/pwm/fpwm/fpwm_intr.c

@ -65,7 +65,6 @@ void FPwmRegisterInterruptHandler(FPwmCtrl *instance_p, FPwmIntrEventType event_
void FPwmIntrHandler(s32 vector, void *args)
{
u32 status;
static int i = 0;
FPwmCtrl *pctrl = (FPwmCtrl *)args;
FASSERT(pctrl != NULL);

11
drivers/qspi/fqspi/fqspi_flash.c

@ -260,7 +260,6 @@ FError FQspiFlashReadReg(FQspiCtrl *pctrl, u32 offset, u8 *buf, size_t len)
{
FASSERT(pctrl && buf);
FError ret = FQSPI_SUCCESS;
u32 cmd_reg = 0;
uintptr base_addr = pctrl->config.base_addr;
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
@ -327,7 +326,7 @@ size_t FQspiFlashReadData(FQspiCtrl *pctrl, u32 chip_addr, u8 *buf, size_t len)
const size_t remain = len % FQSPI_ALIGNED_BYTE; /* remain number of 1-byte not aligned */
u8 align_buf[FQSPI_ALIGNED_BYTE];
size_t copy_len = 0;
u32 addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
uintptr addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
intptr src_addr = (intptr)addr; /* conver to 32/64 bit addr */
intptr dst_addr = (intptr)buf;
@ -592,7 +591,7 @@ FError FQspiFlashWriteData(FQspiCtrl *pctrl, u8 command, u32 chip_addr, const u8
u32 aligned_bit = 0;
u8 tmp[FQSPI_ALIGNED_BYTE] = {0xff, 0xff, 0xff, 0xff};
u32 addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
uintptr addr = pctrl->config.mem_start + pctrl->config.channel * pctrl->flash_size + chip_addr;
uintptr base_addr = pctrl->config.base_addr;
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
@ -723,7 +722,7 @@ FError FQspiFlashPortReadData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf,
}
FError ret = FQSPI_SUCCESS;
u32 addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
uintptr addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
uintptr base_addr = pctrl->config.base_addr;
FQspiXIPModeSet(base_addr, FQSPI_XIP_EXIT);
@ -786,7 +785,7 @@ FError FQspiFlashPortWriteData(FQspiCtrl *pctrl, u8 cmd, u32 chip_addr, u8 *buf,
}
FError ret = FQSPI_SUCCESS;
u32 addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
uintptr addr = chip_addr + pctrl->config.channel * pctrl->flash_size;
uintptr base_addr = pctrl->config.base_addr;
/* Flash write enable */
@ -936,7 +935,6 @@ FError FQspiFlashEnableWrite(FQspiCtrl *pctrl)
{
FASSERT(pctrl);
FError ret = FQSPI_SUCCESS;
u32 timeout = FQSPI_BUSY_TIMEOUT_US;
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{
@ -1016,7 +1014,6 @@ FError FQspiFlashWriteReg(FQspiCtrl *pctrl, u8 command, const u8 *buf, size_t le
{
FASSERT(pctrl);
FError ret = FQSPI_SUCCESS;
u8 sr1_v = 0;
if (FT_COMPONENT_IS_READY != pctrl->is_ready)
{

1
drivers/qspi/fqspi/fqspi_hw.c

@ -46,7 +46,6 @@ void FQspiGetPortData(uintptr base_addr, u8 *buf, size_t len)
{
FASSERT(buf);
FASSERT((len <= FQSPI_CMD_PORT_CMD_RW_MAX) && (len));
u32 loop = 0;
u32 bouncebuf[2] = { 0 };
/* Dummy write to LD_PORT register and issue READ ops */

8
drivers/sata/fsata/fsata.c

@ -142,7 +142,6 @@ static FError FSataAhciInquiry(FSataCtrl *instance_p, u8 port)
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FError ret = FSATA_SUCCESS;
u16 *idbuf;
/* 64位需要预留给内存池更大的空间 */
static u16 tmpid[FSATA_ID_WORDS] __attribute__((aligned(128))) = {0};
@ -346,9 +345,6 @@ static FError FSataAhciReadCapacity(FSataCtrl *instance_p, u8 port,
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FError ret = FSATA_SUCCESS;
u32 transfer_size; /* number of bytes per iteration */
if (!instance_p->ataid[port])
{
@ -390,7 +386,6 @@ FError FSataAhciReadInfo(FSataCtrl *instance_p, u8 port)
{
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
uintptr base_addr = instance_p->config.base_addr;
FError ret = FSATA_SUCCESS;
u16 *idbuf;
@ -629,7 +624,6 @@ FError FSataAhciPortStart(FSataCtrl *instance_p, u8 port, uintptr mem)
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FASSERT(mem);
uintptr base_addr = instance_p->config.base_addr;
FError ret = FSATA_SUCCESS;
FSataAhciPorts *port_info = &(instance_p->port[port]);
@ -774,7 +768,6 @@ static FError FSataAhciDataIO(FSataCtrl *instance_p, u8 port, u8 *fis,
FSataAhciPorts *port_info = &(instance_p->port[port]);
uintptr base_addr = instance_p->config.base_addr;
uintptr port_base_addr = instance_p->port[port].port_base_addr;
if (port >= instance_p->n_ports)
@ -846,7 +839,6 @@ FError FSataReadWrite(FSataCtrl *instance_p, u8 port, u32 start,
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FASSERT(blk_cnt);
uintptr base_addr = instance_p->config.base_addr;
FError ret = FSATA_SUCCESS;
u16 now_blocks; /* number of blocks per iteration */

3
drivers/sata/fsata/fsata_intr.c

@ -53,7 +53,6 @@
*/
void FSataIrqEnable(FSataCtrl *instance_p, u32 int_mask)
{
u32 reg_value;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
u32 port = instance_p->private_data;
@ -79,7 +78,6 @@ void FSataIrqEnable(FSataCtrl *instance_p, u32 int_mask)
*/
void FSataIrqDisable(FSataCtrl *instance_p, u32 int_mask)
{
u32 reg_value;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
u32 port = instance_p->private_data;
@ -151,7 +149,6 @@ FError FSataSetHandler(FSataCtrl *instance_p, u32 irq_type, void *func_pointer,
void FSataIrqHandler(s32 vector, void *param)
{
FSataCtrl *instance_p = (FSataCtrl *)param;
FSataConfig *config_p;
FASSERT(instance_p != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);

3
drivers/scmi/fscmi_mhu/fscmi_base.c

@ -160,7 +160,6 @@ static FError FScmiBaseGetImplementVersion(FScmi *instance_p, u32 *impl_ver)
{
FError ret;
struct FScmiTransferInfo *info;
struct FScmiBaseAttributes *attr_info;
info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
if (info == NULL)
@ -195,7 +194,6 @@ static FError FScmiBaseGetImplementList(FScmi *instance_p , u8 *protocols_imp)
{
FError ret;
struct FScmiTransferInfo *info;
struct FScmiBaseAttributes *attr_info;
u32 *num_skip, *num_ret;
u8 *list;
@ -255,7 +253,6 @@ static FError FScmiBaseGetAgent(FScmi *instance_p,int id,char *name)
{
FError ret;
struct FScmiTransferInfo *info;
struct FScmiBaseAttributes *attr_info;
info = FScmiGetInfo(instance_p, SCMI_PROTOCOL_BASE);
if (info == NULL)

3
drivers/scmi/fscmi_mhu/fscmi_perf.c

@ -291,7 +291,6 @@ static FError FScmiPerfLimitsGet(FScmi *instance_p, u32 domain, u32 *max_perf, u
FASSERT(domain < instance_p->perf.num_domains);
FError ret;
s32 status;
struct FScmiTransferInfo *info;
struct FScmiPerfGetLimits *limits;
@ -319,7 +318,7 @@ static FError FScmiPerfLimitsGet(FScmi *instance_p, u32 domain, u32 *max_perf, u
return ret;
}
limits = (struct FScmiPerfGetLimits *)info->rx.buf;
//status = limits->status;
*max_perf = limits->max_level;
*min_perf = limits->min_level;
FSCMI_PERF_INFO("FScmiPerfLimitsGet domain:%d, max_level:%d KHz, min_level:%d KHz.",domain,*max_perf,*min_perf);

5
drivers/scmi/fscmi_mhu/fscmi_sensors.c

@ -301,8 +301,6 @@ FError FScmiSensorGetTemp(FScmi *instance_p, u32 sensor_id,s64 *temp)
FASSERT(temp != NULL);
FASSERT(instance_p->is_ready == FT_COMPONENT_IS_READY);
FError ret;
if(instance_p->sensors.num_sensors > 0 && instance_p->sensors.num_sensors > sensor_id)
{
if (instance_p->sensors.sensor_info[sensor_id].type == DEGRESS_C)
@ -327,9 +325,10 @@ FError FScmiSensorGetTemp(FScmi *instance_p, u32 sensor_id,s64 *temp)
FError FScmiSensorInit(FScmi *instance_p)
{
u32 version;
FError ret;
struct FScmiSensorsInfo *sinfo;
sinfo = &instance_p->sensors;
FError ret;
ret = FScmiSensorGetVersion(instance_p,&instance_p->sensors.version);
if(ret != FT_SUCCESS)

2
drivers/serial/fpl011/fpl011_options.c

@ -409,7 +409,7 @@ void FPl011ProgramCtlReg(FPl011 *uart_p, u32 ctrl_reg)
u32 line_ctrl_reg;
u32 temp_ctrl_reg;
u32 isbusy;
u32 addr = uart_p->config.base_address;
uintptr addr = uart_p->config.base_address;
FASSERT(uart_p);
/*

1
drivers/timer/ftimer_tacho/ftimer.c

@ -311,7 +311,6 @@ FError FTimerInit(FTimerTachoCtrl *instance_p, const FTimerTachoConfig *config_p
FASSERT(instance_p && config_p);
u32 reg_val = 0;
u32 Ret = FTIMER_TACHO_SUCCESS;
if ((FTIMER_ONCE_CMP == config_p->cmp_type) &&
(FTIMER_FREE_RUN != config_p->timer_mode))

2
example/media/lvgl_demo_test/src/cmd_lvgl.c

@ -48,7 +48,7 @@ static void FMediaCmdUsage(void)
static FError FMediaCmdEntry(int argc, char *argv[])
{
FError ret ;
FError ret = FT_SUCCESS ;
if (argc < 2)
{
FMediaCmdUsage();

8
example/media/lvgl_demo_test/src/lvgl_disp_test.c

@ -62,7 +62,6 @@ void lv_hpd_detect(void)
FDcDp *instance_p = &dcdp_config;
u32 ret;
u32 index;
u32 mode_id;
for (index = 0; index < FDCDP_INSTANCE_NUM; index++)
{
@ -147,7 +146,7 @@ static void FMediaAuxErrorCallback(void *args, u32 index)
* @param {u32} index is the channel
* @return Null
*/
static void FMediaAuxRecievedCallback(void *args, u32 index)
_UNUSED static void FMediaAuxRecievedCallback(void *args, u32 index)
{
FASSERT(args != NULL);
FDcDp *instance_p = (FDcDp *)args;
@ -162,7 +161,7 @@ static void FMediaAuxRecievedCallback(void *args, u32 index)
*/
FError FMediaCtrlProbe(void)
{
FError ret;
FError ret = FT_SUCCESS;
u32 index;
FDcDpCfgInitialize(&dcdp_config);
for (index = 0; index < FDCDP_INSTANCE_NUM; index ++)
@ -184,7 +183,6 @@ static void FMediaIrqSet(FDcDp *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
FMediaIntrConfig intr_config;
memset(&intr_config, 0, sizeof(intr_config));
GetCpuId(&cpu_id);
@ -212,7 +210,7 @@ static void FDcDpIrqAllEnable(FDcDp *instance_p)
FDcDpIntrEventType event_type = FDCDP_HPD_IRQ_CONNECTED;
for (index = 0; index < FDCDP_INSTANCE_NUM; index++)
{
for (event_type = 0; event_type < FDCDP_INSTANCE_NUM; event_type++)
for (event_type = 0; event_type < FDCDP_INTR_MAX_NUM; event_type++)
{
FDcDpIrqEnable(instance_p, index, event_type);
}

9
example/media/media_test/src/media_test_example.c

@ -60,8 +60,8 @@ void FMediaHpdDetect(void)
{
FDcDp *instance_p = &dcdp_config;
u32 ret;
u32 index;
u32 mode_id;
u32 index;
for (index = 0; index < FDCDP_INSTANCE_NUM; index++)
{
@ -79,7 +79,7 @@ void FMediaHpdDetect(void)
}
/**
* @name: BltVideoToFill
* @name: PhyFramebufferWrite
* @msg: write the rgb to the dc
* @param {FDcCtrl} *instance_p is the struct of dc
* @param {uintptr} offset is the addr
@ -115,8 +115,6 @@ static void BltVideoToFill(FDcCtrl *instance_p, GraphicsTest *config, u32 width,
FASSERT(instance_p != NULL);
FASSERT(config != NULL);
u32 ResWidth;
u32 ResHeight;
u32 Stride;
u32 I;
u32 J;
@ -218,7 +216,6 @@ static void FMediaIrqSet(FDcDp *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
FMediaIntrConfig intr_config;
memset(&intr_config, 0, sizeof(intr_config));
@ -247,7 +244,7 @@ static void FDcDpIrqAllEnable(FDcDp *instance_p)
FDcDpIntrEventType event_type = FDCDP_HPD_IRQ_CONNECTED;
for (index = 0; index < FDCDP_INSTANCE_NUM; index++)
{
for (event_type = 0; event_type < FDCDP_INSTANCE_NUM; event_type++)
for (event_type = 0; event_type < FDCDP_INTR_MAX_NUM; event_type++)
{
FDcDpIrqEnable(instance_p, index, event_type);
}

1
example/peripherals/can/can/src/can_box_example.c

@ -117,7 +117,6 @@ u32 FCanBoxTestExample(u32 can_id, u32 arb_baud, u32 data_baud, boolean ide, u32
FASSERT(data_baud >= FCAN_BAUDRATE_50K);
FASSERT(data_baud <= FCAN_BAUDRATE_5000K);
FError ret = FCAN_SUCCESS;
FCanCtrl *instance_p;
int i = 0;
printf("Use can2.0 protocol!\n");

2
example/peripherals/can/canfd/inc/canfd_id_filter_example.h

@ -43,7 +43,7 @@ extern "C"
/************************** Function Prototypes ******************************/
/* entry function for canfd id filter example */
int FCanfdIdFilterExample();
int FCanfdIdFilterExample(void);
#ifdef __cplusplus
}

2
example/peripherals/can/canfd/inc/canfd_intr_loopback_mode_example.h

@ -43,7 +43,7 @@ extern "C"
/************************** Function Prototypes ******************************/
/* function for canfd interrupt loopback mode example */
int FCanfdIntrLoopbackExample();
int FCanfdIntrLoopbackExample(void);
#ifdef __cplusplus
}

2
example/peripherals/can/canfd/inc/canfd_polled_loopback_mode_example.h

@ -43,7 +43,7 @@ extern "C"
/************************** Function Prototypes ******************************/
/*function for canfd polled loopback mode example */
int FCanfdPolledLoopbackExample();
int FCanfdPolledLoopbackExample(void);
#ifdef __cplusplus
}

2
example/peripherals/can/canfd/main.c

@ -48,7 +48,7 @@
/************************** Function *****************************************/
int main()
int main(void)
{
#ifdef CONFIG_USE_LETTER_SHELL
/* if shell command is enabled, register example entry as shell command */

5
example/peripherals/can/canfd/src/canfd_box_example.c

@ -117,7 +117,6 @@ u32 FCanfdBoxTestExample(u32 can_id, u32 arb_baud, u32 data_baud, boolean ide, u
FASSERT(data_baud >= FCAN_BAUDRATE_50K);
FASSERT(data_baud <= FCAN_BAUDRATE_5000K);
FError ret = FCAN_SUCCESS;
FCanCtrl *instance_p;
int i = 0;
printf("Use canfd protocol!\n");
@ -171,7 +170,7 @@ u32 FCanfdBoxTestExample(u32 can_id, u32 arb_baud, u32 data_baud, boolean ide, u
FCanIdMaskConfig id_mask;
FCanEnable(&can[can_id], FALSE);
memset(&id_mask, 0, sizeof(id_mask));
for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
for (i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
{
id_mask.filter_index = i;
id_mask.id = 0;
@ -241,7 +240,7 @@ exit:
}
else
{
printf("%s@%d: canfd box example [failure], status = %d \r\n", __func__, __LINE__, ret);
printf("%s@%d: canfd box example [failure], status = %ld \r\n", __func__, __LINE__, ret);
}
return ret;

2
example/peripherals/can/canfd/src/canfd_id_filter_example.c

@ -124,7 +124,7 @@ int FCanfdIdFilterExample()
FCanIdMaskConfig id_mask;
FCanEnable(&can[can_id], FALSE);
memset(&id_mask, 0, sizeof(id_mask));
for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
for (i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
{
id_mask.filter_index = i;
/* 只接收发送id=0x02的帧 */

2
example/peripherals/can/canfd/src/canfd_intr_loopback_mode_example.c

@ -320,7 +320,7 @@ int FCanfdIntrLoopbackExample()
FCanIdMaskConfig id_mask;
FCanEnable(&can[can_id], FALSE);
memset(&id_mask, 0, sizeof(id_mask));
for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
for (i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
{
id_mask.filter_index = i;
id_mask.id = 0;

2
example/peripherals/can/canfd/src/canfd_polled_loopback_mode_example.c

@ -120,7 +120,7 @@ int FCanfdPolledLoopbackExample()
FCanIdMaskConfig id_mask;
FCanEnable(&can[can_id], FALSE);
memset(&id_mask, 0, sizeof(id_mask));
for (int i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
for (i = 0; i < FCAN_ACC_ID_REG_NUM; i++)
{
id_mask.filter_index = i;
id_mask.id = 0;

1
example/peripherals/generic_timer/src/cmd_timer.c

@ -51,7 +51,6 @@ static void FGenericCmdUsage(void)
static int FGenericCmdEntry(int argc, char *argv[])
{
u32 times = 0;
if (argc < 3)
{
FGenericCmdUsage();

2
example/peripherals/generic_timer/src/physical_counter.c

@ -51,7 +51,7 @@ static unsigned long FEmulDivision(u64 val, u64 div)
return cnt;
}
static u64 FTicksToNs(u64 ticks)
_UNUSED static u64 FTicksToNs(u64 ticks)
{
return FEmulDivision(ticks * 1000,
GenericTimerFrequecy() / 1000 / 1000);

2
example/peripherals/generic_timer/src/virtual_counter.c

@ -51,7 +51,7 @@ static unsigned long FEmulDivision(u64 val, u64 div)
return cnt;
}
static u64 FTicksToNs(u64 ticks)
_UNUSED static u64 FTicksToNs(u64 ticks)
{
return FEmulDivision(ticks * 1000,
GenericTimerFrequecy() / 1000 / 1000);

2
example/peripherals/i2c/README.md

@ -134,6 +134,7 @@ bootelf -p 0x90100000
| --------------- | --------------------------- |
| i2c rtc_example | E2000Q ,E2000D |
| i2c ms_example | phytiumpi(firefly) ,PD2308 |
| i2c ms_ddma_example | phytiumpi(firefly) ,PD2308 |
注:请仔细查看例程中所定义的板卡型号,命令与板卡请确认适配。例如:在firefly板卡中无rtc,则使用i2c rtc_example时,可能出现卡死或运行不正确的现象。
@ -153,6 +154,7 @@ i2c ms_example
![一键运行](./fig/ms_example.png "ms_example.png")
## 3. 如何解决问题
> `<font size="1">`主要记录使用例程中可能会遇到的问题,给出相应的解决方案 `</font><br />`

16
example/peripherals/i2c/configs/pd2308_aarch64_demo_i2c.config

@ -91,9 +91,9 @@ CONFIG_TARGET_NAME="i2c"
CONFIG_ELOG_LINE_BUF_SIZE=0x100
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
CONFIG_LOG_INFO=y
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set
@ -159,7 +159,17 @@ CONFIG_USE_MIO=y
# Third-party configuration
#
# CONFIG_USE_LWIP is not set
# CONFIG_USE_LETTER_SHELL is not set
CONFIG_USE_LETTER_SHELL=y
#
# Letter shell configuration
#
CONFIG_LS_PL011_UART=y
CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y
# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set
# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set
# end of Letter shell configuration
# CONFIG_USE_AMP is not set
# CONFIG_USE_YMODEM is not set
# CONFIG_USE_SFUD is not set

4
example/peripherals/i2c/configs/phytiumpi_aarch32_firefly_i2c.config

@ -99,9 +99,9 @@ CONFIG_TARGET_NAME="i2c"
CONFIG_ELOG_LINE_BUF_SIZE=0x100
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
CONFIG_LOG_INFO=y
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set

6
example/peripherals/i2c/configs/phytiumpi_aarch64_firefly_i2c.config

@ -67,7 +67,7 @@ CONFIG_BOARD_NAME="firefly"
# CONFIG_USE_CAN_IOPAD is not set
# CONFIG_USE_QSPI_IOPAD is not set
# CONFIG_USE_PWM_IOPAD is not set
CONFIG_USE_MIO_IOPAD=y
# CONFIG_USE_MIO_IOPAD is not set
# CONFIG_USE_TACHO_IOPAD is not set
CONFIG_USE_UART_IOPAD=y
# CONFIG_USE_THIRD_PARTY_IOPAD is not set
@ -93,9 +93,9 @@ CONFIG_TARGET_NAME="i2c"
CONFIG_ELOG_LINE_BUF_SIZE=0x100
# CONFIG_LOG_VERBOS is not set
# CONFIG_LOG_DEBUG is not set
# CONFIG_LOG_INFO is not set
CONFIG_LOG_INFO=y
# CONFIG_LOG_WARN is not set
CONFIG_LOG_ERROR=y
# CONFIG_LOG_ERROR is not set
# CONFIG_LOG_NONE is not set
# CONFIG_LOG_EXTRA_INFO is not set
# CONFIG_LOG_DISPALY_CORE_NUM is not set

2
example/peripherals/i2c/sdkconfig

@ -67,7 +67,7 @@ CONFIG_BOARD_NAME="firefly"
# CONFIG_USE_CAN_IOPAD is not set
# CONFIG_USE_QSPI_IOPAD is not set
# CONFIG_USE_PWM_IOPAD is not set
CONFIG_USE_MIO_IOPAD=y
# CONFIG_USE_MIO_IOPAD is not set
# CONFIG_USE_TACHO_IOPAD is not set
CONFIG_USE_UART_IOPAD=y
# CONFIG_USE_THIRD_PARTY_IOPAD is not set

2
example/peripherals/i2c/sdkconfig.h

@ -64,7 +64,7 @@
/* CONFIG_USE_CAN_IOPAD is not set */
/* CONFIG_USE_QSPI_IOPAD is not set */
/* CONFIG_USE_PWM_IOPAD is not set */
#define CONFIG_USE_MIO_IOPAD
/* CONFIG_USE_MIO_IOPAD is not set */
/* CONFIG_USE_TACHO_IOPAD is not set */
#define CONFIG_USE_UART_IOPAD
/* CONFIG_USE_THIRD_PARTY_IOPAD is not set */

28
example/peripherals/i2c/src/cmd_i2c.c

@ -36,10 +36,15 @@
#include "i2c_ds1339_rtc_example.h"
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD) || defined(CONFIG_PD2308_DEMO_BOARD)
#if defined(CONFIG_PD2308_DEMO_BOARD)
#include "i2c_master_slave_example.h"
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD)
#include "i2c_master_slave_example.h"
#endif
/* usage info function for i2c example */
static void FI2cExampleUsage(void)
{
@ -48,7 +53,11 @@ static void FI2cExampleUsage(void)
printf("i2c rtc_example\r\n");
printf("-- use rtc example.\r\n");
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD) || defined(CONFIG_PD2308_DEMO_BOARD)
#if defined(CONFIG_PD2308_DEMO_BOARD)
printf("i2c ms_example\r\n");
printf("-- use master and slave communicate example.\r\n");
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD)
printf("i2c ms_example\r\n");
printf("-- use master and slave communicate example.\r\n");
#endif
@ -78,7 +87,7 @@ static int FI2cCmdEntry(int argc, char *argv[])
}
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD) || defined(CONFIG_PD2308_DEMO_BOARD)
#if defined(CONFIG_PD2308_DEMO_BOARD)
else if (!strcmp(argv[1], "ms_example"))
{
ret = FI2cMasterSlaveExample();
@ -88,6 +97,19 @@ static int FI2cCmdEntry(int argc, char *argv[])
return ret;
}
}
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD)
else if (!strcmp(argv[1], "ms_example"))
{
ret = FI2cMasterSlaveExample();
if (ret != FT_SUCCESS)
{
printf("FI2cMasterSlaveExample error :0x%x!\n",ret);
return ret;
}
}
#endif
return ret;
}

5
example/peripherals/i2c/src/i2c_ds1339_rtc_example.c

@ -208,7 +208,7 @@ FError FDs1339RtcSet(FRtcDateTimer *rtc_time)
data_buf[6] = BIN_TO_BCD(rtc_time->year % 100);
/*FI2cMasterWriteIntr*/
/*FI2cMasterWritePoll*/
ret = FI2cMasterWritePoll(instance_p, 0, 1, data_buf, sizeof(data_buf));
if (ret != FDSRTC_SUCCESS)
{
@ -239,10 +239,9 @@ FError FDs1339RtcGet(FRtcDateTimer *rtc_time)
data_buf[5] u8 monCent;
data_buf[6] u8 year;
*/
u8 century;
u8 data_buf[7] = {0};
/*FI2cMasterWriteIntr*/
/*FI2cMasterReadPoll*/
ret = FI2cMasterReadPoll(instance_p, 0, 1, data_buf, sizeof(data_buf));
if (ret != FDSRTC_SUCCESS)
{

67
example/peripherals/i2c/src/i2c_master_slave_example.c

@ -45,20 +45,20 @@
#endif
#if defined(CONFIG_FIREFLY_DEMO_BOARD)
#include "fmio_hw.h"
#include "fmio.h"
#define I2C_USE_MIO
static FMioConfig master_mio_config;
static FMioCtrl master_mio_ctrl;
static FMioConfig slave_mio_config;
static FMioCtrl slave_mio_ctrl;
#define MASTER_MIO FMIO1_ID
#define SLAVE_MIO FMIO2_ID
#include "fmio_hw.h"
#include "fmio.h"
#define I2C_USE_MIO
static FMioConfig master_mio_config;
static FMioCtrl master_mio_ctrl;
static FMioConfig slave_mio_config;
static FMioCtrl slave_mio_ctrl;
#define MASTER_MIO FMIO1_ID
#define SLAVE_MIO FMIO2_ID
#elif defined(CONFIG_PD2308_DEMO_BOARD)
#define I2C_USE_CONTROLLER
#define MASTER_I2C_ID FI2C0_ID
#define SLAVE_I2C_ID FI2C1_ID
#define I2C_USE_CONTROLLER
#define MASTER_I2C_ID FI2C0_ID
#define SLAVE_I2C_ID FI2C1_ID
#endif
@ -121,6 +121,8 @@ void FI2cSlaveCb(void *instance_p, void *para, u32 evt)
case FI2C_EVT_SLAVE_WRITE_REQUESTED:
slave_p->first_write = TRUE;
break;
case FI2C_EVT_SLAVE_ABORT:
break;
default:
break;
}
@ -153,6 +155,11 @@ void FI2cSlaveWriteRequest(void *instance_p, void *para)
FI2cSlaveCb(instance_p, para, FI2C_EVT_SLAVE_WRITE_REQUESTED);
}
void FI2cSlaveAbort(void *instance_p, void *para)
{
FI2cSlaveCb(instance_p, para, FI2C_EVT_SLAVE_ABORT);
}
#if defined(I2C_USE_MIO)
FError FI2cMioSlaveInit(u32 address, u32 speed_rate)
{
@ -206,7 +213,7 @@ FError FI2cMioSlaveInit(u32 address, u32 speed_rate)
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_READ_REQUESTED, FI2cSlaveReadRequest);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_STOP, FI2cSlaveStop);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_WRITE_REQUESTED, FI2cSlaveWriteRequest);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_ABORT, FI2cSlaveAbort);
u32 cpu_id;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(input_cfg.irq_num, cpu_id);
@ -325,7 +332,7 @@ FError FI2cSlaveInit(u32 address, u32 speed_rate)
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_READ_REQUESTED, FI2cSlaveReadRequest);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_STOP, FI2cSlaveStop);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_WRITE_REQUESTED, FI2cSlaveWriteRequest);
FI2cSlaveRegisterIntrHandler(instance_p, FI2C_EVT_SLAVE_ABORT, FI2cSlaveAbort);
u32 cpu_id;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(input_cfg.irq_num, cpu_id);
@ -453,6 +460,8 @@ FError FI2cSlaveDeinit(void)
#endif
FI2c *instance_p = &slave.device;
FI2cClearAbort(instance_p->config.base_addr);/* 清除错误状态 */
InterruptMask(instance_p->config.irq_num);
FI2cDeInitialize(instance_p);
@ -472,7 +481,8 @@ FError FI2cMasterDeinit(void)
return ret;
}
#endif
/* disable all i2c irq */
FI2cClearAbort(master_i2c_instance.config.base_addr);/* 清除错误状态 */
FI2c *instance_p = &master_i2c_instance;
FI2cDeInitialize(instance_p);
@ -499,14 +509,14 @@ FError FI2cMasterSlaveExample(void)
ret = FI2cMioSlaveInit(address, speed_rate);
if (ret != FT_SUCCESS)
{
FI2CMS_ERROR("FI2cMioSlaveInit mio_id :%d is error!\n",SLAVE_MIO);
FI2CMS_ERROR("FI2cMioSlaveInit mio_id :%d is error!\n", SLAVE_MIO);
goto err;
}
ret = FI2cMioMasterInit(address, speed_rate);
if (FT_SUCCESS != ret)
{
FI2CMS_ERROR("FI2cMioMasterInit mio_id :%d is error!\n",MASTER_MIO);
FI2CMS_ERROR("FI2cMioMasterInit mio_id :%d is error!\n", MASTER_MIO);
goto err;
}
#endif
@ -515,14 +525,14 @@ FError FI2cMasterSlaveExample(void)
ret = FI2cSlaveInit(address, speed_rate);
if (ret != FT_SUCCESS)
{
FI2CMS_ERROR("FI2cSlaveInit I2c_id :%d is error!\n",SLAVE_I2C_ID);
FI2CMS_ERROR("FI2cSlaveInit I2c_id :%d is error!\n", SLAVE_I2C_ID);
goto err;
}
ret = FI2cMasterInit(address, speed_rate);
if (FT_SUCCESS != ret)
{
FI2CMS_ERROR("FI2cMasterInit I2c_id :%d is error!\n",MASTER_I2C_ID);
FI2CMS_ERROR("FI2cMasterInit I2c_id :%d is error!\n", MASTER_I2C_ID);
goto err;
}
#endif
@ -544,19 +554,24 @@ FError FI2cMasterSlaveExample(void)
ret = FI2cMasterRead(read_buf, input_len, offset);
if (FI2C_SUCCESS == ret)
{
printf("\r\nRead 0x%x len %d:%s.\r\n", offset, input_len,read_buf);
printf("\r\nRead 0x%x len %d:%s.\r\n", offset, input_len, read_buf);
FtDumpHexByte(read_buf, input_len);
}
/* print message on example run result */
err:
ret = FI2cMasterDeinit();
if (FI2C_SUCCESS != ret)
if (ret != FT_SUCCESS)
{
FI2CMS_ERROR("FI2cMasterDeinit error!\n");
goto err;
FI2CMS_ERROR("FI2cDdmaMasterDeinit error!\n");
}
/* print message on example run result */
err:
ret = FI2cSlaveDeinit();
if (ret != FT_SUCCESS)
{
FI2CMS_ERROR("FI2cSlaveDeinit error!\n");
}
FIOMuxDeInit();
if (0 == ret)
{
printf("%s@%d: I2C master-slave example [success]\r\n", __func__, __LINE__);

1
example/peripherals/i2s/i2s_board/src/i2s_rx_example.c

@ -82,7 +82,6 @@ static void FI2sIrqSet(FI2s *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);

1
example/peripherals/i2s/i2s_board/src/i2s_tx_example.c

@ -81,7 +81,6 @@ static void FI2sIrqSet(FI2s *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);

1
example/peripherals/i2s/i2s_dp/src/i2s_dp_rx_example.c

@ -80,7 +80,6 @@ static void FI2sIrqSet(FI2s *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);

1
example/peripherals/i2s/i2s_dp/src/i2s_dp_tx_example.c

@ -80,7 +80,6 @@ static void FI2sIrqSet(FI2s *instance_p)
FASSERT(instance_p != NULL);
u32 cpu_id;
u32 index;
GetCpuId(&cpu_id);
InterruptSetTargetCpus(instance_p->config.irq_num, cpu_id);

1
example/peripherals/i3c/src/i3c_at24c04_eeprom_example.c

@ -48,7 +48,6 @@ static FI3c master_device;
static void FI3cCmddEmpCallback(void *args)
{
FI3c *instance_p = (FI3c *)args;
printf("I3C AT24C04 eeprom example.I3C cmd descriptor queun empty intr callback.\n");
}

2
example/peripherals/i3c/src/i3c_ds1339_rtc_example.c

@ -47,7 +47,6 @@ static FI3c master_device;
static void FI3cCmddEmpCallback(void *args)
{
FI3c *instance_p = (FI3c *)args;
printf("I3C DS1339 rtc example.I3C cmd descriptor queun empty intr callback.\n");
}
@ -201,7 +200,6 @@ FError FDs1339RtcGet(FRtcDateTimer *rtc_time)
data_buf[5] u8 monCent;
data_buf[6] u8 year;
*/
u8 century;
u8 data_buf[7] = {0};
/*FI2cMasterWriteIntr*/

2
example/peripherals/iopad/src/iopad_set_config_example.c

@ -94,8 +94,6 @@ static void FPinRecoverIoPadSetting(u32 pin_reg_off)
/* function of iopad set config example */
int FIopadModifySettingExample(void)
{
uintptr iopad_off;
FIOPadCfgInitialize(&iopad_ctrl, FIOPadLookupConfig(FIOPAD0_ID));
printf("[uart-1 rx pin] \r\n");
FPinGetIoPadSetting(FIOPAD_AW47_REG0_OFFSET);

5
example/peripherals/pin/README.md

@ -152,10 +152,9 @@ pin gpio_intr_example
![two_input_gpio](./figs/two_input_gpio.png)
- 如果是飞腾派,可以按照下图联想,分别将 GPIO 4-13 GPIO 4-12 和 GPIO 0-0 接地
![alt text](./figs/firefly_two_gpio.png)
- 如果是飞腾派,可以按照下图连线,分别将 GPIO 4-13 GPIO 4-12 和 GPIO 0-0 接地
![firefly_three_gpio](figs/firefly_three_gpio.png)
- 如果是 D2000 测试板,可以按照下面连线,用 SPI 插槽的引脚复用成 GPIO 进行测试,使用左侧排线的最下面脚(SPI0-SO 对应 GPIO 1-A-7)和右侧排线的最上面脚(SPI0-SCK 对应 GPIO 1-A-6),都连接板子上的一个 GND 脚

0
example/peripherals/pin/figs/firefly_two_gpio.png → example/peripherals/pin/figs/firefly_three_gpio.png

Before

Width:  |  Height:  |  Size: 3.9 MiB

After

Width:  |  Height:  |  Size: 3.9 MiB

2
example/peripherals/pin/src/pin_gpio_low_level_example.c

@ -91,10 +91,8 @@ static u32 output_pin = (u32)FGPIO_PIN_7;
/* function of gpio low level example */
int FPinGpioLowLevelExample(void)
{
int ret = 0;
int flag = 1;
u32 reg_val;
u32 set_level = FGPIO_PIN_HIGH;
/* init pin */
FIOMuxInit();

4
example/peripherals/pin/src/pin_gpio_pwm_example.c

@ -75,8 +75,6 @@ static FGpio output_pin_instance_2;
static FSoftPwm pwm_output_1;
static FSoftPwm pwm_output_2;
/* pwm related parameters */
static u32 tick_delay = SYS_TICK_DELAY;
static u32 tick_level = 0;
static u32 pwm_clk_hz = 10000; /* pwm system tick rate */
static u32 pwm_total_ms; /* represents the time pwm will lasting */
static u32 pwm_range; /* freq_hz = pwm_clk_hz / pwm_range ==> pwm_range = pwm_clk_hz / freq_hz */
@ -250,7 +248,7 @@ int FPinGpioPwmExample(void)
if (FGPIO_SW_PWM_OK != ret)
{
printf("Pwm instance init failed.\r\n");
return ret;
goto exit;
}
FPwmSetDuty(&pwm_output_1, (u32)(pwm_range * (1 - pwm_duty)));

5
example/peripherals/pmbus/src/pmbus_mp_detect_example.c

@ -96,7 +96,6 @@ static int PmbusInit(void)
static int MpchipInfoGet(void)
{
FError ret = FT_SUCCESS;
u8 data_buf[2]; /* [0] for low 8-bits and [1] for high 8-bits */
u16 register_p;
float voltage;
@ -141,7 +140,7 @@ static int MpchipInfoGet(void)
data_buf[0] = 0;
data_buf[1] = 0;
FI2cMasterReadPoll(&pmbus_instance, MFR_DC_LOOP_CTRL, 1, data_buf, sizeof(u16));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15))
{
printf("Rail 1 voltage will show in direct format, 1mV/LSB.\r\n");
}
@ -172,7 +171,7 @@ static int MpchipInfoGet(void)
data_buf[0] = 0;
data_buf[1] = 0;
FI2cMasterReadPoll(&pmbus_instance, MFR_DC_LOOP_CTRL, 1, data_buf, sizeof(u16));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15))
{
printf("Rail 2 voltage will show in direct format, 1mV/LSB.\r\n");
}

5
example/peripherals/pmbus/src/pmbus_mp_voltage_example.c

@ -101,7 +101,6 @@ static int PmbusInit(void)
static int MpchipInfoGet(void)
{
FError ret = FT_SUCCESS;
u8 data_buf[2]; /* [0] for low 8-bits and [1] for high 8-bits */
/* set to Page 0 */
@ -150,7 +149,7 @@ static int MpchipRail1Voltage(void)
data_buf[0] = 0;
data_buf[1] = 0;
FI2cMasterReadPoll(&pmbus_instance, MFR_DC_LOOP_CTRL, 1, data_buf, sizeof(u16));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15))
{
printf("\r\nRail 1 voltage will show in direct format, 1mV/LSB.\r\n");
}
@ -241,7 +240,7 @@ static int MpchipRail2Voltage(void)
data_buf[0] = 0;
data_buf[1] = 0;
FI2cMasterReadPoll(&pmbus_instance, MFR_DC_LOOP_CTRL, 1, data_buf, sizeof(u16));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15));
if (!GET_REG16_BITS((u16)(data_buf[0] + (data_buf[1] << 8)), 15, 15))
{
printf("\r\nRail 2 voltage will show in direct format, 1mV/LSB.\r\n");
}

2
example/peripherals/pwm/main.c

@ -55,7 +55,7 @@ int main()
LSUserShellLoop();
#else
/* if shell command is not enabled, run example one by one */
FPwmSingleChannelExample()
FPwmSingleChannelExample();
#ifdef CONFIG_FIREFLY_DEMO_BOARD
FPwmDeadBandExample();

1
example/peripherals/qspi/src/qspi_dual_flash_stack_example.c

@ -113,7 +113,6 @@ int FQspiDualFlashStackExample()
u32 ret = FQSPI_SUCCESS;
u32 rw_start_addr;
u8 write_buf[DAT_LENGTH] = {0};
size_t read_len;
#if defined(CONFIG_E2000D_DEMO_BOARD) || defined(CONFIG_E2000Q_DEMO_BOARD) || defined(CONFIG_PD2308_DEMO_BOARD)
/*init iomux*/

2
example/peripherals/sata/sata_pcie/src/sata_pcie_common.c

@ -154,9 +154,7 @@ FError FSataPcieInit(u32 ahci_host)
FError ret = FSATA_SUCCESS;
u32 instance_id = ahci_host;
s32 host;
u32 bdf;
u32 class;
u16 pci_command;
const u32 class_code = PCI_CLASS_STORAGE_SATA_AHCI;
uintptr bar_addr = 0;
u16 vid, did;

2
example/peripherals/sd/src/sdif/sdif_tf_read_write_example.c

@ -144,7 +144,7 @@ err_exit:
if (kStatus_Success != err)
{
FSD_ERROR("TF card read/write failed.");
printf("%s@%d: SD TF card read and write example [failure].\r\n", __func__, __LINE__, err);
printf("%s@%d: SD TF card read and write example [failure].err = %d\r\n", __func__, __LINE__, err);
}
SD_Deinit(&s_inst.card);

7
example/peripherals/spi/src/spim_common.c

@ -109,7 +109,6 @@ int FSpimWaitRxDone(int timeout)
static void FSpimSendRxDoneEvent(void *instance_p, void *param)
{
FASSERT(instance_p && param);
FSpim *spim_p = (FSpim *)instance_p;
boolean *done_flag = (boolean *)param;
FSPIM_DEBUG("Spim send Rx done !!!\n");
@ -122,7 +121,6 @@ static void FSpimSendRxDoneEvent(void *instance_p, void *param)
static void FSpimTxFifoOverflowCallback(void *instance_p, void *param)
{
FASSERT(instance_p);
FSpim *spim_p = (FSpim *)instance_p;
FSPIM_WARN("Spim tx fifo overflow!!!\n");
}
@ -130,14 +128,12 @@ static void FSpimTxFifoOverflowCallback(void *instance_p, void *param)
static void FSpimRxFifoUnderflowCallback(void *instance_p, void *param)
{
FASSERT(instance_p);
FSpim *spim_p = (FSpim *)instance_p;
FSPIM_WARN("Spim rx fifo underflow!!!\n");
}
static void FSpimRxFifoOverflowCallback(void *instance_p, void *param)
{
FASSERT(instance_p);
FSpim *spim_p = (FSpim *)instance_p;
FSPIM_WARN("Spim rx fifo overflow!!!\n");
}
@ -146,8 +142,6 @@ static FError FSpimSetupInterrupt(FSpim *instance_p)
FASSERT(instance_p);
FSpimConfig *config_p = &instance_p->config;
uintptr base_addr = config_p->base_addr;
u32 evt;
u32 mask;
u32 cpu_id = 0;
GetCpuId(&cpu_id);
@ -176,7 +170,6 @@ static FError FSpimSetupInterrupt(FSpim *instance_p)
int FSpimOpsDeInit(void)
{
FSpim *spim_p = &spim;
FError ret = FSPIM_SUCCESS;
/*interrupt deinit*/
InterruptMask(spim_p->config.irq_num);
/*spim deinit*/

5
example/peripherals/timer/tacho/src/tacho_common.c

@ -124,11 +124,6 @@ FError FTachoFunctionInit(u8 id, u32 tacho_mode)
FIOMuxInit();
FIOPadSetTachoMux(TIMER_TACHO_ID);
if (ret != FT_SUCCESS)
{
return ret;
}
if (tacho_mode == FTIMER_WORK_MODE_TACHO)
{
FTachoSetMaxMin(TACHO_MAX, TACHO_MIN); /* Not open operation interface for cmd */

1
example/storage/fatfs/src/cmd_fatfs.c

@ -64,7 +64,6 @@ static void FFatfsExampleUsage(void)
static int FFatfsExampleEntry(int argc, char *argv[])
{
int ret = 0;
u32 id = 0U;
/* check input args of example, exit if invaild */
if (argc < 2)

1
example/storage/memory_pool_test/src/memory_pool_basic_example.c

@ -81,7 +81,6 @@ static boolean MemoryPoolIsAligned(void *addr, u32 alignment)
/* function of memory pool basic test example */
int MemoryPoolBasicExample(void)
{
tlsf_t *tlsf;
FError ret = FMEMP_SUCCESS;
FMemp memp;
Dummy *dummy1;

1
example/system/amp/libmetal_test/apu_running/src/ipi_shmem_demo.c

@ -306,7 +306,6 @@ int ipi_shmem_demo(u32 core_mask)
target_cpu_mask = core_mask;
struct metal_device *ipi_dev = NULL, *shm_dev = NULL;
struct metal_io_region *ipi_io = NULL, *shm_io = NULL;
int ipi_irq;
int ret = 0;
/* Open shared memory device */

1
example/system/amp/libmetal_test/apu_running/src/ipi_waking_up_demo.c

@ -95,7 +95,6 @@ int ipi_waking_up_demo(u32 core_mask)
struct metal_device *dev;
struct metal_io_region *io;
struct channel_s ch;
int ipi_irq;
int ret = 0;
memset(&ch, 0, sizeof(ch));

1
example/system/amp/libmetal_test/apu_running/src/shmem_latency_demo.c

@ -212,7 +212,6 @@ int shmem_latency_demo(u32 core_mask)
struct metal_device *dev;
struct metal_io_region *io;
struct channel_s ch;
int ipi_irq;
int ret = 0;
memset(&ch, 0, sizeof(ch));

1
example/system/amp/libmetal_test/apu_running/src/shmem_throughput_demo.c

@ -340,7 +340,6 @@ int shmem_throughput_demo(u32 core_mask)
struct metal_device *dev;
struct metal_io_region *io;
struct channel_s ch;
int ipi_irq;
int ret = 0;
memset(&ch, 0, sizeof(ch));

3
example/system/amp/libmetal_test/rpu_running/main.c

@ -41,8 +41,7 @@ int main(void)
{
/*set spin lock address*/
LOG_SPIN_SET(FSPIN_LOCK_ADDR);
struct metal_device *device;
struct metal_io_region *io;
int ret = 0;
ret = FLibmetalSysInit();
if (ret)

1
example/system/amp/libmetal_test/rpu_running/src/ipi_shmem_demod.c

@ -225,7 +225,6 @@ int ipi_shmem_demod()
struct metal_device *ipi_dev = NULL;
struct metal_device *shm_dev = NULL;
struct metal_io_region *ipi_io = NULL, *shm_io = NULL;
int ipi_irq;
int ret = 0;
/* Open shared memory device */

1
example/system/amp/libmetal_test/rpu_running/src/ipi_waking_up_demod.c

@ -101,7 +101,6 @@ int ipi_waking_up_demod()
{
struct channel_s ch;
struct metal_device *ipi_dev = NULL;
int ipi_irq;
int ret = 0;
/* Open IPI device */

1
example/system/amp/libmetal_test/rpu_running/src/shmem_atomic_demod_rpu.c

@ -102,7 +102,6 @@ int atomic_shmem_demod(void)
struct metal_device *ipi_dev = NULL;
struct metal_device *shm_dev = NULL;
struct metal_io_region *ipi_io = NULL, *shm_io = NULL;
int ipi_irq;
int ret = 0;
LIBMETAL_ATSH_RPU_DEBUG_I("atomic operation over shared memory.");

1
example/system/amp/libmetal_test/rpu_running/src/shmem_latency_demod.c

@ -166,7 +166,6 @@ int shmem_latency_demod()
struct metal_device *ipi_dev = NULL;
struct metal_device *shm_dev = NULL;
struct metal_device *ttc_dev = NULL;
int ipi_irq;
int ret = 0;
memset(&ch, 0, sizeof(ch));

3
example/system/amp/libmetal_test/rpu_running/src/shmem_throughput_demod.c

@ -132,7 +132,7 @@ static int measure_shmem_throughputd(struct channel_s *ch)
void *lbuf = NULL;
int ret = 0;
u64 s, i;
u64 tstart,tend,tdiff;
u64 tstart,tend;
u32 rx_count, rx_avail, tx_count, iterations;
unsigned long tx_avail_offset, rx_avail_offset;
unsigned long tx_addr_offset, rx_addr_offset;
@ -304,7 +304,6 @@ int shmem_throughput_demod()
struct metal_device *ipi_dev = NULL;
struct metal_device *shm_dev = NULL;
struct metal_device *ttc_dev = NULL;
int ipi_irq;
int ret = 0;
/* Open shared memory device */

1
example/system/cxx/cryptopp/src/cmd_cyptopp.c

@ -53,7 +53,6 @@ static void FCryptoExampleUsage(void)
static int FCryptoExampleEntry(int argc, char *argv[])
{
int ret = 0;
u32 id;
/* check input args of example, exit if invaild */
if (argc < 2)
{

3
example/system/nested_interrupt/src/nested_interrupt_timer_example.c

@ -100,9 +100,6 @@ static void FGenericPhysicalTimerHandler(s32 vector, void *param)
static void FGenericVirtualTimerHandlerFunc(void)
{
static u64 delta_old;
u64 delta;
if(physical_intr_calling == TRUE)
{
nest_occur = TRUE;

9
example/system/newlib_test/src/math.c

@ -182,7 +182,6 @@ run_vector_1 (int vector,
char *args)
{
FILE *f;
int mag;
double result;
if (vector)
@ -235,9 +234,6 @@ run_vector_1 (int vector,
double arg1 = thedouble(p->qs[1].msw, p->qs[1].lsw);
double arg2 = thedouble(p->qs[2].msw, p->qs[2].lsw);
double r;
double rf;
errno = 0;
merror = 0;
mname = 0;
@ -261,7 +257,6 @@ run_vector_1 (int vector,
else if (strcmp(args,"ff")==0)
{
float arga;
double a;
typedef float (*pdblfunc) (float);
@ -283,8 +278,6 @@ run_vector_1 (int vector,
}
else if (strcmp(args,"fff")==0)
{
double a,b;
float arga;
float argb;
@ -308,8 +301,6 @@ run_vector_1 (int vector,
}
else if (strcmp(args,"fif")==0)
{
double a,b;
float arga;
float argb;

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