diff --git a/board/d2000_test/fio_mux.c b/board/d2000_test/fio_mux.c index ce43c973c..dea35bda1 100644 --- a/board/d2000_test/fio_mux.c +++ b/board/d2000_test/fio_mux.c @@ -56,10 +56,41 @@ void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id) /* QspiMux has been set in uboot */ } -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) +void FIOPadSetGpioMux(u32 gpio_id, u32 port_id, u32 pin_id) { - FIOCtrlSetFunc(&ioctrl, FIOCTRL_LPC_LAD0_PAD, FIOCTRL_FUNC1); - FIOCtrlSetFunc(&ioctrl, FIOCTRL_LPC_LAD1_PAD, FIOCTRL_FUNC1); + if (gpio_id == FGPIO_CTRL_1) + { + if (port_id == FGPIO_PORT_A) + { + switch (pin_id) + { + case 5: /* gpio 1-a-5 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_CSN0_PAD, FIOCTRL_FUNC1); + break; + case 6: /* gpio 1-a-6 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SCK_PAD, FIOCTRL_FUNC1); + break; + case 7: /* gpio 1-a-7 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SO_PAD, FIOCTRL_FUNC1); + break; + default: + break; + } + } + else if (port_id == FGPIO_PORT_B) + { + switch (pin_id) + { + case 0: /* gpio 1-b-0 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SI_PAD, FIOCTRL_FUNC2); + break; + default: + break; + } + } + + } + } void FIOPadSetI2cMux(u32 i2c_id) diff --git a/board/d2000_test/fio_mux.h b/board/d2000_test/fio_mux.h index 87b1b3349..5afd770ee 100644 --- a/board/d2000_test/fio_mux.h +++ b/board/d2000_test/fio_mux.h @@ -33,7 +33,7 @@ extern "C" void FIOPadSetSpimMux(u32 spim_id); void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id); -void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id); +void FIOPadSetGpioMux(u32 gpio_id, u32 port_id, u32 pin_id); void FIOPadSetCanMux(u32 can_id); void FIOPadSetI2cMux(u32 i2c_id); diff --git a/board/e2000d_demo/fio_mux.c b/board/e2000d_demo/fio_mux.c index e7fd78897..d624fba70 100644 --- a/board/e2000d_demo/fio_mux.c +++ b/board/e2000d_demo/fio_mux.c @@ -65,55 +65,55 @@ void FIOPadSetSpimMux(u32 spim_id) */ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) { - if (FGPIO3_ID == gpio_id) + if (FGPIO_CTRL_3 == gpio_id) { switch (pin_id) { - case 3: /* gpio 3-a-3 */ + case 3: /* gpio 3-3 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_A29_REG0_OFFSET, FIOPAD_FUNC6); break; - case 4: /* gpio 3-a-4 */ + case 4: /* gpio 3-4 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_C29_REG0_OFFSET, FIOPAD_FUNC6); break; - case 5: /* gpio 3-a-5 */ + case 5: /* gpio 3-5 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_C27_REG0_OFFSET, FIOPAD_FUNC6); break; - case 6: /* gpio 3-a-6 */ + case 6: /* gpio 3-6 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_A27_REG0_OFFSET, FIOPAD_FUNC6); break; - case 7: /* gpio 3-a-7 */ /*cannot use this pin*/ + case 7: /* gpio 3-7 */ /*cannot use this pin*/ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AJ49_REG0_OFFSET, FIOPAD_FUNC6); break; - case 8: /* gpio 3-a-8 */ + case 8: /* gpio 3-8 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AL45_REG0_OFFSET, FIOPAD_FUNC6); break; - case 9: /* gpio 3-a-9 */ + case 9: /* gpio 3-9 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AL43_REG0_OFFSET, FIOPAD_FUNC6); break; default: break; } } - else if (FGPIO4_ID == gpio_id) + else if (FGPIO_CTRL_4 == gpio_id) { switch (pin_id) { - case 5: /* gpio 4-a-5 */ + case 5: /* gpio 4-5 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_W47_REG0_OFFSET, FIOPAD_FUNC6); break; - case 9: /* gpio 4-a-9 */ + case 9: /* gpio 4-9 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_U49_REG0_OFFSET, FIOPAD_FUNC6); break; - case 10: /* gpio 4-a-10 */ + case 10: /* gpio 4-10 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE45_REG0_OFFSET, FIOPAD_FUNC6); break; - case 11: /* gpio 4-a-11 */ + case 11: /* gpio 4-11 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC45_REG0_OFFSET, FIOPAD_FUNC6); break; - case 12: /* gpio 4-a-12 */ + case 12: /* gpio 4-12 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE43_REG0_OFFSET, FIOPAD_FUNC6); break; - case 13: /* gpio 4-a-13 */ + case 13: /* gpio 4-13 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AA43_REG0_OFFSET, FIOPAD_FUNC6); break; default: diff --git a/board/e2000q_demo/fio_mux.c b/board/e2000q_demo/fio_mux.c index 5acbede7c..20f0f52dd 100644 --- a/board/e2000q_demo/fio_mux.c +++ b/board/e2000q_demo/fio_mux.c @@ -99,67 +99,67 @@ void FIOPadSetSpimMux(u32 spim_id) */ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) { - if (FGPIO2_ID == gpio_id) + if (FGPIO_CTRL_2 == gpio_id) { switch (pin_id) { - case 11: /* gpio 2-a-11 */ + case 11: /* gpio 2-11 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_N49_REG0_OFFSET, FIOPAD_FUNC0); break; - case 12: /* gpio 2-a-12 */ + case 12: /* gpio 2-12 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_L51_REG0_OFFSET, FIOPAD_FUNC0); break; - case 13: /* gpio 2-a-13 */ + case 13: /* gpio 2-13 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_L49_REG0_OFFSET, FIOPAD_FUNC0); break; - case 14: /* gpio 2-a-14 */ + case 14: /* gpio 2-14 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_N53_REG0_OFFSET, FIOPAD_FUNC0); break; - case 15: /* gpio 2-a-15 */ + case 15: /* gpio 2-15 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_J53_REG0_OFFSET, FIOPAD_FUNC0); break; } } - else if (FGPIO3_ID == gpio_id) + else if (FGPIO_CTRL_3 == gpio_id) { switch (pin_id) { - case 3: /* gpio 3-a-3 */ + case 3: /* gpio 3-3 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_A33_REG0_OFFSET, FIOPAD_FUNC6); break; - case 4: /* gpio 3-a-4 */ + case 4: /* gpio 3-4 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_C33_REG0_OFFSET, FIOPAD_FUNC6); break; - case 5: /* gpio 3-a-5 */ + case 5: /* gpio 3-5 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_C31_REG0_OFFSET, FIOPAD_FUNC6); break; - case 6: /* gpio 3-a-6 */ + case 6: /* gpio 3-6 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_A31_REG0_OFFSET, FIOPAD_FUNC6); break; default: break; } } - else if (FGPIO4_ID == gpio_id) + else if (FGPIO_CTRL_4 == gpio_id) { switch (pin_id) { - case 5: /* gpio 4-a-5 */ + case 5: /* gpio 4-5 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_W51_REG0_OFFSET, FIOPAD_FUNC6); break; - case 9: /* gpio 4-a-9 */ + case 9: /* gpio 4-9 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_U53_REG0_OFFSET, FIOPAD_FUNC6); break; - case 10: /* gpio 4-a-10 */ + case 10: /* gpio 4-10 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE49_REG0_OFFSET, FIOPAD_FUNC6); break; - case 11: /* gpio 4-a-11 */ + case 11: /* gpio 4-11 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC49_REG0_OFFSET, FIOPAD_FUNC6); break; - case 12: /* gpio 4-a-12 */ + case 12: /* gpio 4-12 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE47_REG0_OFFSET, FIOPAD_FUNC6); break; - case 13: /* gpio 4-a-13 */ + case 13: /* gpio 4-13 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AA47_REG0_OFFSET, FIOPAD_FUNC6); break; default: diff --git a/board/firefly/fio_mux.c b/board/firefly/fio_mux.c index d208966f6..efbe08a1b 100644 --- a/board/firefly/fio_mux.c +++ b/board/firefly/fio_mux.c @@ -76,19 +76,25 @@ void FIOPadSetSpimMux(u32 spim_id) */ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) { - if (FGPIO0_ID == gpio_id) + if (FGPIO_CTRL_0 == gpio_id) { switch (pin_id) { + case 0: /* gpio 0-0 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AN59_REG0_OFFSET, FIOPAD_FUNC5); + break; case 5: /* gpio 0-5 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_N43_REG0_OFFSET, FIOPAD_FUNC6); break; + case 14: /* gpio 0-14 */ + FIOPadSetFunc(&iopad_ctrl, FIOPAD_AJ59_REG0_OFFSET, FIOPAD_FUNC5); + break; default: FBOARD_IO_DEBUG("No preconfiguration for GPIO-%d pin-%d iopad mux info.\r\n", gpio_id, pin_id); break; } } - else if (FGPIO1_ID == gpio_id) + else if (FGPIO_CTRL_1 == gpio_id) { switch (pin_id) { @@ -112,7 +118,7 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) break; } } - else if (FGPIO2_ID == gpio_id) + else if (FGPIO_CTRL_2 == gpio_id) { switch (pin_id) { @@ -124,7 +130,7 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) break; } } - else if (FGPIO3_ID == gpio_id) + else if (FGPIO_CTRL_3 == gpio_id) { switch (pin_id) { @@ -139,18 +145,18 @@ void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) break; } } - else if (FGPIO4_ID == gpio_id) + else if (FGPIO_CTRL_4 == gpio_id) { switch (pin_id) { - case 11: /* gpio 4-a-11 */ + case 11: /* gpio 4-11 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AC49_REG0_OFFSET, FIOPAD_FUNC6); break; - case 12: /* gpio 4-a-12 */ + case 12: /* gpio 4-12 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AE47_REG0_OFFSET, FIOPAD_FUNC6); break; - case 13: /* gpio 4-a-13 */ + case 13: /* gpio 4-13 */ FIOPadSetFunc(&iopad_ctrl, FIOPAD_AA47_REG0_OFFSET, FIOPAD_FUNC6); break; default: diff --git a/board/ft2004_dsk/fio_mux.c b/board/ft2004_dsk/fio_mux.c index c571d9a00..f6a98e3ef 100644 --- a/board/ft2004_dsk/fio_mux.c +++ b/board/ft2004_dsk/fio_mux.c @@ -82,6 +82,42 @@ void FIOPadSetI2cMux(u32 i2c_id) } } +void FIOPadSetGpioMux(u32 gpio_id, u32 port_id, u32 pin_id) +{ + if (gpio_id == FGPIO_CTRL_1) + { + if (port_id == FGPIO_PORT_A) + { + switch (pin_id) + { + case 5: /* gpio 1-a-5 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_CSN0_PAD, FIOCTRL_FUNC1); + break; + case 6: /* gpio 1-a-6 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SCK_PAD, FIOCTRL_FUNC1); + break; + case 7: /* gpio 1-a-7 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SO_PAD, FIOCTRL_FUNC1); + break; + default: + break; + } + } + else if (port_id == FGPIO_PORT_B) + { + switch (pin_id) + { + case 0: /* gpio 1-b-0 */ + FIOCtrlSetFunc(&ioctrl, FIOCTRL_SPI0_SI_PAD, FIOCTRL_FUNC2); + break; + default: + break; + } + } + + } +} + void FIOPadSetCanMux(u32 can_id) { if (can_id == FCAN0_ID) diff --git a/board/ft2004_dsk/fio_mux.h b/board/ft2004_dsk/fio_mux.h index b0d012478..5afd770ee 100644 --- a/board/ft2004_dsk/fio_mux.h +++ b/board/ft2004_dsk/fio_mux.h @@ -33,6 +33,7 @@ extern "C" void FIOPadSetSpimMux(u32 spim_id); void FIOPadSetQspiMux(u32 qspi_id, u32 cs_id); +void FIOPadSetGpioMux(u32 gpio_id, u32 port_id, u32 pin_id); void FIOPadSetCanMux(u32 can_id); void FIOPadSetI2cMux(u32 i2c_id); diff --git a/board/pd2308_demo/fio_mux.c b/board/pd2308_demo/fio_mux.c index 79d087ac1..d96ee3bb8 100644 --- a/board/pd2308_demo/fio_mux.c +++ b/board/pd2308_demo/fio_mux.c @@ -80,9 +80,9 @@ void FIOPadSetSpimMux(u32 spim_id) void FIOPadSetGpioMux(u32 gpio_id, u32 pin_id) { FASSERT(gpio_id < FGPIO_NUM); - FASSERT(pin_id < FGPIO_CTRL_PIN_NUM); + FASSERT(pin_id < FGPIO_PIN_NUM); - if (FGPIO0_ID == gpio_id) + if (FGPIO_CTRL_0 == gpio_id) { switch (pin_id) { diff --git a/doc/ChangeLog.md b/doc/ChangeLog.md index 97ad4e28c..f72724e9d 100644 --- a/doc/ChangeLog.md +++ b/doc/ChangeLog.md @@ -1,3 +1,32 @@ +# Phytium Standalone SDK 2024-05-16 ChangeLog + +Change Log since 2024-05-15 + +## soc + +- add gpio table to define the gpio pin config + +## board + +- update io mux for used gpio + +## drivers + +- re-work fgpio, undef gpio ctrl, use gpio pin as instance + +## example + +- update pin example following gpio drivers + +# Phytium Standalone SDK 2024-05-15 ChangeLog + +Change Log since 2024-05-15 + +## IDE + +- Modify the sample project script +- Modify user documentation + # Phytium Standalone SDK 2024-05-15 ChangeLog Change Log since 2024-05-14 @@ -146,6 +175,7 @@ Change Log since 2024-04-18 ## third-party - delete eth_poll in fxmac,the operations performed by eth_poll are merged into eth_input + - adjust lwip_port.c which support gmac and xmac well in rtos # Phytium Standalone SDK 2024-04-22 ChangeLog @@ -155,6 +185,7 @@ Change Log since 2024-04-22 ## example - add pwm single channel example + - modify pwm example README ## board diff --git a/doc/reference/driver/fgpio.md b/doc/reference/driver/fgpio.md index 28149f031..edc0f3425 100644 --- a/doc/reference/driver/fgpio.md +++ b/doc/reference/driver/fgpio.md @@ -4,17 +4,17 @@ - GPIO(General-purpose input/output)，即通用型输入输出，其引脚可以供使用者通过程序控制其输入、输出，常用于产生时钟，作为片选信号和模拟低速通信协议等场景 -- FT2000/4和D2000提供两个 GPIO 模块，每个 GPIO 模块有 16 位接口，每8位一组，分别是A组和B组，GPIO可以控制外部IO的输入输出方向，作为输出时，内部寄存器的数据输出到片外，作为输入时，片外的数据被锁存在内部寄存器 +- FT2000/4和D2000提供两个 GPIO 模块，每个 GPIO 模块有 16 位接口，每 8 位一组，分别是A组和B组，GPIO可以控制外部IO的输入输出方向，作为输出时，内部寄存器的数据输出到片外，作为输入时，片外的数据被锁存在内部寄存器 -- FGPIO 驱动支持配置 GPIO 引脚的输入输出方向，输出高低电平，或者获取输入电平，配置引脚的中断触发模式，配置引脚的中断响应回调函数等 +- E2000和Phytium PI提供六个 GPIO 模块，每个模块有 16 个接口，0 ~ 2 号 GPIO 模块中每个引脚独立处理中断，3 ~ 5 号 GPIO 模块中各引脚的中断合并上报 -- FGPIO_VERSION_1 对应 FT2000/4和D2000 的 GPIO，FGPIO_VERSION_2 对应 E2000的 GPIO，具体差异请参考软件编程手册 +- FGPIO 驱动支持配置 GPIO 引脚的输入输出方向，输出高低电平，或者获取输入电平，配置引脚的中断触发模式，配置引脚的中断响应回调函数等 ## 2. 功能 - FGPIO 驱动程序主要完成GPIO相关的功能配置，包括 -- 1. GPIO 控制器初始化 +- 1. GPIO 引脚初始化 - 2. GPIO 引脚输入输出方向设置 - 3. GPIO 引脚输出和输入 - 4. GPIO 引脚中断使能和屏蔽 @@ -24,11 +24,13 @@ - 驱动相关的源文件如下， - drivers/pin/fgpio ``` +soc +└── fgpio_table.c + . ├── Kconfig ├── fgpio.c ├── fgpio.h -├── fgpio_g.c ├── fgpio_hw.h ├── fgpio_selftest.c ├── fgpio_intr.c @@ -41,7 +43,7 @@ - 参考以下步骤完成 FGPIO 硬件配置， - 1. 获取FT2000/4, D2000或E2000的软件编程手册，参考引脚复用表，设置引脚复用为 GPIO -- 2. 初始化 GPIO 控制器实例 +- 2. 初始化 GPIO 引脚实例 - 3. 设置 GPIO 引脚的输入，输出方向 - 4. 获取 GPIO 引脚上的输入，或者设置 GPIO 引脚的输出电平 - 5. 设置 GPIO 引脚的中断屏蔽位和中断触发类型，注册引脚的中断回调函数 @@ -62,48 +64,36 @@ ```c typedef struct { - u32 instance_id; /* GPIO实例ID */ - uintptr base_addr; /* GPIO控制器基地址 */ -#if defined(FGPIO_VERSION_1) /* FT2000-4, D2000 */ - u32 irq_num; /* GPIO控制器中断号 */ -#elif defined(FGPIO_VERSION_2) /* E2000 GPIO 0 ~ 5 */ - u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号 */ -#endif + u32 id; /* GPIO标号，0 ~ FGPIO_NUM */ + u32 ctrl; /* GPIO所属的控制器，0 ~ FGPIO_CTRL_NUM */ + u32 port; /* GPIO所属的Port, Port A, B */ + u32 pin; /* GPIO的引脚号，0 ~ FGPIO_PIN_NUM */ + uintptr base_addr; /* GPIO控制器基地址 */ + u32 irq_num; /* GPIO中断号，如果不支持中断，置位为 0 */ u32 irq_priority; /* 中断优先级 */ -} FGpioConfig; /* GPIO控制器配置 */ -``` - -#### FGpioPin - -```c -typedef struct _FGpioPin -{ - FGpioPinId index; /* 索引 */ - u32 is_ready; - FGpio *instance; - FGpioInterruptCallback irq_cb; /* 中断回调函数, Port-A有效 */ - void *irq_cb_params; /* 中断回调函数的入参, Port-A有效 */ - boolean irq_one_time; /* Port-A有效, TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */ -} FGpioPin; /* GPIO引脚实例 */ + u32 cap; /* GPIO引脚能力集 */ +} FGpioConfig; /* GPIO引脚配置 */ ``` #### FGpio ```c -typedef struct _FGpio +typedef struct { FGpioConfig config; u32 is_ready; - FGpioPin *pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM]; -} FGpio; /* GPIO控制器实例 */ + FGpioInterruptCallback irq_cb; /* 中断回调函数 */ + void *irq_cb_params; /* 中断回调函数的入参 */ +} FGpio; /* GPIO引脚实例 */ ``` + ### 5.2 错误码定义 -- [0x0] FGPIO_SUCCESS : success +- FGPIO_SUCCESS : success -- [0x1050000] FGPIO_ERR_INVALID_PARA : invalid input parameters +- FGPIO_ERR_INVALID_PARA : invalid input parameters -- [0x1050001] FGPIO_ERR_INVALID_STATE : invalid state +- FGPIO_ERR_INVALID_STATE : invalid state ### 5.3 用户API接口 @@ -111,63 +101,25 @@ typedef struct _FGpio #### FGpioLookupConfig ```c -const FGpioConfig *FGpioLookupConfig(u32 instance_id); +const FGpioConfig *FGpioLookupConfig(u32 gpio_id) ``` Note: -- 获取GPIO控制器的默认配置 +- 获取GPIO引脚的默认配置 Input: -- {u32} instance_id, GPIO控制器实例号 +- {u32} gpio_id, GPIO引脚号, 0 ~ FGPIO_NUM，可以通过宏 FGPIO_ID 获取编码 Return: -- {const FGpioConfig *} GPIO控制器的默认配置 +- {const FGpioConfig *} GPIO引脚的参数和默认配置 #### FGpioCfgInitialize ```c -FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config); -``` - -Note: - -- 初始化GPIO控制器实例 - -Input: - -- {FGpio} *instance, GPIO控制器实例 -- {FGpioConfig} *config, GPIO控制器配置 - -Return: - -- {FError} FGPIO_SUCCESS 表示初始化成功 - -#### FGpioDeInitialize - -```c -void FGpioDeInitialize(FGpio *const instance); -``` - -Note: - -- 去初始化GPIO控制器实例 - -Input: - -- {FGpio} *instance, GPIO控制器实例 - -Return: - -- 无 - -#### FGpioPinInitialize - -```c -FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin, - const FGpioPinId pin_id); +FError FGpioCfgInitialize(FGpio *const pin, const FGpioConfig *const config) ``` Note: @@ -176,18 +128,17 @@ Note: Input: -- {FGpio} *instance, GPIO控制器实例 -- {FGpioPin} *pin_instance, GPIO引脚实例 -- {FGpioPinId} index, GPIO引脚索引 +- {FGpio} *instance, GPIO引脚实例 +- {FGpioConfig} *config, GPIO引脚配置 Return: - {FError} FGPIO_SUCCESS 表示初始化成功 -#### FGpioPinDeInitialize +#### FGpioDeInitialize ```c -void FGpioPinDeInitialize(FGpioPin *const pin); +void FGpioDeInitialize(FGpio *const pin); ``` Note: @@ -196,34 +147,16 @@ Note: Input: -- {FGpioPin} *pin_instance, GPIO引脚实例 +- {FGpio} *instance, GPIO引脚实例 Return: -- {FError} FGPIO_SUCCESS 表示初始化成功 - -#### FGpioGetPinIrqSourceType - -```c -FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin *const pin); -``` - -Note: - -- 获取引脚中断的上报方式 - -Input: - -- {FGpioPin} *pin_instance, GPIO引脚实例 - -Return: - -- {FGpioIrqSourceType} 引脚中断的上报方式 +- 无 #### FGpioSetDirection ```c -void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir); +void FGpioSetDirection(FGpio *const pin, FGpioDirection dir) ``` Note: @@ -233,7 +166,7 @@ Note: Input: -- @param {FGpioPin} *instance, GPIO控制器实例 +- @param {FGpio} *pin, GPIO引脚实例 - @param {FGpioDirection} dir, 待设置的GPIO的方向 Return: @@ -243,7 +176,7 @@ Return: #### FGpioGetDirection ```c -FGpioDirection FGpioGetDirection(FGpioPin *const pin); +FGpioDirection FGpioGetDirection(FGpio *const pin) ``` Note: @@ -253,7 +186,7 @@ Note: Input: -- {FGpioPin} *pin, GPIO引脚实例 +- {FGpio} *pin, GPIO引脚实例 Return: @@ -262,7 +195,7 @@ Return: #### FGpioSetOutputValue ```c -FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output); +FError FGpioSetOutputValue(FGpio *const pin, const FGpioVal output) ``` Note: @@ -272,8 +205,8 @@ Note: Input: -- {FGpioPin} *pin, GPIO引脚实例 -- {FGpioPinVal} output, GPIO引脚的输出值 +- {FGpio} *pin, GPIO引脚实例 +- {FGpioVal} output, GPIO引脚的输出值 Return: @@ -284,7 +217,7 @@ Return: - 获取GPIO引脚的输入值 ```c -FGpioPinVal FGpioGetInputValue(FGpioPin *const pin); +FGpioVal FGpioGetInputValue(FGpio *const pin) ``` Note: @@ -293,71 +226,71 @@ Note: Input: -- {FGpioPin} *instance, GPIO引脚实例 -- {FGpioPinVal} output, GPIO引脚的输出值 +- {FGpio} *instance, GPIO引脚实例 Return: -- {FGpioPinVal} 获取的输入值，高电平/低电平 +- {FGpioVal} 获取的输入值，高电平/低电平 #### FGpioGetInterruptMask -- 获取GPIO A组引脚的中断屏蔽位 +- 获取GPIO 引脚的中断屏蔽位 ```c -void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled) +void FGpioGetInterruptMask(FGpio *const pin, u32 *mask, u32 *enabled) ``` Note: -- 获取的是A组所有Pin的中断屏蔽位和中断使能位 +- 获取的是所有Pin的中断屏蔽位和中断使能位 Input: -- {FGpio} *instance, GPIO控制器实例 -- {u32} *mask, 返回的GPIO A组引脚中断屏蔽位 -- {u32} *enabled, 返回的GPIO A组中断使能位 +- {FGpio} *pin, GPIO引脚实例 +- {u32} *mask, 返回的GPIO引脚中断屏蔽位 +- {u32} *enabled, 返回的GPIO引脚中断使能位 Return: - 无 + #### FGpioSetInterruptMask -- 设置GPIO A组引脚的中断屏蔽位 +- 设置GPIO引脚的中断屏蔽位 ```c -void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable); +void FGpioSetInterruptMask(FGpio *const pin, boolean enable) ``` Note: -- index对应的引脚必须为A组引脚，B组引脚不支持中断 +- 引脚必须为A组引脚，B组引脚不支持中断 Input: -- {FGpioPin} *pin, GPIO引脚实例 +- {FGpio} *pin, GPIO引脚实例 - {boolean} enable, TRUE表示使能GPIO引脚中断，FALSE表示去使能GPIO引脚中断 Return: - 无 + #### FGpioGetInterruptType -- 获取GPIO A组引脚的中断类型和中断极性 +- 获取GPIO引脚的中断类型和中断极性 ```c -void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity) +void FGpioGetInterruptType(FGpio *const pin, FGpioIrqType *type) ``` Note: -- 获取的是A组所有Pin的电平和极性 +- 获取GPIO引脚的中断类型和中断极性 Input: -- {FGpio} *instance, GPIO控制器实例 -- {u32} *levels, GPIO A组引脚中断电平类型 -- {u32} *polarity, GPIO A组引脚中断极性类型 +- {FGpio} *pin, GPIO引脚实例 +- {FGpioIrqType} *type, GPIO引脚中断触发类型 Return: @@ -368,7 +301,7 @@ Return: - 设置GPIO引脚的中断类型 ```c -void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type) +void FGpioSetInterruptType(FGpio *const pin, const FGpioIrqType type) ``` Note: @@ -384,9 +317,9 @@ Return: - 无 -#### FGpioInterruptHandler +#### FGpioSharedInterruptHandler -- GPIO中断处理函数 +- GPIO 引脚中断处理函数 ```c void FGpioInterruptHandler(s32 vector, void *param) @@ -405,46 +338,20 @@ Return: - 无 - -#### FGpioPinInterruptHandler - -- GPIO中断处理函数 - -```c -void FGpioPinInterruptHandler(s32 vector, void *param) -``` - -Note: - -- 需要用户将此函数注册Gic上，才能生效 - -Input: - -- {s32} vector, 中断输入参数1 -- {void} *param, 中断输入参数2 - -Return: - -- 无 - #### FGpioRegisterInterruptCB -- 注册GPIO引脚中断回调函数 +- 注册GPIO引脚中断回调函数(引脚通过控制器统一上报中断，共用中断号) ```c -void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time) +void FGpioRegisterInterruptCB(FGpio *const pin, FGpioInterruptCallback cb, + void *cb_param) ``` -Note: - -- 注册的回调函数在`FGpioInterruptHandler`中被调用 - Input: -- {FGpioPin} pin, GPIO引脚实例 +- {FGpio} pin, GPIO引脚 - {FGpioInterruptCallback} cb, GPIO引脚中断回调函数 - {void} *cb_param, GPIO引脚中断回调函数输入参数 -- {boolean} irq_one_time, TRUE表示引脚中断触发一次后自动关闭中断，用于电平敏感中断 Return: diff --git a/doc/reference/ide/figs/add_noproj_debugconfig.png b/doc/reference/ide/figs/add_noproj_debugconfig.png new file mode 100644 index 000000000..45904e019 Binary files /dev/null and b/doc/reference/ide/figs/add_noproj_debugconfig.png differ diff --git a/doc/reference/ide/figs/e2000_terminal.png b/doc/reference/ide/figs/e2000_terminal.png index aa7cabe69..110178f67 100644 Binary files a/doc/reference/ide/figs/e2000_terminal.png and b/doc/reference/ide/figs/e2000_terminal.png differ diff --git a/doc/reference/ide/figs/edit_noproj_debugconfig.png b/doc/reference/ide/figs/edit_noproj_debugconfig.png new file mode 100644 index 000000000..dbd34853d Binary files /dev/null and b/doc/reference/ide/figs/edit_noproj_debugconfig.png differ diff --git a/doc/reference/ide/figs/noproj_debug.png b/doc/reference/ide/figs/noproj_debug.png new file mode 100644 index 000000000..c9ef20f1d Binary files /dev/null and b/doc/reference/ide/figs/noproj_debug.png differ diff --git a/doc/reference/ide/figs/noproj_debug_source.png b/doc/reference/ide/figs/noproj_debug_source.png new file mode 100644 index 000000000..34555519d Binary files /dev/null and b/doc/reference/ide/figs/noproj_debug_source.png differ diff --git a/doc/reference/ide/figs/terminal_action.png b/doc/reference/ide/figs/terminal_action.png new file mode 100644 index 000000000..54a7d22b3 Binary files /dev/null and b/doc/reference/ide/figs/terminal_action.png differ diff --git a/doc/reference/ide/figs/terminal_addaction.png b/doc/reference/ide/figs/terminal_addaction.png new file mode 100644 index 000000000..b9f26403b Binary files /dev/null and b/doc/reference/ide/figs/terminal_addaction.png differ diff --git a/doc/reference/ide/ide.md b/doc/reference/ide/ide.md index 02dbd4e81..ce000922e 100644 --- a/doc/reference/ide/ide.md +++ b/doc/reference/ide/ide.md @@ -215,9 +215,14 @@ PhyStudio支持通过sdkconfig配置工程，`Makefile工程`类型支持绝大 ![](./figs/com5.png) ![](./figs/e2000_terminal.png) - > 注意有些开发板启动后默认会进入 Linux 环境，要进行后续开发和调试，需要在 U-Boot 界面中修改 bootcmd 使得开发板启动后停留在 U-Boot 界面 +- 串口视图支持命令快捷键，可以为一连串命令创建快捷键，在成功连接串口之后在底部点击右键->Add Action，在弹出的对话框中输入名称和命令，完成之后会在底部显示快捷键，点击快捷键按钮直接发送命令，编辑和删除的操作跟添加类似。 + +![](./figs/terminal_addaction.png) +![](./figs/terminal_action.png) + + ### 1.8 通过网络下载程序 - 对于有网口的开发板，可以使用 TFTP 直接将镜像加载到开发板上进行启动，首先需要用网线连接开发板，PhyStudio 主机侧连接开发板的网络需要配置好 ip 网段与开发板后续配置的 ip 配套 @@ -315,10 +320,25 @@ bootelf -p 0xa0100000 - 通过 Windows > Show View > Memory 查看运行实时内存 ![](./figs/memory.png) +### 1.10 无工程调试 +PhyStudio支持无工程调试，顾名思义也就是在没有创建工程的情况下进行调试，这主要是针对只想使用PhyStudio调试功能的用户，用户选择一个外部的elf文件，然后导入PhyStudio进行调试 +#### 1.10.1 创建调试配置 +- 点击工具栏的调试菜单下拉箭头->Debug Configurations.. + +![](./figs/add_noproj_debugconfig.png) + +- 在弹出的对话框中双击Phytium GDB OpenOCD No-Proj Debugging选项创建一个新的调试配置，输入名字，选择Aarch类型，然后选择需要调试的elf文件，在Debugger页签选择好调试接口类型后点击Debug按钮进行调试 + +![](./figs/edit_noproj_debugconfig.png) +#### 1.10.2 配置源码 +- 无工程调试启动后默认是没有关联源码的，需要手动添加，先从①处复制elf文件编译路径->点击Edit Source Lookup Path，按照下图所示步骤添加源码路径映射，把编译所在的源码路径和本机所在的源码路径关联起来，完成后就可以查看源码了，调试方式跟有工程调试一样 + +![](./figs/noproj_debug_source.png) +![](./figs/noproj_debug.png) -### 1.10 Git版本控制 +### 1.11 Git版本控制 - PhyStudio加入了EGit插件，支持git版本控制，具体使用方法参照官方文档[EGit用户指导](https://wiki.eclipse.org/EGit/User_Guide "EGit用户指导")，这里介绍一些基本的用法 -#### 1.10.1 从远程仓库克隆 +#### 1.11.1 从远程仓库克隆 - 点击右上角的按钮，切换到Git透视图，如下图所示，或者点击菜单栏的Window->Show View->Other..->Git->Git Repositories ![](./figs/git_perspective.png) @@ -336,7 +356,7 @@ bootelf -p 0xa0100000 ![](./figs/gitclone_finish.png) ![](./figs/gitview.png) -#### 1.10.2 创建一个新的Git仓库 +#### 1.11.2 创建一个新的Git仓库 - 在Git视图中点击创建Git新仓库按钮，选择仓库目录，点击`Create`按钮 ![](./figs/gitrepos_create.png) @@ -353,7 +373,7 @@ bootelf -p 0xa0100000 ![](./figs/git_remotes.png) -#### 1.10.3 把代码推送到远程仓库 +#### 1.11.3 把代码推送到远程仓库 - 如果代码还没有加入到git仓库里面，需要右键点击工程->Team->Share Project.. @@ -374,8 +394,8 @@ bootelf -p 0xa0100000 ![](./figs/git_pushresult.png) -### 1.11 开发技巧 -#### 1.11.1 常用快捷键 +### 1.12 开发技巧 +#### 1.12.1 常用快捷键 Alt+/ 代码提示 F3或者Ctrl+鼠标左键 查看定义或声明 F4 查看继承关系 diff --git a/drivers/pin/fgpio/Kconfig b/drivers/pin/fgpio/Kconfig index 02c30d70d..0014ac15c 100644 --- a/drivers/pin/fgpio/Kconfig +++ b/drivers/pin/fgpio/Kconfig @@ -4,4 +4,4 @@ config ENABLE_FGPIO prompt "Use FGPIO" default n - + \ No newline at end of file diff --git a/drivers/pin/fgpio/fgpio.c b/drivers/pin/fgpio/fgpio.c index 8e3557589..56ae361d7 100644 --- a/drivers/pin/fgpio/fgpio.c +++ b/drivers/pin/fgpio/fgpio.c @@ -21,6 +21,7 @@ * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/3/1 init commit * 2.0 zhugengyu 2022/7/1 support e2000 + * 3.0 zhugengyu 2024/5/7 modify interface to use gpio by pin */ @@ -49,14 +50,14 @@ /*****************************************************************************/ /** * @name: FGpioCfgInitialize - * @msg: 初始化GPIO控制器实例 + * @msg: 初始化GPIO引脚实例 * @return {FError} FGPIO_SUCCESS 表示初始化成功 - * @param {FGpio} *instance, GPIO控制器实例 - * @param {FGpioConfig} *config, GPIO控制器配置 + * @param {FGpio} *pin, GPIO引脚实例 + * @param {FGpioConfig} *config, GPIO引脚配置 */ -FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config) +FError FGpioCfgInitialize(FGpio *const pin, const FGpioConfig *const config) { - FASSERT(instance && config); + FASSERT(pin && config); if (0 == config->base_addr) { @@ -64,165 +65,68 @@ FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config return FGPIO_ERR_INVALID_PARA; } - if (config != &instance->config) - { - instance->config = *config; - } - - /* mask interrupt for all pins */ - FGpioWriteReg32(instance->config.base_addr, FGPIO_INTMASK_OFFSET, FGPIO_INTR_PORTA_MASKALL); - - instance->is_ready = FT_COMPONENT_IS_READY; - return FGPIO_SUCCESS; -} - -/** - * @name: FGpioDeInitialize - * @msg: 去初始化GPIO控制器实例 - * @return {*} - * @param {FGpio} *instance, GPIO控制器实例 - */ -void FGpioDeInitialize(FGpio *const instance) -{ - FASSERT(instance); - u32 port_id; - u32 pin_id; - FGpioPin *pin = NULL; - - for (port_id = FGPIO_PORT_A; port_id < FGPIO_PORT_NUM; port_id++) - { - for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++) - { - pin = instance->pins[port_id][pin_id]; - if (NULL != pin) - { - FGpioPinDeInitialize(pin); - } - } - } - - instance->is_ready = 0; - return; -} - -/** - * @name: FGpioPinInitialize - * @msg: 初始化GPIO引脚实例 - * @return {FError} FGPIO_SUCCESS 表示初始化成功 - * @param {FGpio} *instance, GPIO控制器实例 - * @param {FGpioPin} *pin_instance, GPIO引脚实例 - * @param {FGpioPinId} index, GPIO引脚索引 - */ -FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin_instance, - const FGpioPinId index) -{ - FASSERT(instance && pin_instance); - FASSERT_MSG(index.port < FGPIO_PORT_NUM, "Invalid gpio port %d", index.port); - FASSERT_MSG(index.pin < FGPIO_PIN_NUM, "Invalid gpio pin %d", index.pin); - - if (FT_COMPONENT_IS_READY != instance->is_ready) + if (config != &pin->config) { - FGPIO_ERROR("gpio instance is not yet inited !!!"); - return FGPIO_ERR_NOT_INIT; + pin->config = *config; } - if (FT_COMPONENT_IS_READY == pin_instance->is_ready) - { - FGPIO_ERROR("gpio pin already inited !!!"); - return FGPIO_ERR_ALREADY_INIT; - } + pin->is_ready = FT_COMPONENT_IS_READY; - pin_instance->index = index; - instance->pins[index.port][index.pin] = pin_instance; - pin_instance->instance = instance; - pin_instance->irq_cb = NULL; - pin_instance->irq_cb_params = NULL; - pin_instance->irq_one_time = FALSE; - pin_instance->is_ready = FT_COMPONENT_IS_READY; + /* deregister interrupt callback */ + FGpioRegisterInterruptCB(pin, NULL, NULL); + /* disable interrupt*/ + FGpioSetInterruptMask(pin, FALSE); + +#ifdef FGPIO_PORT_B + FGPIO_INFO("GPIO %d-%d-%d inited", pin->config.ctrl, pin->config.port, pin->config.pin); +#else + FGPIO_INFO("GPIO %d-%d inited", pin->config.ctrl, pin->config.pin); +#endif return FGPIO_SUCCESS; } /** - * @name: FGpioPinDeInitialize + * @name: FGpioDeInitialize * @msg: 去初始化GPIO引脚实例 - * @return {NONE} - * @param {FGpioPin} *pin, GPIO引脚实例 + * @return {*} + * @param {FGpio} *pin, GPIO引脚实例 */ -void FGpioPinDeInitialize(FGpioPin *const pin) +void FGpioDeInitialize(FGpio *const pin) { FASSERT(pin); - FGpio *const instance = pin->instance; - if ((NULL == instance) || (FT_COMPONENT_IS_READY != instance->is_ready) || - (FT_COMPONENT_IS_READY != pin->is_ready)) - { - FGPIO_ERROR("gpio instance is not yet inited !!!"); - return; - } - - if (FGPIO_DIR_INPUT == FGpioGetDirection(pin)) - { - FGpioSetInterruptMask(pin, FALSE); /* 关闭引脚中断 */ - } - - FGpioPinId index = pin->index; - FASSERT_MSG(instance->pins[index.port][index.pin] == pin, "invalid pin instance"); - instance->pins[index.port][index.pin] = NULL; - pin->instance = NULL; - pin->is_ready = 0U; + /* 关闭引脚中断 */ + FGpioSetInterruptMask(pin, FALSE); + pin->is_ready = 0; return; } -/** - * @name: FGpioGetPinIrqSourceType - * @msg: 获取引脚中断的上报方式 - * @return {FGpioIrqSourceType} 引脚中断的上报方式 - * @param {FGpioPin} *pin, GPIO引脚实例 - */ -FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin pin_id) -{ - if(FGPIO_PORT_A == pin_id.index.port) - { - if (pin_id.instance->config.caps & FGPIO_CAPACITY_IRQ_TYPE) - { - return FGPIO_IRQ_BY_PIN; - } - else - { - return FGPIO_IRQ_BY_CONTROLLER; - } - } - /* port b not support interrupt */ - return FGPIO_IRQ_NOT_SUPPORT; -} - /** * @name: FGpioReadRegDir * @msg: 从寄存器读取GPIO组的输入输出方向 * @return {u32} GPIO组的输入输出方向, bit[8:0]有效 - * @param {uintptr} base_addr, GPIO控制器基地址 + * @param {FGpio} *pin, GPIO引脚实例 * @param {FGpioPortIndex} port, GPIO组, A/B */ -static u32 FGpioReadRegDir(uintptr base_addr, const FGpioPortIndex port) +static inline u32 FGpioReadRegDir(FGpio *const pin) { u32 reg_val = 0; + uintptr base_addr = pin->config.base_addr; - if (FGPIO_PORT_A == port) +#ifdef FGPIO_PORT_A + if (pin->config.port == FGPIO_PORT_A) { reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTA_DDR_OFFSET); } -#if defined(FGPIO_PORT_A_B_TYPE) - else if (FGPIO_PORT_B == port) +#endif +#ifdef FGPIO_PORT_B + if (pin->config.port == FGPIO_PORT_B) { reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTB_DDR_OFFSET); } #endif - else - { - FASSERT(0); - } return reg_val; } @@ -231,26 +135,26 @@ static u32 FGpioReadRegDir(uintptr base_addr, const FGpioPortIndex port) * @name: FGpioWriteRegDir * @msg: 向寄存器写入GPIO组的输入输出方向 * @return {*} - * @param {uintptr} base_addr, GPIO控制器基地址 + * @param {FGpio} *pin, GPIO引脚实例 * @param {FGpioPortIndex} port, GPIO组, A/B * @param {u32} reg_val, GPIO组的输入输出方向, bit[8:0]有效 */ -static void FGpioWriteRegDir(uintptr base_addr, const FGpioPortIndex port, const u32 reg_val) +static inline void FGpioWriteRegDir(FGpio *const pin, const u32 reg_val) { - if (FGPIO_PORT_A == port) + uintptr base_addr = pin->config.base_addr; + +#ifdef FGPIO_PORT_A + if (pin->config.port == FGPIO_PORT_A) { FGpioWriteReg32(base_addr, FGPIO_SWPORTA_DDR_OFFSET, reg_val); } -#if defined(FGPIO_PORT_A_B_TYPE) - else if (FGPIO_PORT_B == port) +#endif +#ifdef FGPIO_PORT_B + if (pin->config.port == FGPIO_PORT_B) { FGpioWriteReg32(base_addr, FGPIO_SWPORTB_DDR_OFFSET, reg_val); } -#endif - else - { - FASSERT(0); - } +#endif return; } @@ -259,36 +163,32 @@ static void FGpioWriteRegDir(uintptr base_addr, const FGpioPortIndex port, const * @name: FGpioSetDirection * @msg: 设置GPIO引脚的输入输出方向 * @return {*} - * @param {FGpioPin} *instance, GPIO控制器实例 + * @param {FGpio} *pin, GPIO引脚实例 * @param {FGpioDirection} dir, 待设置的GPIO的方向 * @note 初始化 GPIO 实例后使用此函数 */ -void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir) +void FGpioSetDirection(FGpio *const pin, FGpioDirection dir) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); u32 reg_val; - FGpioPinId index = pin->index; - uintptr base_addr = instance->config.base_addr; - reg_val = FGpioReadRegDir(base_addr, index.port); + reg_val = FGpioReadRegDir(pin); if (FGPIO_DIR_INPUT == dir) { - reg_val &= ~BIT(index.pin); /* 0-Input */ + reg_val &= ~BIT(pin->config.pin); /* 0-Input */ } else if (FGPIO_DIR_OUTPUT == dir) { - reg_val |= BIT(index.pin); /* 1-Output */ + reg_val |= BIT(pin->config.pin); /* 1-Output */ } else { FASSERT(0); } - FGpioWriteRegDir(base_addr, index.port, reg_val); + FGpioWriteRegDir(pin, reg_val); return; } @@ -296,50 +196,42 @@ void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir) * @name: FGpioGetDirection * @msg: 获取GPIO引脚的输入输出方向 * @return {FGpioDirection} GPIO引脚方向 - * @param {FGpioPin} *pin, GPIO引脚实例 + * @param {FGpio} *pin, GPIO引脚实例 * @note 初始化 GPIO 实例后使用此函数 */ -FGpioDirection FGpioGetDirection(FGpioPin *const pin) +FGpioDirection FGpioGetDirection(FGpio *const pin) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - - FGpioPinId index = pin->index; - uintptr base_addr = instance->config.base_addr; - u32 reg_val = FGpioReadRegDir(base_addr, index.port); - - return (BIT(index.pin) & reg_val) ? FGPIO_DIR_OUTPUT : FGPIO_DIR_INPUT; + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + u32 reg_val = FGpioReadRegDir(pin); + return (BIT(pin->config.pin) & reg_val) ? FGPIO_DIR_OUTPUT : FGPIO_DIR_INPUT; } /** * @name: FGpioReadRegVal * @msg: 获取GPIO组的输出寄存器值 * @return {u32} 输出寄存器值 bit[8:0]有效 - * @param {uintptr} base_addr, GPIO控制器基地址 - * @param {FGpioPortIndex} port, GPIO组 + * @param {FGpio} pin, GPIO引脚实例 */ -static u32 FGpioReadRegVal(uintptr base_addr, const FGpioPortIndex port) +static inline u32 FGpioReadRegVal(FGpio *const pin) { u32 reg_val = 0; + uintptr base_addr = pin->config.base_addr; - if (FGPIO_PORT_A == port) +#ifdef FGPIO_PORT_A + if (pin->config.port == FGPIO_PORT_A) { reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTA_DR_OFFSET); } -#if defined(FGPIO_PORT_A_B_TYPE) - else if (FGPIO_PORT_B == port) +#endif +#ifdef FGPIO_PORT_B + if (pin->config.port == FGPIO_PORT_B) { reg_val = FGpioReadReg32(base_addr, FGPIO_SWPORTB_DR_OFFSET); } #endif - else - { - FASSERT(0); - } - return reg_val; + return reg_val; } /** @@ -347,46 +239,70 @@ static u32 FGpioReadRegVal(uintptr base_addr, const FGpioPortIndex port) * @msg: 设置GPIO组的输出寄存器值 * @return {*} * @param {uintptr} base_addr, GPIO控制器基地址 - * @param {FGpioPortIndex} port, GPIO组 - * @param {u32} reg_val, 输出寄存器值 bit[8:0]有效 + * @param {FGpio} pin, GPIO引脚实例 + * @param {u32} reg_val, 输出寄存器值有效 */ -void FGpioWriteRegVal(uintptr base_addr, const FGpioPortIndex port, const u32 reg_val) +static inline void FGpioWriteRegVal(FGpio *const pin, const u32 reg_val) { - if (FGPIO_PORT_A == port) + uintptr base_addr = pin->config.base_addr; + +#ifdef FGPIO_PORT_A + if (pin->config.port == FGPIO_PORT_A) { FGpioWriteReg32(base_addr, FGPIO_SWPORTA_DR_OFFSET, reg_val); } -#if defined(FGPIO_PORT_A_B_TYPE) - else if (FGPIO_PORT_B == port) +#endif +#ifdef FGPIO_PORT_B + if (pin->config.port == FGPIO_PORT_B) { FGpioWriteReg32(base_addr, FGPIO_SWPORTB_DR_OFFSET, reg_val); } #endif - else + + return; +} + +/** + * @name: FGpioReadRegInput + * @msg: 获取GPIO引脚输入寄存器值 + * @return {*} + * @param {FGpio} pin, GPIO引脚实例 + * @param {u32} reg_val, 输出寄存器值有效 + */ +static inline u32 FGpioReadRegInput(FGpio *const pin) +{ + u32 reg_val = 0; + uintptr base_addr = pin->config.base_addr; + +#ifdef FGPIO_PORT_A + if (pin->config.port == FGPIO_PORT_A) { - FASSERT(0); + reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTA_OFFSET); } +#endif +#ifdef FGPIO_PORT_B + if (pin->config.port == FGPIO_PORT_B) + { + reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTB_OFFSET); + } +#endif - return; + return reg_val; } /** * @name: FGpioSetOutputValue * @msg: 设置GPIO引脚的输出值 * @return {FError} FGPIO_SUCCESS 表示设置成功 - * @param {FGpioPin} *pin, GPIO引脚实例 - * @param {FGpioPinVal} output, GPIO引脚的输出值 + * @param {FGpio} *pin, GPIO引脚实例 + * @param {FGpioVal} output, GPIO引脚的输出值 * @note 初始化 GPIO 实例后使用此函数，先设置 GPIO 引脚为输出后调用此函数 */ -FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output) +FError FGpioSetOutputValue(FGpio *const pin, const FGpioVal output) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT_MSG(instance->is_ready == FT_COMPONENT_IS_READY, "gpio instance is not yet inited !!!"); + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); - FGpioPinId index = pin->index; - uintptr base_addr = instance->config.base_addr; u32 reg_val; if (FGPIO_DIR_OUTPUT != FGpioGetDirection(pin)) @@ -395,15 +311,14 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output) return FGPIO_ERR_INVALID_STATE; } - FGPIO_INFO("pin-%d at port %d", index.pin, index.port); - reg_val = FGpioReadRegVal(base_addr, index.port); + reg_val = FGpioReadRegVal(pin); if (FGPIO_PIN_LOW == output) { - reg_val &= ~BIT(index.pin); + reg_val &= ~BIT(pin->config.pin); } else if (FGPIO_PIN_HIGH == output) { - reg_val |= BIT(index.pin); + reg_val |= BIT(pin->config.pin); } else { @@ -411,27 +326,24 @@ FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output) } FGPIO_INFO("Output val 0x%x", reg_val); - FGpioWriteRegVal(base_addr, index.port, reg_val); - FGPIO_INFO("Output val 0x%x", FGpioReadRegVal(base_addr, index.port)); - return FGPIO_SUCCESS; + FGpioWriteRegVal(pin, reg_val); + FGPIO_INFO("Output val 0x%x", FGpioReadRegVal(pin)); + return FGPIO_SUCCESS; } /** * @name: FGpioGetInputValue * @msg: 获取GPIO引脚的输入值 - * @return {FGpioPinVal} 获取的输入值，高电平/低电平 - * @param {FGpioPin} *instance, GPIO引脚实例 + * @return {FGpioVal} 获取的输入值，高电平/低电平 + * @param {FGpio} *instance, GPIO引脚实例 * @note 初始化 GPIO 实例后使用此函数，先设置 GPIO 引脚为输入后调用此函数 */ -FGpioPinVal FGpioGetInputValue(FGpioPin *const pin) +FGpioVal FGpioGetInputValue(FGpio *const pin) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - FGpioPinId index = pin->index; - uintptr base_addr = instance->config.base_addr; - u32 reg_val = 0; + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + + u32 reg_val; if (FGPIO_DIR_INPUT != FGpioGetDirection(pin)) { @@ -439,21 +351,8 @@ FGpioPinVal FGpioGetInputValue(FGpioPin *const pin) return FGPIO_PIN_LOW; } - if (FGPIO_PORT_A == index.port) - { - reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTA_OFFSET); - } -#if defined(FGPIO_PORT_A_B_TYPE) - else if (FGPIO_PORT_B == index.port) - { - reg_val = FGpioReadReg32(base_addr, FGPIO_EXT_PORTB_OFFSET); - } -#endif - else - { - FASSERT(0); - } + reg_val = FGpioReadRegInput(pin); FGPIO_INFO("Input val: 0x%x.", reg_val); - return (BIT(index.pin) & reg_val) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW; + return (BIT(pin->config.pin) & reg_val) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW; } \ No newline at end of file diff --git a/drivers/pin/fgpio/fgpio.h b/drivers/pin/fgpio/fgpio.h index da38cf36a..f17b24800 100644 --- a/drivers/pin/fgpio/fgpio.h +++ b/drivers/pin/fgpio/fgpio.h @@ -21,6 +21,7 @@ * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/3/1 init commit * 2.0 zhugengyu 2022/7/1 support e2000 + * 3.0 zhugengyu 2024/5/7 modify interface to use gpio by pin */ @@ -41,40 +42,6 @@ extern "C" #define FGPIO_SUCCESS FT_SUCCESS #define FGPIO_ERR_INVALID_PARA FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x0) #define FGPIO_ERR_INVALID_STATE FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x1) -#define FGPIO_ERR_NOT_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x2) -#define FGPIO_ERR_ALREADY_INIT FT_MAKE_ERRCODE(ErrModBsp, ErrBspGpio, 0x3) - -typedef enum -{ - FGPIO_PORT_A = 0, -#if defined(FGPIO_PORT_A_B_TYPE) - FGPIO_PORT_B, -#endif - FGPIO_PORT_NUM -} FGpioPortIndex; /* GPIO引脚所在的组 */ - -typedef enum -{ - FGPIO_PIN_0 = 0, - FGPIO_PIN_1, - FGPIO_PIN_2, - FGPIO_PIN_3, - FGPIO_PIN_4, - FGPIO_PIN_5, - FGPIO_PIN_6, - FGPIO_PIN_7, -#if !defined (FGPIO_PORT_A_B_TYPE) - FGPIO_PIN_8, - FGPIO_PIN_9, - FGPIO_PIN_10, - FGPIO_PIN_11, - FGPIO_PIN_12, - FGPIO_PIN_13, - FGPIO_PIN_14, - FGPIO_PIN_15, -#endif - FGPIO_PIN_NUM -} FGpioPinIndex; /* GPIO引脚号 */ typedef enum { @@ -90,117 +57,78 @@ typedef enum FGPIO_IRQ_TYPE_LEVEL_HIGH /* 高电平中断，引脚电平为高时触发 */ } FGpioIrqType; /* GPIO引脚中断类型 */ -typedef enum -{ - FGPIO_IRQ_NOT_SUPPORT = 0, /* 不支持引脚中断 */ - FGPIO_IRQ_BY_CONTROLLER, /* 引脚中断控制器合并上报 */ - FGPIO_IRQ_BY_PIN /* 引脚中断单独上报 */ -} FGpioIrqSourceType; - typedef enum { FGPIO_PIN_LOW = 0, /* 低电平 */ FGPIO_PIN_HIGH /* 高电平 */ -} FGpioPinVal; /* GPIO引脚电平类型 */ - -/**************************** Type Definitions *******************************/ -typedef struct _FGpioPin FGpioPin; -typedef struct _FGpio FGpio; +} FGpioVal; /* GPIO引脚电平类型 */ typedef struct { - u32 instance_id; /* GPIO实例ID */ - uintptr base_addr; /* GPIO控制器基地址 */ - u32 irq_num[FGPIO_PIN_NUM]; /* GPIO各引脚的中断号，如果是控制器中断，则数组所有值一致 */ - u32 irq_priority; /* 中断优先级 */ - u32 caps; -} FGpioConfig; /* GPIO控制器配置 */ - -typedef struct -{ - u32 ctrl; /* GPIO控制器号 */ - FGpioPortIndex port; /* GPIO引脚所在的组 */ - FGpioPinIndex pin; /* GPIO引脚号 */ -} FGpioPinId; /* GPIO引脚索引 */ + u32 id; /* GPIO标号，0 ~ FGPIO_NUM */ + u32 ctrl; /* GPIO所属的控制器，0 ~ FGPIO_CTRL_NUM */ + u32 port; /* GPIO所属的Port, Port A, B */ + u32 pin; /* GPIO的引脚号，0 ~ FGPIO_PIN_NUM */ + uintptr base_addr; /* GPIO控制器基地址 */ + u32 irq_num; /* GPIO中断号，如果不支持中断，置位为 0 */ + u32 cap; /* GPIO引脚能力集 */ +} FGpioConfig; /* GPIO引脚配置 */ typedef void (*FGpioInterruptCallback)(s32 vector, void *param); /* GPIO引脚中断回调函数类型 */ -typedef struct _FGpioPin -{ - FGpioPinId index; /* 索引 */ - u32 is_ready; - FGpio *instance; - FGpioInterruptCallback irq_cb; /* 中断回调函数, Port-A有效 */ - void *irq_cb_params; /* 中断回调函数的入参, Port-A有效 */ - boolean irq_one_time; /* Port-A有效, TRUE: 进入中断后关闭该引脚的中断，用于电平敏感中断，防止一直进入中断 */ -} FGpioPin; /* GPIO引脚实例 */ - -typedef struct _FGpio +typedef struct { FGpioConfig config; u32 is_ready; - FGpioPin *pins[FGPIO_PORT_NUM][FGPIO_PIN_NUM]; -} FGpio; /* GPIO控制器实例 */ +} FGpio; /* GPIO引脚实例 */ -/************************** Variable Definitions *****************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ -/* 生成GPIO引脚索引 */ -#define FGPIO_PIN(port, pin) \ - (FGpioPinId) { \ - (port), (pin) \ - } +typedef struct +{ + uintptr base_addr; /* 引脚所在控制器的基地址 */ + FGpioInterruptCallback irq_cbs[FGPIO_PIN_NUM * FGPIO_PORT_NUM]; /* 引脚中断回调 */ + void *irq_cb_params[FGPIO_PIN_NUM * FGPIO_PORT_NUM]; /* 引脚中断回调参数 */ +} FGpioIntrMap; /* GPIO中断索引表，用于多个引脚共用一个中断号的中断处理 */ /************************** Function Prototypes ******************************/ -/* 获取GPIO控制器的默认配置 */ -const FGpioConfig *FGpioLookupConfig(u32 instance_id); - -/* 初始化GPIO控制器实例 */ -FError FGpioCfgInitialize(FGpio *const instance, const FGpioConfig *const config); +/* 获取GPIO引脚的默认配置 */ +const FGpioConfig *FGpioLookupConfig(u32 gpio_id); /* 初始化GPIO引脚实例 */ -FError FGpioPinInitialize(FGpio *const instance, FGpioPin *const pin, - const FGpioPinId pin_id); +FError FGpioCfgInitialize(FGpio *const pin, const FGpioConfig *const config); /* 去初始化GPIO引脚实例 */ -void FGpioPinDeInitialize(FGpioPin *const pin); - -/* 获取引脚中断的上报方式 */ -FGpioIrqSourceType FGpioGetPinIrqSourceType(FGpioPin pin_id); - -/* 去初始化GPIO控制器实例 */ -void FGpioDeInitialize(FGpio *const instance); +void FGpioDeInitialize(FGpio *const pin); /* 设置GPIO引脚的输入输出方向 */ -void FGpioSetDirection(FGpioPin *const pin, FGpioDirection dir); +void FGpioSetDirection(FGpio *const pin, FGpioDirection dir); /* 获取GPIO引脚的输入输出方向 */ -FGpioDirection FGpioGetDirection(FGpioPin *const pin); +FGpioDirection FGpioGetDirection(FGpio *const pin); /* 设置GPIO引脚的输出值 */ -FError FGpioSetOutputValue(FGpioPin *const pin, const FGpioPinVal output); +FError FGpioSetOutputValue(FGpio *const pin, const FGpioVal output); /* 获取GPIO引脚的输入值 */ -FGpioPinVal FGpioGetInputValue(FGpioPin *const pin); +FGpioVal FGpioGetInputValue(FGpio *const pin); -/* 获取GPIO A组引脚的中断屏蔽位 */ -void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled); +/* 获取GPIO引脚的中断屏蔽位 */ +void FGpioGetInterruptMask(FGpio *const pin, u32 *mask, u32 *enabled); -/* 设置GPIO A组引脚的中断屏蔽位 */ -void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable); +/* 设置GPIO 引脚的中断屏蔽位 */ +void FGpioSetInterruptMask(FGpio *const pin, boolean enable); -/* 获取GPIO A组引脚的中断类型和中断极性 */ -void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity); +/* 获取GPIO 引脚的中断类型和中断极性 */ +void FGpioGetInterruptType(FGpio *const pin, FGpioIrqType *type); -/* 设置GPIO A组引脚的中断类型 */ -void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type); +/* 设置GPIO 引脚的中断类型 */ +void FGpioSetInterruptType(FGpio *const pin, const FGpioIrqType type); -/* GPIO控制器中断处理函数 */ +/* GPIO 引脚中断处理函数 */ void FGpioInterruptHandler(s32 vector, void *param); -/* 注册GPIO A组引脚中断回调函数 */ -void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb, - void *cb_param, boolean irq_one_time); +/* 注册GPIO引脚中断回调函数(引脚通过控制器统一上报中断，共用中断号) */ +void FGpioRegisterInterruptCB(FGpio *const pin, FGpioInterruptCallback cb, + void *cb_param); /* 打印GPIO控制寄存器信息 */ void FGpioDumpRegisters(uintptr base_addr); diff --git a/drivers/pin/fgpio/fgpio_g.c b/drivers/pin/fgpio/fgpio_g.c deleted file mode 100644 index 771541e44..000000000 --- a/drivers/pin/fgpio/fgpio_g.c +++ /dev/null @@ -1,96 +0,0 @@ -/* - * Copyright : (C) 2022 Phytium Information Technology, Inc. - * All Rights Reserved. - * - * This program is OPEN SOURCE software: you can redistribute it and/or modify it - * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, - * either version 1.0 of the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; - * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * See the Phytium Public License for more details. - * - * - * FilePath: fgpio_g.c - * Date: 2022-02-10 14:53:42 - * LastEditTime: 2022-02-18 08:25:29 - * Description:  This files is for GPIO static configuration implementation - * - * Modify History: - * Ver   Who        Date         Changes - * ----- ------     --------    -------------------------------------- - * 1.0 zhugengyu 2022/3/1 init commit - * 2.0 zhugengyu 2022/7/1 support e2000 - */ - - -/***************************** Include Files *********************************/ -#include "fparameters.h" - -#include "fgpio_hw.h" -#include "fgpio.h" - -/************************** Constant Definitions *****************************/ - -/**************************** Type Definitions *******************************/ - -/***************** Macros (Inline Functions) Definitions *********************/ - -/************************** Function Prototypes ******************************/ - -/************************** Variable Definitions *****************************/ - -/*****************************************************************************/ -const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = -{ - [FGPIO0_ID] = - { - .instance_id = FGPIO0_ID, - .base_addr = FGPIO0_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO0_CAPACITY - }, - [FGPIO1_ID] = - { - .instance_id = FGPIO1_ID, - .base_addr = FGPIO1_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO1_CAPACITY - }, -#if defined(FGPIO2_ID) - [FGPIO2_ID] = - { - .instance_id = FGPIO2_ID, - .base_addr = FGPIO2_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO2_CAPACITY - }, -#endif -#if defined(FGPIO3_ID) - [FGPIO3_ID] = - { - .instance_id = FGPIO3_ID, - .base_addr = FGPIO3_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO3_CAPACITY - }, -#endif -#if defined(FGPIO4_ID) - [FGPIO4_ID] = - { - .instance_id = FGPIO4_ID, - .base_addr = FGPIO4_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO4_CAPACITY - }, -#endif -#if defined(FGPIO5_ID) - [FGPIO5_ID] = - { - .instance_id = FGPIO5_ID, - .base_addr = FGPIO5_BASE_ADDR, - .irq_priority = 0, - .caps = FGPIO5_CAPACITY - } -#endif -}; diff --git a/drivers/pin/fgpio/fgpio_hw.h b/drivers/pin/fgpio/fgpio_hw.h index 31f0bca9e..303358dcd 100644 --- a/drivers/pin/fgpio/fgpio_hw.h +++ b/drivers/pin/fgpio/fgpio_hw.h @@ -48,11 +48,9 @@ extern "C" #define FGPIO_SWPORTA_DDR_OFFSET 0x04 /* WR Port A Data Direction Register */ #define FGPIO_EXT_PORTA_OFFSET 0x08 /* RO Port A Input Data Register */ -#if defined(FGPIO_PORT_A_B_TYPE) #define FGPIO_SWPORTB_DR_OFFSET 0x0c /* WR Port B Output Data Register */ #define FGPIO_SWPORTB_DDR_OFFSET 0x10 /* WR Port B Data Direction Register */ #define FGPIO_EXT_PORTB_OFFSET 0x14 /* RO Port B Input Data Register */ -#endif #define FGPIO_INTEN_OFFSET 0x18 /* WR Port A Interrput Enable Register */ #define FGPIO_INTMASK_OFFSET 0x1c /* WR Port A Interrupt Mask Register */ @@ -64,41 +62,44 @@ extern "C" #define FGPIO_DEBOUNCE_OFFSET 0x34 /* WR Debounce Enable Register */ #define FGPIO_PORTA_EOI_OFFSET 0x38 /* WO Port A Clear Interrupt Register */ +/* Valid bits for each port registers, e.g 7, 15 */ +#define FGPIO_PIN_MSB (FGPIO_PIN_NUM - 1) + /** @name FGPIO_SWPORTA_DR_OFFSET Register */ -#define FGPIO_SWPORTA_DR_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_SWPORTA_DR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_SWPORTA_DR_MASK GENMASK(7, 0) +#define FGPIO_SWPORTA_DR_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTA_DR_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTA_DR_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_SWPORTA_DDR_OFFSET Register */ -#define FGPIO_SWPORTA_DDR_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_SWPORTA_DDR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_SWPORTA_DDR_MASK GENMASK(7, 0) +#define FGPIO_SWPORTA_DDR_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTA_DDR_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTA_DDR_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_EXT_PORTA_OFFSET Register */ -#define FGPIO_EXT_PORTA_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_EXT_PORTA_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_EXT_PORTA_MASK GENMASK(7, 0) +#define FGPIO_EXT_PORTA_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_EXT_PORTA_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_EXT_PORTA_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_SWPORTB_DR_OFFSET Register */ -#define FGPIO_SWPORTB_DR_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_SWPORTB_DR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_SWPORTB_DR_MASK GENMASK(7, 0) +#define FGPIO_SWPORTB_DR_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTB_DR_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTB_DR_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_SWPORTB_DDR_OFFSET Register */ -#define FGPIO_SWPORTB_DDR_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_SWPORTB_DDR_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_SWPORTB_DDR_MASK GENMASK(7, 0) +#define FGPIO_SWPORTB_DDR_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTB_DDR_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_SWPORTB_DDR_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_EXT_PORTB_OFFSET Register */ -#define FGPIO_EXT_PORTB_SET(dir) SET_REG32_BITS((dir), 7, 0) -#define FGPIO_EXT_PORTB_GET(reg_val) GET_REG32_BITS((reg_val), 7, 0) -#define FGPIO_EXT_PORTB_MASK GENMASK(7, 0) +#define FGPIO_EXT_PORTB_SET(dir) SET_REG32_BITS((dir), FGPIO_PIN_MSB, 0) +#define FGPIO_EXT_PORTB_GET(reg_val) GET_REG32_BITS((reg_val), FGPIO_PIN_MSB, 0) +#define FGPIO_EXT_PORTB_MASK GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_INTEN_OFFSET Register */ @@ -107,7 +108,7 @@ extern "C" /** @name FGPIO_INTMASK_OFFSET Register */ #define FGPIO_INTR_PORTA_MASK(n) BIT(n) /* 1: disable the intr of n-th port in group-a */ -#define FGPIO_INTR_PORTA_MASKALL GENMASK(15, 0) +#define FGPIO_INTR_PORTA_MASKALL GENMASK(FGPIO_PIN_MSB, 0) /** @name FGPIO_INTTYPE_LEVEL_OFFSET Register */ @@ -129,13 +130,6 @@ extern "C" */ #define FGPIO_PCLK_INTR_SYNC(n) BIT(n) /* 1: sync to pclk_intr */ -/** @name FGPIO_DEBOUNCE_OFFSET Register - */ -#define FGPIO_DEBOUNCE_CLK_CONFIG_SET(clk) SET_REG32_BITS((clk), 15, 7) -#define FGPIO_DEBOUNCE_CLK_CONFIG_GET(reg_val) GET_REG32_BITS((reg_val), 15, 7) -#define FGPIO_DEBOUNCE_CLK_CONFIG_MASK GENMASK(15, 7) -#define FGPIO_DEBOUNCE_EN(n) BIT(n) /* 1: enable debounce */ - /** @name FGPIO_PORTA_EOI_OFFSET Register */ #define FGPIO_CLR_INTR_PORTA(n) BIT(n) /* 1: clear interrupt */ diff --git a/drivers/pin/fgpio/fgpio_intr.c b/drivers/pin/fgpio/fgpio_intr.c index 126edc3c2..a9904465f 100644 --- a/drivers/pin/fgpio/fgpio_intr.c +++ b/drivers/pin/fgpio/fgpio_intr.c @@ -21,6 +21,7 @@ * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/3/1 init commit * 2.0 zhugengyu 2022/7/1 support e2000 + * 3.0 zhugengyu 2024/5/7 modify interface to use gpio by pin */ @@ -43,33 +44,37 @@ #define FGPIO_DEBUG(format, ...) FT_DEBUG_PRINT_D(FGPIO_DEBUG_TAG, format, ##__VA_ARGS__) /************************** Function Prototypes ******************************/ +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num); /************************** Variable Definitions *****************************/ +extern FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM]; /*****************************************************************************/ /** * @name: FGpioGetInterruptMask - * @msg: 获取GPIO A组引脚的中断屏蔽位 + * @msg: 获取GPIO 引脚的中断屏蔽位 * @return {*} - * @param {FGpio} *instance, GPIO控制器实例 - * @param {u32} *mask, 返回的GPIO A组引脚中断屏蔽位 - * @param {u32} *enabled, 返回的GPIO A组中断使能位 - * @note 获取的是A组所有Pin的中断屏蔽位和中断使能位 + * @param {FGpio} *pin, GPIO引脚实例 + * @param {u32} *mask, 返回的GPIO引脚中断屏蔽位 + * @param {u32} *enabled, 返回的GPIO引脚中断使能位 */ -void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled) +void FGpioGetInterruptMask(FGpio *const pin, u32 *mask, u32 *enabled) { - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - uintptr base_addr = instance->config.base_addr; + FASSERT(pin); + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + u32 reg_val; + uintptr base_addr = pin->config.base_addr; if (NULL != mask) { - *mask = FGpioReadReg32(base_addr, FGPIO_INTMASK_OFFSET); + reg_val = FGpioReadReg32(base_addr, FGPIO_INTMASK_OFFSET); + *mask = reg_val & BIT(pin->config.pin); } if (NULL != enabled) { - *enabled = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET); + reg_val = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET); + *enabled = reg_val & BIT(pin->config.pin); } return; @@ -77,45 +82,32 @@ void FGpioGetInterruptMask(FGpio *const instance, u32 *mask, u32 *enabled) /** * @name: FGpioSetInterruptMask - * @msg: 设置GPIO A组引脚的中断屏蔽位 + * @msg: 设置GPIO引脚的中断屏蔽位 * @return {*} - * @param {FGpioPin} *pin, GPIO引脚实例 + * @param {FGpio} *pin, GPIO引脚实例 * @param {boolean} enable, TRUE表示使能GPIO引脚中断，FALSE表示去使能GPIO引脚中断 - * @note index对应的引脚必须为A组引脚，B组引脚不支持中断 + * @note 引脚必须为A组引脚，B组引脚不支持中断 */ -void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable) +void FGpioSetInterruptMask(FGpio *const pin, boolean enable) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - uintptr base_addr = instance->config.base_addr; + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + uintptr base_addr = pin->config.base_addr; u32 mask_bits = 0; u32 enable_bits = 0; - FGpioPinId index = pin->index; -#if defined(FGPIO_PORT_A_B_TYPE) - if (FGPIO_PORT_B == index.port) - { - FGPIO_ERROR("None interrupt support for PORT-B !!!"); - return; - } -#endif - if (FGPIO_DIR_OUTPUT == FGpioGetDirection(pin)) - { - FGPIO_ERROR("None interrupt support for output GPIO !!!"); - return; - } - FGpioGetInterruptMask(instance, &mask_bits, &enable_bits); + mask_bits = FGpioReadReg32(base_addr, FGPIO_INTMASK_OFFSET); + enable_bits = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET); + if (TRUE == enable) { - mask_bits &= ~BIT(index.pin); /* not mask: 0 */ - enable_bits |= BIT(index.pin); /* enable pin irq: 1 */ + mask_bits &= ~BIT(pin->config.pin); /* not mask: 0 */ + enable_bits |= BIT(pin->config.pin); /* enable pin irq: 1 */ } else { - mask_bits |= BIT(index.pin); /* mask: 1 */ - enable_bits &= ~BIT(index.pin); /* disable pin irq: 0 */ + mask_bits |= BIT(pin->config.pin); /* mask: 1 */ + enable_bits &= ~BIT(pin->config.pin); /* disable pin irq: 0 */ } FGpioWriteReg32(base_addr, FGPIO_INTMASK_OFFSET, mask_bits); @@ -126,27 +118,45 @@ void FGpioSetInterruptMask(FGpioPin *const pin, boolean enable) /** * @name: FGpioGetInterruptType - * @msg: 获取GPIO A组引脚的中断类型和中断极性 + * @msg: 获取GPIO引脚的中断类型和中断极性 * @return {*} - * @param {FGpio} *instance, GPIO控制器实例 - * @param {u32} *levels, GPIO A组引脚中断电平类型 - * @param {u32} *polarity, GPIO A组引脚中断极性类型 - * @note 获取的是A组所有Pin的电平和极性 + * @param {FGpio} *pin, GPIO引脚实例 + * @param {FGpioIrqType} *type, GPIO引脚中断触发类型 */ -void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity) +void FGpioGetInterruptType(FGpio *const pin, FGpioIrqType *type) { - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - uintptr base_addr = instance->config.base_addr; + FASSERT(pin && type); + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + uintptr base_addr = pin->config.base_addr; + u32 pin_num = pin->config.pin; + u32 levels; + u32 polarity; - if (NULL != levels) + if (pin->config.cap & FGPIO_CAP_IRQ_NONE) { - *levels = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET); + FGPIO_ERROR("None interrupt support for GPIO %d-%d-%d !!!", + pin->config.ctrl, pin->config.port, pin->config.pin); + return; } - if (NULL != polarity) + levels = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET); + polarity = FGpioReadReg32(base_addr, FGPIO_INT_POLARITY_OFFSET); + + if ((levels & BIT(pin_num)) && !(polarity & BIT(pin_num))) + { + *type = FGPIO_IRQ_TYPE_EDGE_FALLING; + } + else if ((levels & BIT(pin_num)) && (polarity & BIT(pin_num))) + { + *type = FGPIO_IRQ_TYPE_EDGE_RISING; + } + else if (!(levels & BIT(pin_num)) && !(polarity & BIT(pin_num))) + { + *type = FGPIO_IRQ_TYPE_LEVEL_LOW; + } + else if (!(levels & BIT(pin_num)) && (polarity & BIT(pin_num))) { - *polarity = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET); + *type = FGPIO_IRQ_TYPE_LEVEL_HIGH; } return; @@ -156,46 +166,45 @@ void FGpioGetInterruptType(FGpio *const instance, u32 *levels, u32 *polarity) * @name: FGpioSetInterruptType * @msg: 设置GPIO引脚的中断类型 * @return {*} - * @param {FGpioPin} *pin, GPIO引脚实例 + * @param {FGpio} *pin, GPIO引脚实例 * @param {FGpioIrqType} type, GPIO引脚中断触发类型 * @note index对应的引脚必须为A组引脚，B组引脚不支持中断 */ -void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type) +void FGpioSetInterruptType(FGpio *const pin, const FGpioIrqType type) { FASSERT(pin); - FGpio *const instance = pin->instance; - FASSERT(instance); - FASSERT(instance->is_ready == FT_COMPONENT_IS_READY); - uintptr base_addr = instance->config.base_addr; + FASSERT_MSG(pin->is_ready == FT_COMPONENT_IS_READY, "gpio instance not is yet inited !!!"); + uintptr base_addr = pin->config.base_addr; u32 level = 0; u32 polarity = 0; - FGpioPinId index = pin->index; -#if defined(FGPIO_PORT_A_B_TYPE) - if (FGPIO_PORT_B == index.port) + + if (pin->config.cap & FGPIO_CAP_IRQ_NONE) { - FGPIO_ERROR("None interrupt support for PORT-B !!!"); - return; + FGPIO_ERROR("None interrupt support for GPIO %d-%d-%d !!!", + pin->config.ctrl, pin->config.port, pin->config.pin); + return; } -#endif - FGpioGetInterruptType(instance, &level, &polarity); + + level = FGpioReadReg32(base_addr, FGPIO_INTTYPE_LEVEL_OFFSET); + polarity = FGpioReadReg32(base_addr, FGPIO_INT_POLARITY_OFFSET); switch (type) { case FGPIO_IRQ_TYPE_EDGE_FALLING: - level |= BIT(index.pin); /* 边沿敏感型 */ - polarity &= ~BIT(index.pin); /* 下降沿或低电平 */ + level |= BIT(pin->config.pin); /* 1, 边沿敏感型 */ + polarity &= ~BIT(pin->config.pin); /* 0, 下降沿或低电平 */ break; case FGPIO_IRQ_TYPE_EDGE_RISING: - level |= BIT(index.pin); /* 边沿敏感型 */ - polarity |= BIT(index.pin); /* 上升沿或高电平 */ + level |= BIT(pin->config.pin); /* 1, 边沿敏感型 */ + polarity |= BIT(pin->config.pin); /* 1, 上升沿或高电平 */ break; case FGPIO_IRQ_TYPE_LEVEL_LOW: - level &= ~BIT(index.pin); /* 电平敏感型 */ - polarity &= ~BIT(index.pin); /* 下降沿或低电平 */ + level &= ~BIT(pin->config.pin); /* 0, 电平敏感型 */ + polarity &= ~BIT(pin->config.pin); /* 0, 下降沿或低电平 */ break; case FGPIO_IRQ_TYPE_LEVEL_HIGH: - level &= ~BIT(index.pin); /* 电平敏感型 */ - polarity |= BIT(index.pin); /* 上升沿或高电平 */ + level &= ~BIT(pin->config.pin); /* 0, 电平敏感型 */ + polarity |= BIT(pin->config.pin); /* 1, 上升沿或高电平 */ break; default: break; @@ -208,73 +217,118 @@ void FGpioSetInterruptType(FGpioPin *const pin, const FGpioIrqType type) } /** - * @name: FGpioInterruptHandler - * @msg: GPIO中断处理函数 + * @name: FGpioCtrlInterruptHandler + * @msg: GPIO中断处理函数(引脚通过控制器统一上报中断，共用中断号) * @return {*} - * @param {s32} vector, 中断输入参数1 - * @param {void} *param, 中断输入参数2 - * @note 需要用户将此函数注册到Interrtup上，使能GPIO中断才能生效 + * @param @param {FGpio} pin, GPIO引脚 */ -void FGpioInterruptHandler(s32 vector, void *param) +static void FGpioSharedInterruptHandler(u32 ctrl_num) { - FGpio *const instance = (FGpio * const)param; - FGpioPin *pin = NULL; - FASSERT(instance); - int loop; - uintptr base_addr = instance->config.base_addr; + FGpioIntrMap *map = &fgpio_intr_map[ctrl_num]; + uintptr base_addr = map->base_addr; + FASSERT(base_addr != 0U); u32 status = FGpioReadReg32(base_addr, FGPIO_INTSTATUS_OFFSET); - u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET); + u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET); + u32 enable_bits = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET); + u32 pin_num; - FGPIO_INFO("status: 0x%x, raw_status: 0x%x.", status, raw_status); - for (loop = FGPIO_PIN_0; loop < FGPIO_PIN_NUM; loop++) + if ((raw_status == 0) || (enable_bits == 0) || ((raw_status & enable_bits) == 0)) + { + return; + } + + for (pin_num = 0; (pin_num < (FGPIO_PIN_NUM * FGPIO_PORT_NUM)); pin_num++) { - if (status & BIT(loop)) + /* skip if interrupt not enabled for this pin */ + if ((raw_status & BIT(pin_num)) && (enable_bits & BIT(pin_num))) { - pin = instance->pins[FGPIO_PORT_A][loop]; - if (NULL == pin) - { - continue; - } + /* ack interrupt */ + FGpioWriteReg32(base_addr, FGPIO_PORTA_EOI_OFFSET, BIT(pin_num)); - if (pin->irq_cb) - { - pin->irq_cb(0U, pin->irq_cb_params); - - /* disable pin interrupt after triggered */ - if (TRUE == pin->irq_one_time) - { - FGpioSetInterruptMask(pin, FALSE); - } - } - else + if (map->irq_cbs[pin_num] != NULL) { - FGPIO_WARN("No irq handler callback for GPIO-%d-A-%d.", - instance->config.instance_id, - loop); - } + map->irq_cbs[pin_num](0U, map->irq_cb_params[pin_num]); + } } } +} + +/** + * @name: FGpioPinInterruptHandler + * @msg: GPIO中断处理函数(引脚单独上报中断) + * @return {*} + * @param @param {FGpio} pin, GPIO引脚 + */ +static void FGpioPinInterruptHandler(u32 ctrl_num, u32 pin_num) +{ + FGpioIntrMap *map = &fgpio_intr_map[ctrl_num]; + uintptr base_addr = map->base_addr; + FASSERT(base_addr != 0U); + u32 status = FGpioReadReg32(base_addr, FGPIO_INTSTATUS_OFFSET); + u32 raw_status = FGpioReadReg32(base_addr, FGPIO_RAW_INTSTATUS_OFFSET); + u32 enable_bits = FGpioReadReg32(base_addr, FGPIO_INTEN_OFFSET); + + if ((raw_status == 0) || ((enable_bits & BIT(pin_num) == 0))) + { + return; + } + + /* ack interrupt */ + FGpioWriteReg32(base_addr, FGPIO_PORTA_EOI_OFFSET, BIT(pin_num)); + + if (map->irq_cbs[pin_num] != NULL) + { + map->irq_cbs[pin_num](0U, map->irq_cb_params[pin_num]); + } - /* clear interrupt status */ - FGpioWriteReg32(base_addr, FGPIO_PORTA_EOI_OFFSET, status); return; } +/** + * @name: FGpioInterruptHandler + * @msg: GPIO 引脚中断处理函数 + * @return {*} + * @param {s32} vector, 中断输入参数1 + * @param {void} *param, 中断输入参数2 + * @note 需要用户将此函数注册到Interrtup上，使能GPIO中断才能生效 + */ +void FGpioInterruptHandler(s32 vector, void *param) +{ + FGPIO_DEBUG("vector = %d\r\n", vector); + const FGpioConfig *pin_cfg = FGpioLookupConfigByIrqNum(vector); + + if (pin_cfg == NULL) + { + return; + } + else if (pin_cfg->cap & FGPIO_CAP_IRQ_BY_PIN) + { + FGpioPinInterruptHandler(pin_cfg->ctrl, pin_cfg->pin); /* 引脚独占中断处理 */ + } + else if (pin_cfg->cap & FGPIO_CAP_IRQ_BY_CTRL) + { + FGpioSharedInterruptHandler(pin_cfg->ctrl); /* 控制器所属的引脚共用中断处理 */ + } +} + /** * @name: FGpioRegisterInterruptCB - * @msg: 注册GPIO引脚中断回调函数 + * @msg: 注册GPIO引脚中断回调函数(引脚通过控制器统一上报中断，共用中断号) * @return {*} - * @param {FGpioPin} pin, GPIO引脚实例 + * @param {FGpio} pin, GPIO引脚 * @param {FGpioInterruptCallback} cb, GPIO引脚中断回调函数 * @param {void} *cb_param, GPIO引脚中断回调函数输入参数 - * @param {boolean} irq_one_time, TRUE表示引脚中断触发一次后自动关闭中断，用于电平敏感中断 * @note 注册的回调函数在FGpioInterruptHandler中被调用 */ -void FGpioRegisterInterruptCB(FGpioPin *const pin, FGpioInterruptCallback cb, void *cb_param, boolean irq_one_time) +void FGpioRegisterInterruptCB(FGpio *const pin, FGpioInterruptCallback cb, void *cb_param) { - FASSERT(pin); - pin->irq_cb = cb; - pin->irq_cb_params = cb_param; - pin->irq_one_time = irq_one_time; + FASSERT(pin && (pin->config.ctrl < FGPIO_CTRL_NUM)); + u32 ctrl_num = pin->config.ctrl; + u32 pin_num = pin->config.port * FGPIO_PIN_NUM + pin->config.pin; + FGpioIntrMap *map = &fgpio_intr_map[ctrl_num]; + + map->irq_cbs[pin_num] = cb; + map->irq_cb_params[pin_num] = cb_param; + return; } \ No newline at end of file diff --git a/drivers/pin/fgpio/fgpio_selftest.c b/drivers/pin/fgpio/fgpio_selftest.c index 6083e70bd..effb4c58a 100644 --- a/drivers/pin/fgpio/fgpio_selftest.c +++ b/drivers/pin/fgpio/fgpio_selftest.c @@ -21,6 +21,7 @@ * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/3/1 init commit * 2.0 zhugengyu 2022/7/1 support e2000 + * 3.0 zhugengyu 2024/5/7 modify interface to use gpio by pin */ /***************************** Include Files *********************************/ #include "fdrivers_port.h" @@ -62,7 +63,7 @@ void FGpioDumpRegisters(uintptr base_addr) FGPIO_DUMPER(base_addr, FGPIO_SWPORTA_DR_OFFSET, "dr"); FGPIO_DUMPER(base_addr, FGPIO_SWPORTA_DDR_OFFSET, "ddr"); FGPIO_DUMPER(base_addr, FGPIO_EXT_PORTA_OFFSET, "ext_porta"); -#if defined(FGPIO_PORT_A_B_TYPE) +#if defined(FGPIO_PORT_B) FGPIO_DUMPER(base_addr, FGPIO_SWPORTB_DR_OFFSET, "portb_dr"); FGPIO_DUMPER(base_addr, FGPIO_SWPORTB_DDR_OFFSET, "portb_ddr"); FGPIO_DUMPER(base_addr, FGPIO_EXT_PORTB_OFFSET, "ext_portb"); diff --git a/drivers/pin/fgpio/fgpio_sinit.c b/drivers/pin/fgpio/fgpio_sinit.c index c6e4791dd..683f5343c 100644 --- a/drivers/pin/fgpio/fgpio_sinit.c +++ b/drivers/pin/fgpio/fgpio_sinit.c @@ -21,6 +21,7 @@ * ----- ------     --------    -------------------------------------- * 1.0 zhugengyu 2022/3/1 init commit * 2.0 zhugengyu 2022/7/1 support e2000 + * 3.0 zhugengyu 2024/5/7 modify interface to use gpio by pin */ @@ -42,105 +43,25 @@ extern FGpioConfig fgpio_cfg_tbl[FGPIO_NUM]; /*****************************************************************************/ - - -/** - * @name: FGpioSetIrqNum - * @msg: 设置GPIO控制器各引脚的中断号 - * @return {NONE} - * @param {u32} instance_id, GPIO控制器实例号 - * @param {FGpioConfig} *ptr, GPIO控制器的默认配置 - */ -static void FGpioSetIrqNum(FGpioConfig *ptr) -{ - u32 pin_id; - u32 irq_num; - u32 instance_id = ptr->instance_id; - - if(ptr->caps & FGPIO_CAPACITY_IRQ_TYPE) - { -#define FGPIO_PIN_IRQ_NUM_GET(id, pin) (FGPIO_PIN_IRQ_BASE + FGPIO_CTRL_PIN_NUM * (id) + (pin)) - /* each pin has its own interrupt id */ - for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++) - { - ptr->irq_num[pin_id] = FGPIO_PIN_IRQ_NUM_GET(instance_id, pin_id); - } - } - else - { -#if defined(FGPIO_0_IRQ_NUM) - if (FGPIO0_ID == instance_id) - { - irq_num = FGPIO_0_IRQ_NUM; - } -#endif -#if defined(FGPIO_1_IRQ_NUM) - if (FGPIO1_ID == instance_id) - { - irq_num = FGPIO_1_IRQ_NUM; - } -#endif -#if defined(FGPIO_2_IRQ_NUM) - if (FGPIO2_ID == instance_id) - { - irq_num = FGPIO_2_IRQ_NUM; - } -#endif -#if defined(FGPIO_3_IRQ_NUM) - if (FGPIO3_ID == instance_id) - { - irq_num = FGPIO_3_IRQ_NUM; - } -#endif -#if defined(FGPIO_4_IRQ_NUM) - if (FGPIO4_ID == instance_id) - { - irq_num = FGPIO_4_IRQ_NUM; - } -#endif -#if defined(FGPIO_5_IRQ_NUM) - if (FGPIO5_ID == instance_id) - { - irq_num = FGPIO_5_IRQ_NUM; - } -#endif - /* all pins in the controller share the same interrupt id */ - for (pin_id = FGPIO_PIN_0; pin_id < FGPIO_PIN_NUM; pin_id++) - { - ptr->irq_num[pin_id] = irq_num; - } - } - - return; -} - /** * @name: FGpioLookupConfig - * @msg: 获取GPIO控制器的默认配置 - * @return {const FGpioConfig *} GPIO控制器的默认配置 - * @param {u32} instance_id, GPIO控制器实例号 + * @msg: 获取GPIO引脚的默认配置 + * @return {const FGpioConfig *} GPIO引脚的参数和默认配置 + * @param {u32} gpio_id, GPIO引脚号, 0 ~ FGPIO_NUM，可以通过宏 FGPIO_ID 获取编码 */ -const FGpioConfig *FGpioLookupConfig(u32 instance_id) +const FGpioConfig *FGpioLookupConfig(u32 gpio_id) { FGpioConfig *ptr = NULL; u32 index; - static boolean irq_num_set = FALSE; - FASSERT_MSG((instance_id < FGPIO_NUM), "Instance_id is invalid."); + FASSERT_MSG((gpio_id < FGPIO_NUM), "Instance_id is invalid."); - for (index = 0; index < FGPIO_NUM; index++) /* find configs of controller */ + for (index = 0; index < FGPIO_NUM; index++) /* find configs of GPIO */ { - if (fgpio_cfg_tbl[index].instance_id == instance_id) + if (fgpio_cfg_tbl[index].id == gpio_id) { ptr = &fgpio_cfg_tbl[index]; break; - } - } - FASSERT_MSG((index < FGPIO_NUM), "Index is invalid."); - - if (FALSE == irq_num_set) /* set irq num in the first time */ - { - FGpioSetIrqNum(ptr); - irq_num_set = TRUE; + } } return ptr; diff --git a/drivers/pin/src.mk b/drivers/pin/src.mk index 898871783..1d899f1e5 100644 --- a/drivers/pin/src.mk +++ b/drivers/pin/src.mk @@ -1,7 +1,6 @@ ifdef CONFIG_ENABLE_FGPIO DRIVERS_CSRCS += \ fgpio.c\ - fgpio_g.c\ fgpio_intr.c\ fgpio_selftest.c\ fgpio_sinit.c diff --git a/example/peripherals/pin/README.md b/example/peripherals/pin/README.md index 3644fc879..d71adbc98 100644 --- a/example/peripherals/pin/README.md +++ b/example/peripherals/pin/README.md @@ -16,13 +16,19 @@ - 本测试中短接两个 GPIO 引脚，一个作为输出，另一个为输入，通过多次改变输出引脚的电平，在输入引脚上触发中断，进行中断处理 - 本测试的主要目的就是提供外部信号给GPIO引脚，测试引脚是否能正常上报中断以及控制器是否能正常处理中断 -### 1.2 GPIO寄存器操作测试例程 (pin_gpio_low_level_example.c) +### 1.2 GPIO多路输入中断触发测试 (pin_gpio_multi_input_example.c) + +- 板上的 GPIO 引脚往往被设置了复用功能，使用前需要通过软件编程手册查阅复用设置 +- 本测试中使用两个 GPIO 引脚，都作为输入，中断触发模式设置为低电平触发，将两个输入 GPIO 引脚和板子上的 GDN (接地脚) 短接，中断使用后会 GPIO 中断会被立即触发，进行中断处理 +- 本测试的主要目的是测试多路 GPIO 引脚能够正常上报中断并进行处理 + +### 1.3 GPIO寄存器操作测试例程 (pin_gpio_low_level_example.c) - 板上的 GPIO 引脚往往被设置了复用功能，使用前需要通过软件编程手册查阅复用设置 - 本测试中短接两个 GPIO 引脚，一个作为输出，另一个为输入，多次变化输出引脚的电平，判断输入电平是否跟随变化 - 本测试的主要目的是测试对GPIO相关寄存器直接操作是否能产生对应效果 -### 1.3 GPIO脉冲宽度调制测试例程 (pin_gpio_pwm_example.c) +### 1.4 GPIO脉冲宽度调制测试例程 (pin_gpio_pwm_example.c) - 板上的 GPIO 引脚往往被设置了复用功能，使用前需要通过软件编程手册查阅复用设置 - 现有驱动可以完成对某个 GPIO 初始化、引脚上下拉、改变输出方向等操作 @@ -36,7 +42,7 @@ 本例程需要以下硬件， -- E2000D Demo 板,PhytiumPi. +- E2000D Demo 板,PhytiumPi,D2000 Test 板 - 串口线和串口上位机 - 逻辑分析仪 @@ -44,11 +50,32 @@ > ``哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）`
` +#### 2.1.1 E2000 D/Q Demo 板 + ![pin_gpio_intr_board](./figs/pin_gpio_intr_board.png) -对于GPIO中断触发测试用例（pin_gpio_intr_example）和寄存器操作测试例程 (pin_gpio_low_level_example.c)，利用杜邦线短接 GPIO 4-A-11与 GPIO 4-A-12 ,即将上图红色框内的第二排排从右往左数第 4 与第 5 个引脚用杜邦线短接。 + +对于GPIO中断触发测试用例（pin_gpio_intr_example）和寄存器操作测试例程 + +#### 2.1.2 飞腾派 + +> 如果是飞腾派，可以使用 40 针引脚中的几个 GPIO，如下图所示，连接了 GPIO 0-0 和 GPIO 4-13, 如下图所示 + +![alt text](./figs/firefly.png) + +#### 2.1.3 D2000 测试板 + +> 如果是 D2000 测试板，可以用 SPI 插槽的引脚复用成 GPIO 进行测试，使用左侧排线的最下面脚（SPI0-SO 对应 GPIO 1-A-7）和右侧排线的最上面脚（SPI0-SCK 对应 GPIO 1-A-6） + +![d2000_gpio_pin](./figs/d2000_gpio_pin.png) + +(pin_gpio_low_level_example.c)，利用杜邦线短接 GPIO 4-A-11与 GPIO 4-A-12 ,即将上图红色框内的第二排排从右往左数第 4 与第 5 个引脚用杜邦线短接。 ![pin_gpio_pwm_board](./figs/pin_gpio_pwm_board.png) 对于GPIO脉冲宽度调制测试（pin_gpio_pwm_example），需要将中断测试中使用到的两个引脚与逻辑分析仪连接。注意，逻辑分析仪需要接地（见红色杜邦线）。 +- 也可以使用其它的逻辑分析仪，比如 + +![nanodla_pwm](./figs/nanodla_pwm.jpg) + ### 2.2 SDK配置方法 > ``依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）`
` @@ -107,13 +134,54 @@ bootelf -p 0x90100000 #### 2.4.1 GPIO中断触发测试 +- 按照 2.1 硬件配置方法 进行连线 + ``` pin gpio_intr_example ``` ![pin_gpio_intr_result](./figs/pin_gpio_intr_result.png) -#### 2.4.2 GPIO寄存器操作测试 +> 对于 D2000 测试板 + +![d2000_pin_gpio_intr_result](./figs/d2000_pin_gpio_intr_result.png) + +#### 2.4.2 GPIO多路中断测试 + +- 如下图所示, 如果是 E2000 D/Q Demo 板 参考原理图将两路 GPIO 引脚接地，然后输入下列命令 + +![two_input_gpio](./figs/two_input_gpio.png) + +- 如果是飞腾派，可以按照下图联想，分别将 GPIO 4-13 GPIO 4-12 和 GPIO 0-0 接地 + +![alt text](./figs/firefly_two_gpio.png) + + +- 如果是 D2000 测试板，可以按照下面连线，用 SPI 插槽的引脚复用成 GPIO 进行测试，使用左侧排线的最下面脚（SPI0-SO 对应 GPIO 1-A-7）和右侧排线的最上面脚（SPI0-SCK 对应 GPIO 1-A-6），都连接板子上的一个 GND 脚 + +![d2000_two_gpio](./figs/d2000_two_gpio.png) + +- 连线完成后输入下面的命令 + +``` +pin gpio_multi_input_example +``` + +- 对于 E2000 D/Q Demo 板 + +![two_gpio_intr_result](./figs/two_gpio_intr_result.png) + +- 对于飞腾派 + +![firefly_two_gpio_intr_result](./figs/firefly_two_gpio_intr_result.png) + +- 对于 D2000 测试板 + +![d2000_two_gpio_intr_result](./figs/d2000_two_gpio_intr_result.png) + +#### 2.4.3 GPIO寄存器操作测试 + +- 按照 2.1 硬件配置方法 进行连线 ``` pin gpio_low_level_example @@ -121,16 +189,16 @@ pin gpio_low_level_example ![pin_gpio_low_level_result](./figs/pin_gpio_low_level_result.png) -#### 2.4.3 GPIO脉冲宽度调制测试 +#### 2.4.4 GPIO脉冲宽度调制测试 ``` pin gpio_pwm_example ``` -- 打开逻辑分析仪配套的logic软件，提前观测波形 -- 进入 shell 界面，输入上述指令，会显示如下内容： +打开逻辑分析仪配套的logic软件，提前观测波形 +进入 shell 界面，输入上述指令，会显示如下内容： ![pin_gpio_pwm_result_1](./figs/pin_gpio_pwm_result_1.png) -- 观察逻辑分析仪结果是否出现如下波形： +观察逻辑分析仪结果是否出现如下波形： ![pin_gpio_pwm_result_2](./figs/pin_gpio_pwm_result_2.png) ## 3. 如何解决问题 @@ -141,6 +209,7 @@ pin gpio_pwm_example > ``记录例程的重大修改记录，标明修改发生的版本号 `
` -v1.0.0 首次合入 -v1.1.1 支持 D2000 -v1.3.0 删除 D2000支持 +- v1.0.0 首次合入 +- v1.1.1 支持 D2000 +- v1.3.0 删除 D2000支持 +- v1.3.1 适配重构后的 GPIO 驱动接口, 支持 D2000 测试板 \ No newline at end of file diff --git a/example/peripherals/pin/configs/d2000_aarch32_test_pin.config b/example/peripherals/pin/configs/d2000_aarch32_test_pin.config new file mode 100644 index 000000000..08c42dbdc --- /dev/null +++ b/example/peripherals/pin/configs/d2000_aarch32_test_pin.config @@ -0,0 +1,235 @@ +CONFIG_USE_BAREMETAL=y + +# +# Arch configuration +# +CONFIG_TARGET_ARMv8=y +CONFIG_ARCH_NAME="armv8" + +# +# Arm architecture configuration +# +# CONFIG_ARCH_ARMV8_AARCH64 is not set +CONFIG_ARCH_ARMV8_AARCH32=y + +# +# Compiler configuration +# +CONFIG_ARM_GCC_SELECT=y +# CONFIG_ARM_CLANG_SELECT is not set +CONFIG_TOOLCHAIN_NAME="gcc" +CONFIG_TARGET_ARMV8_AARCH32=y +CONFIG_ARCH_EXECUTION_STATE="aarch32" + +# +# Fpu configuration +# +CONFIG_CRYPTO_NEON_FP_ARMV8=y +# CONFIG_VFPV4 is not set +# CONFIG_VFPV4_D16 is not set +# CONFIG_VFPV3 is not set +# CONFIG_VFPV3_D16 is not set +CONFIG_ARM_MFPU="crypto-neon-fp-armv8" +CONFIG_MFLOAT_ABI_HARD=y +# CONFIG_MFLOAT_ABI_SOFTFP is not set +CONFIG_ARM_MFLOAT_ABI="hard" +# end of Fpu configuration +# end of Compiler configuration + +CONFIG_USE_CACHE=y +# CONFIG_USE_L3CACHE is not set +CONFIG_USE_MMU=y +CONFIG_USE_AARCH64_L1_TO_AARCH32=y +# end of Arm architecture configuration +# end of Arch configuration + +# +# Soc configuration +# +# CONFIG_TARGET_PHYTIUMPI is not set +# CONFIG_TARGET_E2000Q is not set +# CONFIG_TARGET_E2000D is not set +# CONFIG_TARGET_E2000S is not set +# CONFIG_TARGET_FT2004 is not set +CONFIG_TARGET_D2000=y +# CONFIG_TARGET_PD2308 is not set +CONFIG_SOC_NAME="d2000" +CONFIG_SOC_CORE_NUM=8 +CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 +CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 +CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 +CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set +# end of Soc configuration + +# +# Board Configuration +# +CONFIG_BOARD_NAME="test" +CONFIG_D2000_TEST_BOARD=y + +# +# IO mux configuration when board start up +# +# CONFIG_CUS_DEMO_BOARD is not set + +# +# Build project name +# +CONFIG_TARGET_NAME="pin" +# end of Build project name +# end of Board Configuration + +# +# Sdk common configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +CONFIG_LOG_EXTRA_INFO=y +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set +# end of Sdk common configuration + +# +# Image information configuration +# +# CONFIG_IMAGE_INFO is not set +# end of Image information configuration + +# +# Drivers configuration +# +CONFIG_USE_IOMUX=y +CONFIG_ENABLE_IOCTRL=y +# CONFIG_ENABLE_IOPAD is not set +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration + +CONFIG_USE_GPIO=y +CONFIG_ENABLE_FGPIO=y +# CONFIG_USE_ETH is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_USE_I2S is not set +# CONFIG_USE_I3C is not set +# end of Drivers configuration + +# +# Third-party configuration +# +# CONFIG_USE_LWIP is not set +CONFIG_USE_LETTER_SHELL=y + +# +# Letter shell configuration +# +CONFIG_LS_PL011_UART=y +CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y +# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set +# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set +# end of Letter shell configuration + +# CONFIG_USE_AMP is not set +# CONFIG_USE_YMODEM is not set +# CONFIG_USE_SFUD is not set +# CONFIG_USE_FATFS_0_1_4 is not set +CONFIG_USE_TLSF=y +# CONFIG_USE_SPIFFS is not set +# CONFIG_USE_LITTLE_FS is not set +# CONFIG_USE_LVGL is not set +# CONFIG_USE_FREEMODBUS is not set +# CONFIG_USE_FSL_SDMMC is not set +# CONFIG_USE_MICROPYTHON is not set +# CONFIG_USE_TINYMAIX is not set +# end of Third-party configuration + +# +# Build setup +# +CONFIG_CHECK_DEPS=y +CONFIG_OUTPUT_BINARY=y + +# +# Optimization options +# +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_OPT_UNUSED_SECTIONS=y +CONFIG_DEBUG_LINK_MAP=y +# CONFIG_CCACHE is not set +# CONFIG_ARCH_COVERAGE is not set +# CONFIG_LTO_FULL is not set +# end of Optimization options + +# +# Debug options +# +# CONFIG_DEBUG_ENABLE_ALL_WARNING is not set +# CONFIG_WALL_WARNING_ERROR is not set +# CONFIG_STRICT_PROTOTYPES is not set +# CONFIG_DEBUG_SYMBOLS is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_OUTPUT_ASM_DIS is not set +# CONFIG_ENABLE_WSHADOW is not set +# CONFIG_ENABLE_WUNDEF is not set +CONFIG_DOWNGRADE_DIAG_WARNING=y +# end of Debug options + +# +# Lib +# +CONFIG_USE_COMPILE_CHAIN=y +# CONFIG_USE_NEWLIB is not set +# CONFIG_USE_USER_DEFINED is not set +# end of Lib + +# CONFIG_ENABLE_CXX is not set + +# +# Linker Options +# +CONFIG_DEFAULT_LINKER_SCRIPT=y +# CONFIG_USER_DEFINED_LD is not set +CONFIG_IMAGE_LOAD_ADDRESS=0x80100000 +CONFIG_IMAGE_MAX_LENGTH=0x1000000 +CONFIG_HEAP_SIZE=2 +CONFIG_SVC_STACK_SIZE=0x1000 +CONFIG_SYS_STACK_SIZE=0x1000 +CONFIG_IRQ_STACK_SIZE=0x1000 +CONFIG_ABORT_STACK_SIZE=0x1000 +CONFIG_FIQ_STACK_SIZE=0x1000 +CONFIG_UNDEF_STACK_SIZE=0x1000 +# end of Linker Options +# end of Build setup diff --git a/example/peripherals/pin/configs/d2000_aarch64_test_pin.config b/example/peripherals/pin/configs/d2000_aarch64_test_pin.config new file mode 100644 index 000000000..4e32430f3 --- /dev/null +++ b/example/peripherals/pin/configs/d2000_aarch64_test_pin.config @@ -0,0 +1,224 @@ +CONFIG_USE_BAREMETAL=y + +# +# Arch configuration +# +CONFIG_TARGET_ARMv8=y +CONFIG_ARCH_NAME="armv8" + +# +# Arm architecture configuration +# +CONFIG_ARCH_ARMV8_AARCH64=y +# CONFIG_ARCH_ARMV8_AARCH32 is not set + +# +# Compiler configuration +# +CONFIG_ARM_GCC_SELECT=y +# CONFIG_ARM_CLANG_SELECT is not set +CONFIG_TOOLCHAIN_NAME="gcc" +CONFIG_TARGET_ARMV8_AARCH64=y +CONFIG_ARCH_EXECUTION_STATE="aarch64" +CONFIG_ARM_NEON=y +CONFIG_ARM_CRC=y +CONFIG_ARM_CRYPTO=y +CONFIG_ARM_FLOAT_POINT=y +# CONFIG_GCC_CODE_MODEL_TINY is not set +CONFIG_GCC_CODE_MODEL_SMALL=y +# CONFIG_GCC_CODE_MODEL_LARGE is not set +# end of Compiler configuration + +CONFIG_USE_CACHE=y +# CONFIG_USE_L3CACHE is not set +CONFIG_USE_MMU=y +CONFIG_BOOT_WITH_FLUSH_CACHE=y +# CONFIG_MMU_DEBUG_PRINTS is not set +# end of Arm architecture configuration +# end of Arch configuration + +# +# Soc configuration +# +# CONFIG_TARGET_PHYTIUMPI is not set +# CONFIG_TARGET_E2000Q is not set +# CONFIG_TARGET_E2000D is not set +# CONFIG_TARGET_E2000S is not set +# CONFIG_TARGET_FT2004 is not set +CONFIG_TARGET_D2000=y +# CONFIG_TARGET_PD2308 is not set +CONFIG_SOC_NAME="d2000" +CONFIG_SOC_CORE_NUM=8 +CONFIG_F32BIT_MEMORY_ADDRESS=0x80000000 +CONFIG_F32BIT_MEMORY_LENGTH=0x80000000 +CONFIG_F64BIT_MEMORY_ADDRESS=0x2000000000 +CONFIG_F64BIT_MEMORY_LENGTH=0x800000000 +CONFIG_DEFAULT_DEBUG_PRINT_UART1=y +# CONFIG_DEFAULT_DEBUG_PRINT_UART0 is not set +# CONFIG_DEFAULT_DEBUG_PRINT_UART2 is not set +# end of Soc configuration + +# +# Board Configuration +# +CONFIG_BOARD_NAME="test" +CONFIG_D2000_TEST_BOARD=y + +# +# IO mux configuration when board start up +# +# CONFIG_CUS_DEMO_BOARD is not set + +# +# Build project name +# +CONFIG_TARGET_NAME="pin" +# end of Build project name +# end of Board Configuration + +# +# Sdk common configuration +# +# CONFIG_LOG_VERBOS is not set +# CONFIG_LOG_DEBUG is not set +# CONFIG_LOG_INFO is not set +# CONFIG_LOG_WARN is not set +CONFIG_LOG_ERROR=y +# CONFIG_LOG_NONE is not set +CONFIG_LOG_EXTRA_INFO=y +# CONFIG_LOG_DISPALY_CORE_NUM is not set +# CONFIG_BOOTUP_DEBUG_PRINTS is not set +CONFIG_USE_DEFAULT_INTERRUPT_CONFIG=y +CONFIG_INTERRUPT_ROLE_MASTER=y +# CONFIG_INTERRUPT_ROLE_SLAVE is not set +# end of Sdk common configuration + +# +# Image information configuration +# +# CONFIG_IMAGE_INFO is not set +# end of Image information configuration + +# +# Drivers configuration +# +CONFIG_USE_IOMUX=y +CONFIG_ENABLE_IOCTRL=y +# CONFIG_ENABLE_IOPAD is not set +# CONFIG_USE_SPI is not set +# CONFIG_USE_QSPI is not set +CONFIG_USE_SERIAL=y + +# +# Usart Configuration +# +CONFIG_ENABLE_Pl011_UART=y +# end of Usart Configuration + +CONFIG_USE_GPIO=y +CONFIG_ENABLE_FGPIO=y +# CONFIG_USE_ETH is not set +# CONFIG_USE_CAN is not set +# CONFIG_USE_I2C is not set +# CONFIG_USE_TIMER is not set +# CONFIG_USE_MIO is not set +# CONFIG_USE_SDMMC is not set +# CONFIG_USE_PCIE is not set +# CONFIG_USE_WDT is not set +# CONFIG_USE_DMA is not set +# CONFIG_USE_NAND is not set +# CONFIG_USE_RTC is not set +# CONFIG_USE_SATA is not set +# CONFIG_USE_USB is not set +# CONFIG_USE_ADC is not set +# CONFIG_USE_PWM is not set +# CONFIG_USE_IPC is not set +# CONFIG_USE_MEDIA is not set +# CONFIG_USE_SCMI_MHU is not set +# CONFIG_USE_I2S is not set +# CONFIG_USE_I3C is not set +# end of Drivers configuration + +# +# Third-party configuration +# +# CONFIG_USE_LWIP is not set +CONFIG_USE_LETTER_SHELL=y + +# +# Letter shell configuration +# +CONFIG_LS_PL011_UART=y +CONFIG_DEFAULT_LETTER_SHELL_USE_UART1=y +# CONFIG_DEFAULT_LETTER_SHELL_USE_UART0 is not set +# CONFIG_DEFAULT_LETTER_SHELL_USE_UART2 is not set +# end of Letter shell configuration + +# CONFIG_USE_AMP is not set +# CONFIG_USE_YMODEM is not set +# CONFIG_USE_SFUD is not set +# CONFIG_USE_FATFS_0_1_4 is not set +CONFIG_USE_TLSF=y +# CONFIG_USE_SPIFFS is not set +# CONFIG_USE_LITTLE_FS is not set +# CONFIG_USE_LVGL is not set +# CONFIG_USE_FREEMODBUS is not set +# CONFIG_USE_FSL_SDMMC is not set +# CONFIG_USE_MICROPYTHON is not set +# CONFIG_USE_TINYMAIX is not set +# end of Third-party configuration + +# +# Build setup +# +CONFIG_CHECK_DEPS=y +CONFIG_OUTPUT_BINARY=y + +# +# Optimization options +# +# CONFIG_DEBUG_NOOPT is not set +# CONFIG_DEBUG_CUSTOMOPT is not set +CONFIG_DEBUG_FULLOPT=y +CONFIG_DEBUG_OPT_UNUSED_SECTIONS=y +CONFIG_DEBUG_LINK_MAP=y +# CONFIG_CCACHE is not set +# CONFIG_ARCH_COVERAGE is not set +# CONFIG_LTO_FULL is not set +# end of Optimization options + +# +# Debug options +# +# CONFIG_DEBUG_ENABLE_ALL_WARNING is not set +# CONFIG_WALL_WARNING_ERROR is not set +# CONFIG_STRICT_PROTOTYPES is not set +# CONFIG_DEBUG_SYMBOLS is not set +# CONFIG_FRAME_POINTER is not set +# CONFIG_OUTPUT_ASM_DIS is not set +# CONFIG_ENABLE_WSHADOW is not set +# CONFIG_ENABLE_WUNDEF is not set +CONFIG_DOWNGRADE_DIAG_WARNING=y +# end of Debug options + +# +# Lib +# +CONFIG_USE_COMPILE_CHAIN=y +# CONFIG_USE_NEWLIB is not set +# CONFIG_USE_USER_DEFINED is not set +# end of Lib + +# CONFIG_ENABLE_CXX is not set + +# +# Linker Options +# +CONFIG_DEFAULT_LINKER_SCRIPT=y +# CONFIG_USER_DEFINED_LD is not set +CONFIG_IMAGE_LOAD_ADDRESS=0x80100000 +CONFIG_IMAGE_MAX_LENGTH=0x1000000 +CONFIG_HEAP_SIZE=2 +CONFIG_STACK_SIZE=0x400 +# end of Linker Options +# end of Build setup diff --git a/example/peripherals/pin/figs/d2000_gpio_pin.png b/example/peripherals/pin/figs/d2000_gpio_pin.png new file mode 100644 index 000000000..0d4c8c305 Binary files /dev/null and b/example/peripherals/pin/figs/d2000_gpio_pin.png differ diff --git a/example/peripherals/pin/figs/d2000_pin_gpio_intr_result.png b/example/peripherals/pin/figs/d2000_pin_gpio_intr_result.png new file mode 100644 index 000000000..707edfc70 Binary files /dev/null and b/example/peripherals/pin/figs/d2000_pin_gpio_intr_result.png differ diff --git a/example/peripherals/pin/figs/d2000_two_gpio.png b/example/peripherals/pin/figs/d2000_two_gpio.png new file mode 100644 index 000000000..aa32fb62c Binary files /dev/null and b/example/peripherals/pin/figs/d2000_two_gpio.png differ diff --git a/example/peripherals/pin/figs/d2000_two_gpio_intr_result.png b/example/peripherals/pin/figs/d2000_two_gpio_intr_result.png new file mode 100644 index 000000000..c3ef81448 Binary files /dev/null and b/example/peripherals/pin/figs/d2000_two_gpio_intr_result.png differ diff --git a/example/peripherals/pin/figs/firefly.png b/example/peripherals/pin/figs/firefly.png new file mode 100644 index 000000000..3d0a2df00 Binary files /dev/null and b/example/peripherals/pin/figs/firefly.png differ diff --git a/example/peripherals/pin/figs/firefly_two_gpio.png b/example/peripherals/pin/figs/firefly_two_gpio.png new file mode 100644 index 000000000..bf0b41fdb Binary files /dev/null and b/example/peripherals/pin/figs/firefly_two_gpio.png differ diff --git a/example/peripherals/pin/figs/firefly_two_gpio_intr_result.png b/example/peripherals/pin/figs/firefly_two_gpio_intr_result.png new file mode 100644 index 000000000..046bece4d Binary files /dev/null and b/example/peripherals/pin/figs/firefly_two_gpio_intr_result.png differ diff --git a/example/peripherals/pin/figs/nanodla_pwm.jpg b/example/peripherals/pin/figs/nanodla_pwm.jpg new file mode 100644 index 000000000..e6d247bf7 Binary files /dev/null and b/example/peripherals/pin/figs/nanodla_pwm.jpg differ diff --git a/example/peripherals/pin/figs/pin_gpio_intr_board.png b/example/peripherals/pin/figs/pin_gpio_intr_board.png index a8d138a3c..0bb54936f 100644 Binary files a/example/peripherals/pin/figs/pin_gpio_intr_board.png and b/example/peripherals/pin/figs/pin_gpio_intr_board.png differ diff --git a/example/peripherals/pin/figs/pin_gpio_pwm_board.png b/example/peripherals/pin/figs/pin_gpio_pwm_board.png index f53f248fc..8c83db998 100644 Binary files a/example/peripherals/pin/figs/pin_gpio_pwm_board.png and b/example/peripherals/pin/figs/pin_gpio_pwm_board.png differ diff --git a/example/peripherals/pin/figs/pin_gpio_pwm_result_3.png b/example/peripherals/pin/figs/pin_gpio_pwm_result_3.png new file mode 100644 index 000000000..f4a9286cc Binary files /dev/null and b/example/peripherals/pin/figs/pin_gpio_pwm_result_3.png differ diff --git a/example/peripherals/pin/figs/two_gpio_intr_result.png b/example/peripherals/pin/figs/two_gpio_intr_result.png new file mode 100644 index 000000000..c2e2ada82 Binary files /dev/null and b/example/peripherals/pin/figs/two_gpio_intr_result.png differ diff --git a/example/peripherals/pin/figs/two_input_gpio.png b/example/peripherals/pin/figs/two_input_gpio.png new file mode 100644 index 000000000..f990529f4 Binary files /dev/null and b/example/peripherals/pin/figs/two_input_gpio.png differ diff --git a/example/peripherals/pin/inc/pin_gpio_multi_input_example.h b/example/peripherals/pin/inc/pin_gpio_multi_input_example.h new file mode 100644 index 000000000..a6aac7fce --- /dev/null +++ b/example/peripherals/pin/inc/pin_gpio_multi_input_example.h @@ -0,0 +1,44 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: pin_gpio_multi_input_example.h + * Date: 2022-03-01 16:58:44 + * LastEditTime: 2022-03-05 12:46:07 + * Description:  This file is for gpio interrupt tigger function definition. + * Modify History: + * Ver    Who        Date         Changes + * -----  -------    --------     -------------------------------------- + * 1.0 zhugengyu 2024/05/09 first commit + */ + +#ifndef PIN_GPIO_MULTI_INPUT_EXAMPLE_H +#define PIN_GPIO_MULTI_INPUT_EXAMPLE_H + +#ifdef __cplusplus +extern "C" +{ +#endif +/***************************** Include Files *********************************/ +#include "ftypes.h" +#include "fgpio.h" +#include "fkernel.h" +/**************************** Type Definitions *******************************/ + +/************************** Function Prototypes ******************************/ +int FPinGpioMultiInputExample(void); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/example/peripherals/pin/inc/pin_gpio_pwm_example.h b/example/peripherals/pin/inc/pin_gpio_pwm_example.h index 0258c285b..e92200bd1 100644 --- a/example/peripherals/pin/inc/pin_gpio_pwm_example.h +++ b/example/peripherals/pin/inc/pin_gpio_pwm_example.h @@ -19,6 +19,7 @@ * Ver    Who        Date         Changes * -----  -------    --------     -------------------------------------- * 1.0 liqiaozhong 2023/03/05 first commit + * 2.0 zhugengyu 2024/5/8 update interface to use gpio by pin */ #ifndef PIN_GPIO_PWM_EXAMPLE_H @@ -35,11 +36,11 @@ extern "C" /**************************** Type Definitions *******************************/ typedef struct /* pwm instance */ { - FGpioPin *pin_instance; + FGpio *pin_instance; u32 range; volatile boolean is_running; u32 duty; - FGpioPinVal level; + FGpioVal level; u32 count; } FSoftPwm; diff --git a/example/peripherals/pin/src/cmd_pin.c b/example/peripherals/pin/src/cmd_pin.c index 75882658f..ff3f63305 100644 --- a/example/peripherals/pin/src/cmd_pin.c +++ b/example/peripherals/pin/src/cmd_pin.c @@ -39,6 +39,7 @@ #include "pin_common.h" #include "pin_gpio_intr_example.h" +#include "pin_gpio_multi_input_example.h" #include "pin_gpio_low_level_example.h" #include "pin_gpio_pwm_example.h" @@ -48,6 +49,8 @@ static void FPinExampleUsage(void) printf("Usage:\r\n"); printf("pin gpio_intr_example\r\n"); printf("-- run pin gpio interrupt trigger example on defult controller\r\n"); + printf("pin gpio_multi_input_example\r\n"); + printf("-- run pin gpio multi input interrupt example on defult controller\r\n"); printf("pin gpio_low_level_example\r\n"); printf("-- run pin gpio register operation example on defult controller\r\n"); printf("pin gpio_pwm_example\r\n"); @@ -71,6 +74,10 @@ static int FPinExampleEntry(int argc, char *argv[]) { ret = FPinGpioIntrExample(); } + else if (!strcmp(argv[1], "gpio_multi_input_example")) + { + ret = FPinGpioMultiInputExample(); + } else if (!strcmp(argv[1], "gpio_low_level_example")) { ret = FPinGpioLowLevelExample(); diff --git a/example/peripherals/pin/src/pin_gpio_intr_example.c b/example/peripherals/pin/src/pin_gpio_intr_example.c index 5177ace6d..a4af117f3 100644 --- a/example/peripherals/pin/src/pin_gpio_intr_example.c +++ b/example/peripherals/pin/src/pin_gpio_intr_example.c @@ -21,6 +21,7 @@ * -----  -------    --------     -------------------------------------- * 1.0 liqiaozhong 2023/03/05 first commit * 1.1 liqiaozhong 2023/8/11 adapt to new iomux + * 2.0 zhugengyu 2024/5/8 update interface to use gpio by pin */ @@ -42,23 +43,25 @@ #include "fcpu_info.h" #include "fio_mux.h" +#include "fparameters.h" + #include "fgpio.h" #include "pin_common.h" #include "pin_gpio_intr_example.h" /************************** Constant Definitions *****************************/ #if defined(CONFIG_FIREFLY_DEMO_BOARD) -static const u32 ctrl_id = FGPIO3_ID; -static const FGpioPinId input_pin_index = {FGPIO3_ID, FGPIO_PORT_A, FGPIO_PIN_1}; -static const FGpioPinId output_pin_index = {FGPIO3_ID, FGPIO_PORT_A, FGPIO_PIN_2}; +static const u32 input_pin_index = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_0); +static const u32 output_pin_index = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_13); #elif defined(CONFIG_E2000Q_DEMO_BOARD) || defined(CONFIG_E2000D_DEMO_BOARD) -static const u32 ctrl_id = FGPIO4_ID; -static const FGpioPinId input_pin_index = {FGPIO4_ID, FGPIO_PORT_A, FGPIO_PIN_11}; -static const FGpioPinId output_pin_index = {FGPIO4_ID, FGPIO_PORT_A, FGPIO_PIN_12}; +static const u32 input_pin_index = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_11); +static const u32 output_pin_index = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_12); #elif defined(CONFIG_PD2308_DEMO_BOARD) -static const u32 ctrl_id = FGPIO0_ID; -static const FGpioPinId input_pin_index = {FGPIO0_ID, FGPIO_PORT_A, FGPIO_PIN_8}; -static const FGpioPinId output_pin_index = {FGPIO0_ID, FGPIO_PORT_A, FGPIO_PIN_10}; +static const u32 input_pin_index = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_8); +static const u32 output_pin_index = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_10); +#elif defined(CONFIG_D2000_TEST_BOARD) +static const u32 input_pin_index = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_6); +static const u32 output_pin_index = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_7); #endif static FGpioIrqType irq_type = FGPIO_IRQ_TYPE_LEVEL_HIGH; @@ -72,9 +75,8 @@ static const char *irq_type_names[] = /**************************** Type Definitions *******************************/ static int intr_flag = 0; /************************** Variable Definitions *****************************/ -static FGpio ctrl_instance; -static FGpioPin input_pin_instance; -static FGpioPin output_pin_instance; +static FGpio input_pin_instance; +static FGpio output_pin_instance; /***************** Macros (Inline Functions) Definitions *********************/ /************************** Function Prototypes ******************************/ @@ -84,9 +86,9 @@ static void FPinAckIrq(s32 vector, void *param) { printf("Assert %s for gpio %d-%c-%d !!!\n", irq_type_names[irq_type], - input_pin_index.ctrl, - (input_pin_index.port == FGPIO_PORT_A)?'a':'b', - input_pin_index.pin); + input_pin_instance.config.ctrl, + (input_pin_instance.config.port == FGPIO_PORT_A)?'a':'b', + input_pin_instance.config.pin); intr_flag = 1; @@ -100,6 +102,11 @@ static void FPinAckIrq(s32 vector, void *param) { FGpioSetOutputValue(&output_pin_instance, FGPIO_PIN_LOW); } + + if ((FGPIO_IRQ_TYPE_LEVEL_LOW == irq_type) || (FGPIO_IRQ_TYPE_LEVEL_HIGH == irq_type)) + { + FGpioSetInterruptMask(&input_pin_instance, FALSE); /* disable pin irq */ + } } static void FPinTriggerFallingEdgeIrq(void) @@ -162,59 +169,63 @@ static void FPinTriggerLevelHighIrq(void) int FPinGpioIntrExample(void) { int ret = 0; - input_pin_instance.index = input_pin_index; - output_pin_instance.index = output_pin_index; + u32 cpu_id; + u32 irq_num; + u32 irq_priority = 0U; + + memset(&input_pin_instance, 0, sizeof(input_pin_instance)); + memset(&output_pin_instance, 0, sizeof(output_pin_instance)); /* init ctrl */ - FGpioConfig input_cfg = *FGpioLookupConfig(ctrl_id); - ret = FGpioCfgInitialize(&ctrl_instance, &input_cfg); + FGpioConfig input_cfg = *FGpioLookupConfig(input_pin_index); + FGpioConfig output_cfg = *FGpioLookupConfig(output_pin_index); FIOMuxInit(); - FIOPadSetGpioMux(input_pin_index.ctrl, (u32)input_pin_index.pin); - FIOPadSetGpioMux(output_pin_index.ctrl, (u32)output_pin_index.pin); - ret = FGpioPinInitialize(&ctrl_instance, &input_pin_instance, input_pin_index); - ret = FGpioPinInitialize(&ctrl_instance, &output_pin_instance, output_pin_index); + ret = FGpioCfgInitialize(&input_pin_instance, &input_cfg); + FASSERT(ret == FT_SUCCESS); - if (ret != 0) - { - printf("Fail to init ctrl or pins."); - goto exit; - } + ret = FGpioCfgInitialize(&output_pin_instance, &output_cfg); + FASSERT(ret == FT_SUCCESS); + +#if defined(CONFIG_D2000_TEST_BOARD) + FIOPadSetGpioMux(input_pin_instance.config.ctrl, input_pin_instance.config.port, (u32)input_pin_instance.config.pin); + FIOPadSetGpioMux(output_pin_instance.config.ctrl, output_pin_instance.config.port, (u32)output_pin_instance.config.pin); +#else + FIOPadSetGpioMux(input_pin_instance.config.ctrl, (u32)input_pin_instance.config.pin); + FIOPadSetGpioMux(output_pin_instance.config.ctrl, (u32)output_pin_instance.config.pin); +#endif FGpioSetDirection(&input_pin_instance, FGPIO_DIR_INPUT); FGpioSetDirection(&output_pin_instance, FGPIO_DIR_OUTPUT); /* input pin irq set */ - FGpioSetInterruptMask(&input_pin_instance, FALSE); /* disable pin irq */ - if (input_pin_instance.instance->config.caps & FGPIO_CAPACITY_IRQ_TYPE)//单独中断号上报 + if (input_pin_instance.config.cap & FGPIO_CAP_IRQ_NONE) { - FASSERT_MSG((FGPIO_IRQ_BY_PIN == FGpioGetPinIrqSourceType(input_pin_instance)), - "Irq is not reported by pin."); - } - else//合成中断号上报 - { - FASSERT_MSG((FGPIO_IRQ_BY_CONTROLLER == FGpioGetPinIrqSourceType(input_pin_instance)), - "Irq is not reported by controller."); + printf("input gpio %u-%u-%u do not support interrupt\r\n", + input_pin_instance.config.ctrl, + input_pin_instance.config.port, + input_pin_instance.config.pin); + intr_flag = 0; + goto exit; } - u32 cpu_id; - u32 irq_num; - irq_num = ctrl_instance.config.irq_num[input_pin_index.pin]; + irq_num = input_pin_instance.config.irq_num; GetCpuId(&cpu_id); FPIN_TEST_INFO("cpu_id is cpu_id %d, irq_num %d", cpu_id, irq_num); InterruptSetTargetCpus(irq_num, cpu_id); - InterruptSetPriority(irq_num, ctrl_instance.config.irq_priority); /* setup interrupt */ - InterruptInstall(irq_num, - FGpioInterruptHandler, - &ctrl_instance, - NULL); /* register intr handler */ - InterruptUmask(irq_num); - + InterruptSetPriority(irq_num, irq_priority); /* setup interrupt */ + FGpioRegisterInterruptCB(&input_pin_instance, FPinAckIrq, - NULL, - FALSE); /* register intr callback */ + NULL); /* register intr callback to intr map */ + + InterruptInstall(irq_num, + FGpioInterruptHandler, + NULL, + NULL); /* register intr handler */ + + InterruptUmask(irq_num); /* trigger irq as one of four types */ switch (irq_type) @@ -239,7 +250,8 @@ int FPinGpioIntrExample(void) FGpioSetInterruptMask(&input_pin_instance, FALSE); /* deinit ctrl and pin instance */ - FGpioDeInitialize(&ctrl_instance); + FGpioDeInitialize(&input_pin_instance); + FGpioDeInitialize(&output_pin_instance); InterruptMask(irq_num); diff --git a/example/peripherals/pin/src/pin_gpio_low_level_example.c b/example/peripherals/pin/src/pin_gpio_low_level_example.c index 43fb455a9..4954b9668 100644 --- a/example/peripherals/pin/src/pin_gpio_low_level_example.c +++ b/example/peripherals/pin/src/pin_gpio_low_level_example.c @@ -21,6 +21,7 @@ * -----  -------    --------     -------------------------------------- * 1.0 liqiaozhong 2023/03/05 first commit * 1.1 liqiaozhong 2023/8/11 adapt to new iomux + * 2.0 zhugengyu 2024/5/8 update interface to use gpio by pin */ /***************************** Include Files *********************************/ @@ -39,6 +40,8 @@ #include "fsleep.h" #include "fio_mux.h" +#include "fparameters.h" + #include "fgpio_hw.h" #include "pin_common.h" @@ -51,20 +54,35 @@ /***************** Macros (Inline Functions) Definitions *********************/ #if defined(CONFIG_FIREFLY_DEMO_BOARD) -static uintptr gpio_base = FGPIO3_BASE_ADDR; -static const u32 ctrl_id = FGPIO3_ID; -static u32 input_pin = (u32)FGPIO_PIN_1; -static u32 output_pin = (u32)FGPIO_PIN_2; +static uintptr input_base = FGPIO0_BASE_ADDR; +static const u32 input_ctrl = FGPIO_CTRL_0; +static u32 input_pin = (u32)FGPIO_PIN_0; +static uintptr output_base = FGPIO4_BASE_ADDR; +static const u32 output_ctrl = FGPIO_CTRL_4; +static u32 output_pin = (u32)FGPIO_PIN_13; #elif defined(CONFIG_E2000Q_DEMO_BOARD) || defined(CONFIG_E2000D_DEMO_BOARD) -static uintptr gpio_base = FGPIO4_BASE_ADDR; -static const u32 ctrl_id = FGPIO4_ID; +static uintptr input_base = FGPIO4_BASE_ADDR; +static const u32 input_ctrl = FGPIO_CTRL_4; static u32 input_pin = (u32)FGPIO_PIN_11; +static uintptr output_base = FGPIO4_BASE_ADDR; +static const u32 output_ctrl = FGPIO_CTRL_4; static u32 output_pin = (u32)FGPIO_PIN_12; #elif defined(CONFIG_PD2308_DEMO_BOARD) -static uintptr gpio_base = FGPIO0_BASE_ADDR; -static const u32 ctrl_id = FGPIO0_ID; +static uintptr input_base = FGPIO0_BASE_ADDR; +static const u32 input_ctrl = FGPIO_CTRL_0; static u32 input_pin = (u32)FGPIO_PIN_8; +static uintptr output_base = FGPIO0_BASE_ADDR; +static const u32 output_ctrl = FGPIO_CTRL_0; static u32 output_pin = (u32)FGPIO_PIN_10; +#elif defined(CONFIG_D2000_TEST_BOARD) +static uintptr input_base = FGPIO1_BASE_ADDR; +static const u32 input_ctrl = FGPIO_CTRL_1; +static u32 input_port = FGPIO_PORT_A; +static u32 input_pin = (u32)FGPIO_PIN_6; +static uintptr output_base = FGPIO1_BASE_ADDR; +static const u32 output_ctrl = FGPIO_CTRL_1; +static u32 output_port = FGPIO_PORT_A; +static u32 output_pin = (u32)FGPIO_PIN_7; #endif /************************** Function Prototypes ******************************/ @@ -80,23 +98,31 @@ int FPinGpioLowLevelExample(void) /* init pin */ FIOMuxInit(); - FIOPadSetGpioMux(ctrl_id, input_pin); - FIOPadSetGpioMux(ctrl_id, output_pin); +#if defined(CONFIG_D2000_TEST_BOARD) + FIOPadSetGpioMux(input_ctrl, input_port, input_pin); + FIOPadSetGpioMux(output_ctrl, output_port, output_pin); +#else + FIOPadSetGpioMux(input_ctrl, input_pin); + FIOPadSetGpioMux(output_ctrl, output_pin); +#endif - reg_val = FGpioReadReg32(gpio_base, FGPIO_SWPORTA_DDR_OFFSET); /* set direction */ + reg_val = FGpioReadReg32(input_base, FGPIO_SWPORTA_DDR_OFFSET); /* set direction */ reg_val &= ~BIT(input_pin); /* 0-input */ + FGpioWriteReg32(input_base, FGPIO_SWPORTA_DDR_OFFSET, reg_val); + + reg_val = FGpioReadReg32(output_base, FGPIO_SWPORTA_DDR_OFFSET); /* set direction */ reg_val |= BIT(output_pin); /* 1-output */ - FGpioWriteReg32(gpio_base, FGPIO_SWPORTA_DDR_OFFSET, reg_val); + FGpioWriteReg32(output_base, FGPIO_SWPORTA_DDR_OFFSET, reg_val); /* operations */ - reg_val = FGpioReadReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to low-level */ + reg_val = FGpioReadReg32(output_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to low-level */ reg_val &= ~BIT(output_pin); - FGpioWriteReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); + FGpioWriteReg32(output_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); - reg_val = FGpioReadReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to high-level */ + reg_val = FGpioReadReg32(output_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to high-level */ reg_val |= BIT(output_pin); - FGpioWriteReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); - reg_val = FGpioReadReg32(gpio_base, FGPIO_EXT_PORTA_OFFSET); /* get input pin level */ + FGpioWriteReg32(output_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); + reg_val = FGpioReadReg32(input_base, FGPIO_EXT_PORTA_OFFSET); /* get input pin level */ if (((BIT(input_pin) & reg_val) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW) == FGPIO_PIN_HIGH) { printf("Low level operation works for the first time.\n"); @@ -109,10 +135,10 @@ int FPinGpioLowLevelExample(void) fsleep_millisec(10); /* delay 10ms */ - reg_val = FGpioReadReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to low-level */ + reg_val = FGpioReadReg32(output_base, FGPIO_SWPORTA_DR_OFFSET); /* set output pin to low-level */ reg_val &= ~BIT(output_pin); - FGpioWriteReg32(gpio_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); - reg_val = FGpioReadReg32(gpio_base, FGPIO_EXT_PORTA_OFFSET); /* get input pin level */ + FGpioWriteReg32(output_base, FGPIO_SWPORTA_DR_OFFSET, reg_val); + reg_val = FGpioReadReg32(input_base, FGPIO_EXT_PORTA_OFFSET); /* get input pin level */ if (((BIT(input_pin) & reg_val) ? FGPIO_PIN_HIGH : FGPIO_PIN_LOW) == FGPIO_PIN_LOW) { printf("Low level operation works for the second time.\n"); diff --git a/example/peripherals/pin/src/pin_gpio_multi_input_example.c b/example/peripherals/pin/src/pin_gpio_multi_input_example.c new file mode 100644 index 000000000..a2c318fc3 --- /dev/null +++ b/example/peripherals/pin/src/pin_gpio_multi_input_example.c @@ -0,0 +1,214 @@ +/* + * Copyright : (C) 2023 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: pin_gpio_intr_example.c + * Date: 2022-03-01 12:54:42 + * LastEditTime: 2022-03-05 17:28:07 + * Description:  This file is for pin gpio interrupt tigger example function implmentation. + * + * Modify History: + * Ver    Who        Date         Changes + * -----  -------    --------     -------------------------------------- + * 1.0 liqiaozhong 2023/03/05 first commit + * 1.1 liqiaozhong 2023/8/11 adapt to new iomux + * 2.0 zhugengyu 2024/5/8 update interface to use gpio by pin + */ + + +/***************************** Include Files *********************************/ +#include "sdkconfig.h" +#ifndef SDK_CONFIG_H__ + #warning "Please include sdkconfig.h" +#endif + +#include +#include +#include "strto.h" + +#include "ftypes.h" +#include "fdebug.h" +#include "fassert.h" +#include "fsleep.h" +#include "finterrupt.h" +#include "fcpu_info.h" +#include "fio_mux.h" + +#include "fparameters.h" + +#include "fgpio.h" + +#include "pin_common.h" +#include "pin_gpio_intr_example.h" +/************************** Constant Definitions *****************************/ +#if defined(CONFIG_FIREFLY_DEMO_BOARD) +#define GPIO_INPUT_PIN_NUM 3U + +static const u32 pin_index_array[GPIO_INPUT_PIN_NUM] = +{ + FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_13), /* IRQ 189 */ + FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_0), /* IRQ 140 */ + FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_12) /* IRQ 189 */ +}; +#elif defined(CONFIG_E2000Q_DEMO_BOARD) || defined(CONFIG_E2000D_DEMO_BOARD) +#define GPIO_INPUT_PIN_NUM 2U + +static const u32 pin_index_array[GPIO_INPUT_PIN_NUM] = +{ + FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_11), + FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_12) +}; +#elif defined(CONFIG_PD2308_DEMO_BOARD) +#define GPIO_INPUT_PIN_NUM 2U + +static const u32 pin_index_array[GPIO_INPUT_PIN_NUM] = +{ + FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_8), + FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_10) +}; +#elif defined(CONFIG_D2000_TEST_BOARD) +#define GPIO_INPUT_PIN_NUM 2U + +static const u32 pin_index_array[GPIO_INPUT_PIN_NUM] = +{ + FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_6), + FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_7) +}; +#endif + +static FGpioIrqType irq_type = FGPIO_IRQ_TYPE_LEVEL_LOW; +static const char *irq_type_names[] = +{ + [FGPIO_IRQ_TYPE_EDGE_FALLING] = "falling edge", + [FGPIO_IRQ_TYPE_EDGE_RISING] = "rising edge", + [FGPIO_IRQ_TYPE_LEVEL_LOW] = "level low", + [FGPIO_IRQ_TYPE_LEVEL_HIGH] = "level high" +}; +/**************************** Type Definitions *******************************/ + +/************************** Variable Definitions *****************************/ +static int intr_count = 0; +static FGpio pin_array[GPIO_INPUT_PIN_NUM]; +static FGpioConfig pin_config_array[GPIO_INPUT_PIN_NUM]; +/***************** Macros (Inline Functions) Definitions *********************/ + +/************************** Function Prototypes ******************************/ + +/************************** Function *****************************************/ +static void FPinAckPinIrq(s32 vector, void *param) +{ + FGpio *pin = (FGpio *)param; + printf("Assert %s for gpio %d-%c-%d !!!\n", + irq_type_names[irq_type], + pin->config.ctrl, + (pin->config.port == FGPIO_PORT_A)?'a':'b', + pin->config.pin); + + intr_count++; + + /* level-sensitive interrupts keeps comming if not disabled */ + if ((FGPIO_IRQ_TYPE_LEVEL_LOW == irq_type) || (FGPIO_IRQ_TYPE_LEVEL_HIGH == irq_type)) + { + FGpioSetInterruptMask(pin, FALSE); /* disable pin irq */ + } +} + +int FPinGpioMultiInputExample(void) +{ + int ret = 0; + u32 cpu_id; + u32 irq_priority = 0; + + intr_count = 0; + memset(&pin_array, 0, sizeof(pin_array)); + + GetCpuId(&cpu_id); + FPIN_TEST_INFO("cpu_id is cpu_id %d", cpu_id); + + FIOMuxInit(); + + for (int i = 0; i < GPIO_INPUT_PIN_NUM; i++) + { + pin_config_array[i] = *FGpioLookupConfig(pin_index_array[i]); + + /* init input pins */ + ret = FGpioCfgInitialize(&pin_array[i], &pin_config_array[i]); + FASSERT(ret == FT_SUCCESS); + + /* set iomux for input inputs */ +#if defined(CONFIG_D2000_TEST_BOARD) + FIOPadSetGpioMux(pin_array[i].config.ctrl, pin_array[i].config.port, pin_array[i].config.pin); +#else + FIOPadSetGpioMux(pin_array[i].config.ctrl, pin_array[i].config.pin); +#endif + + /* set pin direction as input */ + FGpioSetDirection(&pin_array[i], FGPIO_DIR_INPUT); + + /* check if input pin support interrupt */ + if (pin_array[i].config.cap & FGPIO_CAP_IRQ_NONE) + { + printf("interrupt not supported !!!"); + goto exit; + } + + /* register pin intr callback */ + FGpioRegisterInterruptCB(&pin_array[i], + FPinAckPinIrq, + &pin_array[i]); + + /* setup interrupt for input pin, if multi pin shared the same interrupt id, interrupt callback + will be handle by interrupt map internally */ + InterruptInstall(pin_array[i].config.irq_num, + FGpioInterruptHandler, + NULL, + NULL); /* register intr handler */ + + FPIN_TEST_INFO("pin %d-%d irq = %d", + pin_array[i].config.ctrl, + pin_array[i].config.pin, + pin_array[i].config.irq_num); + + InterruptSetTargetCpus(pin_array[i].config.irq_num, cpu_id); + InterruptSetPriority(pin_array[i].config.irq_num, irq_priority); + InterruptUmask(pin_array[i].config.irq_num); + + FGpioSetInterruptMask(&pin_array[i], TRUE); + } + + /* wait interrupt handle done */ + fsleep_millisec(10); + + for (int i = 0; i < GPIO_INPUT_PIN_NUM; i++) + { + FGpioSetInterruptMask(&pin_array[i], FALSE); + + InterruptUmask(pin_array[i].config.irq_num); + + FGpioDeInitialize(&pin_array[i]); + } + + FIOMuxDeInit(); + +exit: + /* print message on example run result */ + if (intr_count == GPIO_INPUT_PIN_NUM) + { + printf("%s@%d: pin GPIO intr example [success].\r\n", __func__, __LINE__); + return 0; + } + else + { + printf("%s@%d: pin GPIO intr example [failure].\r\n", __func__, __LINE__); + return 1; + } +} \ No newline at end of file diff --git a/example/peripherals/pin/src/pin_gpio_pwm_example.c b/example/peripherals/pin/src/pin_gpio_pwm_example.c index 020b2eba8..a132f5807 100644 --- a/example/peripherals/pin/src/pin_gpio_pwm_example.c +++ b/example/peripherals/pin/src/pin_gpio_pwm_example.c @@ -21,6 +21,7 @@ * -----  -------    --------     -------------------------------------- * 1.0 liqiaozhong 2023/03/05 first commit * 1.1 liqiaozhong 2023/8/11 adapt to new iomux + * 2.0 zhugengyu 2024/5/8 update interface to use gpio by pin */ @@ -42,6 +43,8 @@ #include "fgeneric_timer.h" #include "fio_mux.h" +#include "fparameters.h" + #include "fgpio.h" #include "pin_common.h" @@ -51,25 +54,24 @@ #define SYS_TICKINTR_PRIORITY IRQ_PRIORITY_VALUE_11 #if defined(CONFIG_FIREFLY_DEMO_BOARD) -static const u32 pwm_ctrl_id = FGPIO3_ID; -static const FGpioPinId output_pin_index_1 = {FGPIO3_ID, FGPIO_PORT_A, FGPIO_PIN_1}; -static const FGpioPinId output_pin_index_2 = {FGPIO3_ID, FGPIO_PORT_A, FGPIO_PIN_2}; +static const u32 output_pin_index_1 = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_0); +static const u32 output_pin_index_2 = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_13); #elif defined(CONFIG_E2000Q_DEMO_BOARD) || defined(CONFIG_E2000D_DEMO_BOARD) -static const u32 pwm_ctrl_id = FGPIO4_ID; -static const FGpioPinId output_pin_index_1 = {FGPIO4_ID, FGPIO_PORT_A, FGPIO_PIN_11}; -static const FGpioPinId output_pin_index_2 = {FGPIO4_ID, FGPIO_PORT_A, FGPIO_PIN_12}; +static const u32 output_pin_index_1 = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_11); +static const u32 output_pin_index_2 = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_12); #elif defined(CONFIG_PD2308_DEMO_BOARD) -static const u32 pwm_ctrl_id = FGPIO0_ID; -static const FGpioPinId output_pin_index_1 = {FGPIO0_ID, FGPIO_PORT_A, FGPIO_PIN_8}; -static const FGpioPinId output_pin_index_2 = {FGPIO0_ID, FGPIO_PORT_A, FGPIO_PIN_9}; +static const u32 output_pin_index_1 = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_8); +static const u32 output_pin_index_2 = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_9); +#elif defined(CONFIG_D2000_TEST_BOARD) +static const u32 output_pin_index_1 = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_6); +static const u32 output_pin_index_2 = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_7); #endif /**************************** Type Definitions *******************************/ /************************** Variable Definitions *****************************/ -static FGpio pwm_ctrl_instance; -static FGpioPin output_pin_instance_1; -static FGpioPin output_pin_instance_2; +static FGpio output_pin_instance_1; +static FGpio output_pin_instance_2; static FSoftPwm pwm_output_1; static FSoftPwm pwm_output_2; /* pwm related parameters */ @@ -125,7 +127,7 @@ static void PwmStart(FSoftPwm *const pwm) } -static int FSoftPwmSetup(FSoftPwm *const pwm, FGpioPin *pin_instance, u32 range) +static int FSoftPwmSetup(FSoftPwm *const pwm, FGpio *pin_instance, u32 range) { FASSERT(pwm); @@ -168,7 +170,7 @@ static void FPwmTickInterruptHandler(FSoftPwm *const pwm) FASSERT(pwm); if (pwm->is_running) { - FGpioPinVal new_level = FGPIO_PIN_LOW; + FGpioVal new_level = FGPIO_PIN_LOW; if (pwm->duty > 0) { if (pwm->duty < pwm->range) /*duty means PWM duty ratio*/ @@ -208,23 +210,31 @@ static void PwmClkHandler() int FPinGpioPwmExample(void) { int ret = 0; + + memset(&output_pin_instance_1, 0, sizeof(output_pin_instance_1)); + memset(&output_pin_instance_2, 0, sizeof(output_pin_instance_2)); + + printf("pin1: %d pin2: %d \r\n", output_pin_index_1, output_pin_index_2); + /* init ctrl */ - FGpioConfig input_cfg = *FGpioLookupConfig(pwm_ctrl_id); - ret = FGpioCfgInitialize(&pwm_ctrl_instance, &input_cfg); + FGpioConfig output_pin_1_cfg = *FGpioLookupConfig(output_pin_index_1); + FGpioConfig output_pin_2_cfg = *FGpioLookupConfig(output_pin_index_2); + + ret = FGpioCfgInitialize(&output_pin_instance_1, &output_pin_1_cfg); + FASSERT(ret == FT_SUCCESS); + ret = FGpioCfgInitialize(&output_pin_instance_2, &output_pin_2_cfg); + FASSERT(ret == FT_SUCCESS); + /* init pins */ FIOMuxInit(); - FIOPadSetGpioMux(output_pin_index_1.ctrl, (u32)output_pin_index_1.pin); - FIOPadSetGpioMux(output_pin_index_2.ctrl, (u32)output_pin_index_2.pin); - - ret = FGpioPinInitialize(&pwm_ctrl_instance, &output_pin_instance_1, output_pin_index_1); - ret = FGpioPinInitialize(&pwm_ctrl_instance, &output_pin_instance_2, output_pin_index_2); - - if (ret != 0) - { - printf("Fail to init ctrl or pins."); - goto exit; - } +#if defined(CONFIG_D2000_TEST_BOARD) + FIOPadSetGpioMux(output_pin_1_cfg.ctrl, output_pin_1_cfg.port, (u32)output_pin_1_cfg.pin); + FIOPadSetGpioMux(output_pin_2_cfg.ctrl, output_pin_1_cfg.port, (u32)output_pin_2_cfg.pin); +#else + FIOPadSetGpioMux(output_pin_1_cfg.ctrl, (u32)output_pin_1_cfg.pin); + FIOPadSetGpioMux(output_pin_2_cfg.ctrl, (u32)output_pin_2_cfg.pin); +#endif FGpioSetDirection(&output_pin_instance_1, FGPIO_DIR_OUTPUT); FGpioSetDirection(&output_pin_instance_2, FGPIO_DIR_OUTPUT); @@ -257,7 +267,8 @@ int FPinGpioPwmExample(void) RevokeSysTick(); FPwmStop(&pwm_output_1); FPwmStop(&pwm_output_2); - FGpioDeInitialize(&pwm_ctrl_instance); + FGpioDeInitialize(&output_pin_instance_1); + FGpioDeInitialize(&output_pin_instance_2); exit: /* print message on example run result */ diff --git a/example/peripherals/sd/src/sdif/sdif_sdio_detect_example.c b/example/peripherals/sd/src/sdif/sdif_sdio_detect_example.c index 75fd2f7e8..5860f09f9 100644 --- a/example/peripherals/sd/src/sdif/sdif_sdio_detect_example.c +++ b/example/peripherals/sd/src/sdif/sdif_sdio_detect_example.c @@ -67,10 +67,13 @@ /************************** Variable Definitions *****************************/ static sdmmchost_config_t s_inst_config; static sdmmc_sdio_t s_inst; -static FGpio gpio; +static FGpio gpio_power; +#ifdef CONFIG_PD2308_DEMO_BOARD +static u32 gpio_power_index = FGPIO_ID(FGPIO_CTRL_0, FGPIO_PIN_8); +#else +static u32 gpio_power_index = FGPIO_ID(FGPIO_CTRL_4, FGPIO_PIN_11); +#endif static FGpioConfig gpio_config; -static FGpioPinId PDn_index; -static FGpioPin PDn; /* external PDn assertion */ /***************** Macros (Inline Functions) Definitions *********************/ #define FSD_EXAMPLE_TAG "FSD_EXAMPLE" #define FSD_ERROR(format, ...) FT_DEBUG_PRINT_E(FSD_EXAMPLE_TAG, format, ##__VA_ARGS__) @@ -84,35 +87,21 @@ static FGpioPin PDn; /* external PDn assertion */ /* according to mw8801 tech manual, extern PDn assertion is a way to reset the module */ static void FSdifSdioMW8801PowerUp(void) { -#ifdef CONFIG_PD2308_DEMO_BOARD - gpio_config = *FGpioLookupConfig(FGPIO0_ID); -#else - gpio_config = *FGpioLookupConfig(FGPIO4_ID); -#endif - (void)FGpioCfgInitialize(&gpio, &gpio_config); + gpio_config = *FGpioLookupConfig(gpio_power_index); -#ifdef CONFIG_PD2308_DEMO_BOARD - PDn_index.ctrl = FGPIO0_ID; - PDn_index.port = FGPIO_PORT_A; - PDn_index.pin = FGPIO_PIN_8; -#else - PDn_index.ctrl = FGPIO4_ID; - PDn_index.port = FGPIO_PORT_A; - PDn_index.pin = FGPIO_PIN_11; -#endif + (void)FGpioCfgInitialize(&gpio_power, &gpio_config); - FIOPadSetGpioMux(PDn_index.ctrl, (u32)PDn_index.pin); + FIOPadSetGpioMux(gpio_config.ctrl, (u32)gpio_config.pin); - (void)FGpioPinInitialize(&gpio, &PDn, PDn_index); - (void)FGpioSetDirection(&PDn, FGPIO_DIR_OUTPUT); + (void)FGpioSetDirection(&gpio_power, FGPIO_DIR_OUTPUT); /* transitions from low to high for PDn pin to reset sdio card */ - FGpioSetOutputValue(&PDn, FGPIO_PIN_LOW); + FGpioSetOutputValue(&gpio_power, FGPIO_PIN_LOW); SDMMC_OSADelay(50); - FGpioSetOutputValue(&PDn, FGPIO_PIN_HIGH); + FGpioSetOutputValue(&gpio_power, FGPIO_PIN_HIGH); SDMMC_OSADelay(50); - FGpioDeInitialize(&gpio); + FGpioDeInitialize(&gpio_power); } void FSdifSdioCardIntCallback(void *data) diff --git a/example/peripherals/spi/src/spim_common.c b/example/peripherals/spi/src/spim_common.c index affb12647..9bfd3175d 100644 --- a/example/peripherals/spi/src/spim_common.c +++ b/example/peripherals/spi/src/spim_common.c @@ -49,22 +49,14 @@ static boolean is_ready = FALSE; #if defined(CONFIG_D2000_TEST_BOARD) || defined(CONFIG_FT2004_DSK_BOARD) #include "fgpio.h" /* D2000/FT2000-4 使用GPIO引脚控制片选信号 */ -static FGpioPinId cs_pin_id = -{ - .ctrl = FGPIO1_ID, - .port = FGPIO_PORT_A, - .pin = FGPIO_PIN_5 -}; - +static u32 cs_pin_id = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_5); static FGpio gpio; -static FGpioPin cs_pin; static void FSpimSetupCs(void) { - FGpioConfig input_cfg = *FGpioLookupConfig(cs_pin_id.ctrl); + FGpioConfig input_cfg = *FGpioLookupConfig(cs_pin_id); (void)FGpioCfgInitialize(&gpio, &input_cfg); - (void)FGpioPinInitialize(&gpio, &cs_pin, cs_pin_id); - FGpioSetDirection(&cs_pin, FGPIO_DIR_OUTPUT); + FGpioSetDirection(&gpio, FGPIO_DIR_OUTPUT); return; } @@ -73,11 +65,11 @@ void FSpimCsOnOff(boolean on) { if (on) { - FGpioSetOutputValue(&cs_pin, FGPIO_PIN_LOW); + FGpioSetOutputValue(&gpio, FGPIO_PIN_LOW); } else { - FGpioSetOutputValue(&cs_pin, FGPIO_PIN_HIGH); + FGpioSetOutputValue(&gpio, FGPIO_PIN_HIGH); } } #else @@ -192,9 +184,9 @@ int FSpimOpsDeInit(void) /*deinit iopad*/ FIOMuxDeInit(); #if defined(CONFIG_D2000_TEST_BOARD) || defined(CONFIG_FT2004_DSK_BOARD) -if (FT_COMPONENT_IS_READY == cs_pin.is_ready) +if (FT_COMPONENT_IS_READY == gpio.is_ready) { - FGpioPinDeInitialize(&cs_pin); + FGpioDeInitialize(&gpio); } #endif is_ready = FALSE; diff --git a/soc/d2000/fgpio_table.c b/soc/d2000/fgpio_table.c new file mode 100644 index 000000000..0949698af --- /dev/null +++ b/soc/d2000/fgpio_table.c @@ -0,0 +1,121 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fgpio_table.c + * Date: 2023-11-6 10:33:28 + * LastEditTime: 2023-11-6 10:33:28 + * Description:  This file is for GPIO pin definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/5/9 init commit + */ + +#include "fparameters.h" +#include "fgpio.h" + +#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \ + { \ + .id = FGPIO_ID(_ctrl, _port, _pin), \ + .ctrl = _ctrl, \ + .port = _port, \ + .pin = _pin, \ + .base_addr = _base, \ + .irq_num = _irq, \ + .cap = _cap \ + } + +#define FGPIO_PIN_CONFIG_0_A(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_0_B(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_B, (pin), (irq), FGPIO_CAP_IRQ_NONE) +#define FGPIO_PIN_CONFIG_1_A(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_1_B(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_B, (pin), (irq), FGPIO_CAP_IRQ_NONE) + +const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = +{ + /* GPIO 0-A, IRQ 42 */ + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_0, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_1, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_2, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_3, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_4, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_5, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_6, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_7, 42U), + + /* GPIO 0-B, None IRQ */ + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_0, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_1, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_2, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_3, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_4, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_5, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_6, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_7, 0U), + + /* GPIO 1-A IRQ 43 */ + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_0, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_1, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_2, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_3, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_4, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_5, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_6, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_7, 43U), + + /* GPIO 1-B None IRQ */ + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_0, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_1, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_2, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_3, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_4, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_5, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_6, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_7, 0U) +}; + +#define FGPIO_INTR_MAP_CONFIG(_base) \ + { \ + .base_addr = _base, \ + .irq_cbs = {NULL}, \ + .irq_cb_params = {NULL},\ + } + +FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] = +{ + /* GPIO 0 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR), + + /* GPIO 1 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR) +}; + +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num) +{ + u32 index; + const FGpioConfig *ptr = NULL; + + for (index = 0; index < FGPIO_NUM; index++) + { + /* 如果引脚单独上报中断，返回对应引脚的配置 + 如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置 + 如果引脚不支持中断，返回 NULL */ + if (fgpio_cfg_tbl[index].irq_num == irq_num) + { + ptr = &fgpio_cfg_tbl[index]; + break; + } + } + + return ptr; +} \ No newline at end of file diff --git a/soc/d2000/fparameters.h b/soc/d2000/fparameters.h index b63dc839a..eb56ce227 100644 --- a/soc/d2000/fparameters.h +++ b/soc/d2000/fparameters.h @@ -184,29 +184,34 @@ extern "C" #define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ /* GPIO */ -#define FGPIO_PORT_A_B_TYPE /* include A and B port */ #define FGPIO0_BASE_ADDR (0x28004000) #define FGPIO1_BASE_ADDR (0x28005000) -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO_NUM 2 +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_NUM 2U -/* gpio特性 -bit0： 中断类型，1表示单独中断，0表示合成中断 -bit1： port分组，1表示有port a/b分组，0表示无分组 - */ -#define FGPIO_CAPACITY_IRQ_TYPE BIT(0) -#define FGPIO_CAPACITY_PORT_TYPE BIT(1) +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_B 1U +#define FGPIO_PORT_NUM 2U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_NUM 8U -#define FGPIO0_CAPACITY FGPIO_CAPACITY_PORT_TYPE -#define FGPIO1_CAPACITY FGPIO_CAPACITY_PORT_TYPE +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) -#define FGPIO_CTRL_PIN_NUM 8U -#define FGPIO_PIN_IRQ_BASE 42U +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ -#define FGPIO_0_IRQ_NUM (42) /* gpio0 irq number */ -#define FGPIO_1_IRQ_NUM (43) /* gpio1 irq number */ +#define FGPIO_ID(ctrl, port, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((port) * FGPIO_PIN_NUM) + (pin)) /* IOCTRL */ #define FIOCTRL_BASE_ADDR 0x28180000 @@ -242,6 +247,11 @@ bit1： port分组，1表示有port a/b分组，0表示无分组 #define FIOCTRL_HDT_MB_DONE_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x204, 0) /* i2c3-scl: func 2 */ #define FIOCTRL_HDT_MB_FAIL_STATE_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 28) /* i2c3-sda: func 2 */ +#define FIOCTRL_SPI0_CSN0_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 16) /* gpio1_a_5: func 2 */ +#define FIOCTRL_SPI0_SCK_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 12) /* gpio1_a_6: func 2 */ +#define FIOCTRL_SPI0_SO_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 8) /* gpio1_a_7: func 2 */ +#define FIOCTRL_SPI0_SI_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x208, 4) /* gpio1_b_0: func 2 */ + #define FIOCTRL_UART_2_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x210, 0) /* spi1_csn0: func 1 */ #define FIOCTRL_UART_2_TXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 28) /* spi1_sck: func 1 */ #define FIOCTRL_UART_3_RXD_PAD (FIOCtrlPinIndex)FIOCTRL_INDEX(0x214, 24) /* spi1_so: func 1 */ diff --git a/soc/d2000/src.mk b/soc/d2000/src.mk index 65498391a..6b724558e 100644 --- a/soc/d2000/src.mk +++ b/soc/d2000/src.mk @@ -2,3 +2,7 @@ SOC_CSRCS += \ fmmu_table.c\ fcpu_affinity_mask.c + +ifeq ($(CONFIG_ENABLE_FGPIO),y) +SOC_CSRCS += fgpio_table.c +endif \ No newline at end of file diff --git a/soc/e2000/fgpio_table.c b/soc/e2000/fgpio_table.c new file mode 100644 index 000000000..79215bc73 --- /dev/null +++ b/soc/e2000/fgpio_table.c @@ -0,0 +1,203 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fgpio_table.c + * Date: 2023-11-6 10:33:28 + * LastEditTime: 2023-11-6 10:33:28 + * Description:  This file is for GPIO pin definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/5/9 init commit + */ + +#include "fparameters.h" +#include "fgpio.h" + +#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \ + { \ + .id = FGPIO_ID(_ctrl, _pin), \ + .ctrl = _ctrl, \ + .port = _port, \ + .pin = _pin, \ + .base_addr = _base, \ + .irq_num = _irq, \ + .cap = _cap \ + } + +#define FGPIO_PIN_CONFIG_0(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_1(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_2(pin, irq) FGPIO_PIN_CONFIG(FGPIO2_BASE_ADDR, FGPIO_CTRL_2, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_3(pin, irq) FGPIO_PIN_CONFIG(FGPIO3_BASE_ADDR, FGPIO_CTRL_3, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_4(pin, irq) FGPIO_PIN_CONFIG(FGPIO4_BASE_ADDR, FGPIO_CTRL_4, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_5(pin, irq) FGPIO_PIN_CONFIG(FGPIO5_BASE_ADDR, FGPIO_CTRL_5, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) + +const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = +{ + /* GPIO 0, IRQ 140 ~ 155 */ + FGPIO_PIN_CONFIG_0(FGPIO_PIN_0, 140U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_1, 141U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_2, 142U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_3, 143U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_4, 144U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_5, 145U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_6, 146U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_7, 147U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_8, 148U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_9, 149U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_10, 150U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_11, 151U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_12, 152U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_13, 153U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_14, 154U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_15, 155U), + + /* GPIO 1, IRQ 156 ~ 171 */ + FGPIO_PIN_CONFIG_1(FGPIO_PIN_0, 156U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_1, 157U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_2, 158U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_3, 159U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_4, 160U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_5, 161U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_6, 162U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_7, 163U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_8, 164U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_9, 165U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_10, 166U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_11, 167U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_12, 168U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_13, 169U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_14, 170U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_15, 171U), + + /* GPIO 2, IRQ 172 ~ 187 */ + FGPIO_PIN_CONFIG_2(FGPIO_PIN_0, 172U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_1, 173U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_2, 174U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_3, 175U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_4, 176U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_5, 177U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_6, 178U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_7, 179U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_8, 180U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_9, 181U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_10, 182U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_11, 183U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_12, 184U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_13, 185U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_14, 186U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_15, 187U), + + /* GPIO 3, IRQ 188 */ + FGPIO_PIN_CONFIG_3(FGPIO_PIN_0, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_1, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_2, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_3, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_4, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_5, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_6, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_7, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_8, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_9, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_10, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_11, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_12, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_13, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_14, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_15, 188U), + + /* GPIO 4, IRQ 189 */ + FGPIO_PIN_CONFIG_4(FGPIO_PIN_0, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_1, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_2, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_3, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_4, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_5, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_6, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_7, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_8, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_9, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_10, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_11, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_12, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_13, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_14, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_15, 189U), + + /* GPIO 5, IRQ 190 */ + FGPIO_PIN_CONFIG_5(FGPIO_PIN_0, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_1, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_2, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_3, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_4, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_5, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_6, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_7, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_8, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_9, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_10, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_11, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_12, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_13, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_14, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_15, 190U) +}; + +#define FGPIO_INTR_MAP_CONFIG(_base) \ + { \ + .base_addr = _base, \ + .irq_cbs = {NULL}, \ + .irq_cb_params = {NULL},\ + } + +FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] = +{ + /* GPIO 0 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR), + + /* GPIO 1 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR), + + /* GPIO 2 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO2_BASE_ADDR), + + /* GPIO 3 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO3_BASE_ADDR), + + /* GPIO 4 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO4_BASE_ADDR), + + /* GPIO 5 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO5_BASE_ADDR) +}; + +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num) +{ + u32 index; + const FGpioConfig *ptr = NULL; + + for (index = 0; index < FGPIO_NUM; index++) + { + /* 如果引脚单独上报中断，返回对应引脚的配置 + 如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置 + 如果引脚不支持中断，返回 NULL */ + if (fgpio_cfg_tbl[index].irq_num == irq_num) + { + ptr = &fgpio_cfg_tbl[index]; + break; + } + } + + return ptr; +} \ No newline at end of file diff --git a/soc/e2000/fparameters_comm.h b/soc/e2000/fparameters_comm.h index ab211d356..36c0406d0 100644 --- a/soc/e2000/fparameters_comm.h +++ b/soc/e2000/fparameters_comm.h @@ -228,28 +228,6 @@ extern "C" #define GICV3_RD_SIZE (8U << 16) /* GPIO */ -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO2_ID 2 -#define FGPIO3_ID 3 -#define FGPIO4_ID 4 -#define FGPIO5_ID 5 -#define FGPIO_NUM 6 - -/* gpio特性 -bit0： 中断类型，1表示单独中断，0表示合成中断 -bit1： port分组，1表示有port a/b分组，0表示无分组 - */ -#define FGPIO_CAPACITY_IRQ_TYPE BIT(0) -#define FGPIO_CAPACITY_PORT_TYPE BIT(1) - -#define FGPIO0_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO1_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO2_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO3_CAPACITY 0 -#define FGPIO4_CAPACITY 0 -#define FGPIO5_CAPACITY 0 - #define FGPIO0_BASE_ADDR 0x28034000U #define FGPIO1_BASE_ADDR 0x28035000U #define FGPIO2_BASE_ADDR 0x28036000U @@ -257,15 +235,42 @@ bit1： port分组，1表示有port a/b分组，0表示无分组 #define FGPIO4_BASE_ADDR 0x28038000U #define FGPIO5_BASE_ADDR 0x28039000U -#define FGPIO_CTRL_PIN_NUM 16U -#define FGPIO_PIN_IRQ_BASE 140U - - -#define FGPIO_3_IRQ_NUM 188U -#define FGPIO_4_IRQ_NUM 189U -#define FGPIO_5_IRQ_NUM 190U - -#define FGPIO_PIN_IRQ_TOTAL 51U +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_4 4 +#define FGPIO_CTRL_5 5 +#define FGPIO_CTRL_NUM 6U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) /* SPI */ #define FSPI0_BASE_ADDR 0x2803A000U diff --git a/soc/e2000/src.mk b/soc/e2000/src.mk index 6a4653a46..676b3a37e 100644 --- a/soc/e2000/src.mk +++ b/soc/e2000/src.mk @@ -3,3 +3,7 @@ SOC_TYPE_NAME := $(subst ",,$(CONFIG_TARGET_TYPE_NAME)) SOC_CSRCS += $(SOC_TYPE_NAME)/fmmu_table.c\ $(SOC_TYPE_NAME)/fcpu_affinity_mask.c + +ifeq ($(CONFIG_ENABLE_FGPIO),y) +SOC_CSRCS += fgpio_table.c +endif \ No newline at end of file diff --git a/soc/ft2004/fgpio_table.c b/soc/ft2004/fgpio_table.c new file mode 100644 index 000000000..0949698af --- /dev/null +++ b/soc/ft2004/fgpio_table.c @@ -0,0 +1,121 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fgpio_table.c + * Date: 2023-11-6 10:33:28 + * LastEditTime: 2023-11-6 10:33:28 + * Description:  This file is for GPIO pin definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/5/9 init commit + */ + +#include "fparameters.h" +#include "fgpio.h" + +#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \ + { \ + .id = FGPIO_ID(_ctrl, _port, _pin), \ + .ctrl = _ctrl, \ + .port = _port, \ + .pin = _pin, \ + .base_addr = _base, \ + .irq_num = _irq, \ + .cap = _cap \ + } + +#define FGPIO_PIN_CONFIG_0_A(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_0_B(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_B, (pin), (irq), FGPIO_CAP_IRQ_NONE) +#define FGPIO_PIN_CONFIG_1_A(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_1_B(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_B, (pin), (irq), FGPIO_CAP_IRQ_NONE) + +const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = +{ + /* GPIO 0-A, IRQ 42 */ + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_0, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_1, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_2, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_3, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_4, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_5, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_6, 42U), + FGPIO_PIN_CONFIG_0_A(FGPIO_PIN_7, 42U), + + /* GPIO 0-B, None IRQ */ + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_0, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_1, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_2, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_3, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_4, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_5, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_6, 0U), + FGPIO_PIN_CONFIG_0_B(FGPIO_PIN_7, 0U), + + /* GPIO 1-A IRQ 43 */ + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_0, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_1, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_2, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_3, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_4, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_5, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_6, 43U), + FGPIO_PIN_CONFIG_1_A(FGPIO_PIN_7, 43U), + + /* GPIO 1-B None IRQ */ + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_0, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_1, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_2, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_3, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_4, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_5, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_6, 0U), + FGPIO_PIN_CONFIG_1_B(FGPIO_PIN_7, 0U) +}; + +#define FGPIO_INTR_MAP_CONFIG(_base) \ + { \ + .base_addr = _base, \ + .irq_cbs = {NULL}, \ + .irq_cb_params = {NULL},\ + } + +FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] = +{ + /* GPIO 0 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR), + + /* GPIO 1 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR) +}; + +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num) +{ + u32 index; + const FGpioConfig *ptr = NULL; + + for (index = 0; index < FGPIO_NUM; index++) + { + /* 如果引脚单独上报中断，返回对应引脚的配置 + 如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置 + 如果引脚不支持中断，返回 NULL */ + if (fgpio_cfg_tbl[index].irq_num == irq_num) + { + ptr = &fgpio_cfg_tbl[index]; + break; + } + } + + return ptr; +} \ No newline at end of file diff --git a/soc/ft2004/fparameters.h b/soc/ft2004/fparameters.h index 011440a58..023e78d4f 100644 --- a/soc/ft2004/fparameters.h +++ b/soc/ft2004/fparameters.h @@ -149,30 +149,36 @@ extern "C" #define GICV3_RD_OFFSET (2U << 16) #define GICV3_RD_SIZE (8U << 16) -/* GPIO */ -#define FGPIO_PORT_A_B_TYPE /* include A and B port */ -#define FGPIO0_BASE_ADDR 0x28004000 -#define FGPIO1_BASE_ADDR 0x28005000 - -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO_NUM 2 - -/* gpio特性 -bit0： 中断类型，1表示单独中断，0表示合成中断 -bit1： port分组，1表示有port a/b分组，0表示无分组 - */ -#define FGPIO_CAPACITY_IRQ_TYPE BIT(0) -#define FGPIO_CAPACITY_PORT_TYPE BIT(1) -#define FGPIO0_CAPACITY FGPIO_CAPACITY_PORT_TYPE -#define FGPIO1_CAPACITY FGPIO_CAPACITY_PORT_TYPE - -#define FGPIO_CTRL_PIN_NUM 8U -#define FGPIO_PIN_IRQ_BASE 42U - -#define FGPIO0_IRQ_NUM 42 /* gpio0 irq number */ -#define FGPIO1_IRQ_NUM 43 /* gpio1 irq number */ +/* GPIO */ +#define FGPIO0_BASE_ADDR (0x28004000) +#define FGPIO1_BASE_ADDR (0x28005000) + +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_NUM 2U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_B 1U +#define FGPIO_PORT_NUM 2U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_NUM 8U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, port, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((port) * FGPIO_PIN_NUM) + (pin)) /* SPI */ #define FSPI0_BASE_ADDR 0x2800c000 diff --git a/soc/ft2004/src.mk b/soc/ft2004/src.mk index 65498391a..6b724558e 100644 --- a/soc/ft2004/src.mk +++ b/soc/ft2004/src.mk @@ -2,3 +2,7 @@ SOC_CSRCS += \ fmmu_table.c\ fcpu_affinity_mask.c + +ifeq ($(CONFIG_ENABLE_FGPIO),y) +SOC_CSRCS += fgpio_table.c +endif \ No newline at end of file diff --git a/soc/pd2308/fgpio_table.c b/soc/pd2308/fgpio_table.c new file mode 100644 index 000000000..eb5db9ed5 --- /dev/null +++ b/soc/pd2308/fgpio_table.c @@ -0,0 +1,160 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fgpio_table.c + * Date: 2023-11-6 10:33:28 + * LastEditTime: 2023-11-6 10:33:28 + * Description:  This file is for GPIO pin definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/5/9 init commit + */ + +#include "fparameters.h" +#include "fgpio.h" + +#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \ + { \ + .id = FGPIO_ID(_ctrl, _pin), \ + .ctrl = _ctrl, \ + .port = _port, \ + .pin = _pin, \ + .base_addr = _base, \ + .irq_num = _irq, \ + .cap = _cap \ + } + +#define FGPIO_PIN_CONFIG_0(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_1(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_2(pin, irq) FGPIO_PIN_CONFIG(FGPIO2_BASE_ADDR, FGPIO_CTRL_2, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_3(pin, irq) FGPIO_PIN_CONFIG(FGPIO3_BASE_ADDR, FGPIO_CTRL_3, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) + +const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = +{ + /* GPIO-0, IRQ 128 ~ 143 */ + FGPIO_PIN_CONFIG_0(FGPIO_PIN_0, 128U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_1, 129U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_2, 130U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_3, 131U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_4, 132U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_5, 133U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_6, 134U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_7, 135U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_8, 136U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_9, 137U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_10, 138U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_11, 139U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_12, 140U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_13, 141U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_14, 142U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_15, 143U), + + /* GPIO-1, IRQ 144 ~ 159 */ + FGPIO_PIN_CONFIG_1(FGPIO_PIN_0, 144U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_1, 145U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_2, 146U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_3, 147U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_4, 148U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_5, 149U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_6, 150U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_7, 151U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_8, 152U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_9, 153U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_10, 154U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_11, 155U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_12, 156U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_13, 157U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_14, 158U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_15, 159U), + + /* GPIO-2, IRQ 160 */ + FGPIO_PIN_CONFIG_2(FGPIO_PIN_0, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_1, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_2, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_3, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_4, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_5, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_6, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_7, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_8, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_9, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_10, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_11, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_12, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_13, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_14, 160U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_15, 160U), + + /* GPIO-3 IRQ 161 */ + FGPIO_PIN_CONFIG_3(FGPIO_PIN_0, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_1, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_2, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_3, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_4, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_5, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_6, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_7, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_8, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_9, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_10, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_11, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_12, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_13, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_14, 161U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_15, 161U) +}; + + +#define FGPIO_INTR_MAP_CONFIG(_base) \ + { \ + .base_addr = _base, \ + .irq_cbs = {NULL}, \ + .irq_cb_params = {NULL},\ + } + +FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] = +{ + /* GPIO 0 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR), + + /* GPIO 1 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR), + + /* GPIO 2 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO2_BASE_ADDR), + + /* GPIO 3 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO3_BASE_ADDR) +}; + +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num) +{ + u32 index; + const FGpioConfig *ptr = NULL; + + for (index = 0; index < FGPIO_NUM; index++) + { + /* 如果引脚单独上报中断，返回对应引脚的配置 + 如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置 + 如果引脚不支持中断，返回 NULL */ + if (fgpio_cfg_tbl[index].irq_num == irq_num) + { + ptr = &fgpio_cfg_tbl[index]; + break; + } + } + + return ptr; +} \ No newline at end of file diff --git a/soc/pd2308/fparameters.h b/soc/pd2308/fparameters.h index 80423afed..89bef6114 100644 --- a/soc/pd2308/fparameters.h +++ b/soc/pd2308/fparameters.h @@ -451,44 +451,47 @@ enum /* GPIO */ -#if !defined(__ASSEMBLER__) -enum -{ - FGPIO0_ID = 0, - FGPIO1_ID = 1, - FGPIO2_ID, - FGPIO3_ID, - - FGPIO_NUM -}; -#endif - -/* gpio特性 -bit0： 中断类型，1表示单独中断，0表示合成中断 -bit1： port分组，1表示有port a/b分组，0表示无分组 - */ -#define FGPIO_CAPACITY_IRQ_TYPE BIT(0) -#define FGPIO_CAPACITY_PORT_TYPE BIT(1) - -#define FGPIO0_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO1_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO2_CAPACITY 0 -#define FGPIO3_CAPACITY 0 - #define FGPIO0_BASE_ADDR 0x2800E000U #define FGPIO1_BASE_ADDR 0x2800F000U #define FGPIO2_BASE_ADDR 0x28010000U #define FGPIO3_BASE_ADDR 0x28011000U -#define FGPIO_CTRL_PIN_NUM 16U -#define FGPIO_PIN_IRQ_BASE 128U - - -#define FGPIO_2_IRQ_NUM 160U -#define FGPIO_3_IRQ_NUM 161U - -#define FGPIO_PIN_IRQ_TOTAL 34U - +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_NUM 4U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) + +#define FGPIO_CLK_FREQ_HZ (50000000UL) /* 50MHz */ /* generic timer */ /* non-secure physical timer int id */ diff --git a/soc/pd2308/src.mk b/soc/pd2308/src.mk index 65498391a..6b724558e 100644 --- a/soc/pd2308/src.mk +++ b/soc/pd2308/src.mk @@ -2,3 +2,7 @@ SOC_CSRCS += \ fmmu_table.c\ fcpu_affinity_mask.c + +ifeq ($(CONFIG_ENABLE_FGPIO),y) +SOC_CSRCS += fgpio_table.c +endif \ No newline at end of file diff --git a/soc/phytiumpi/fgpio_table.c b/soc/phytiumpi/fgpio_table.c new file mode 100644 index 000000000..79215bc73 --- /dev/null +++ b/soc/phytiumpi/fgpio_table.c @@ -0,0 +1,203 @@ +/* + * Copyright : (C) 2024 Phytium Information Technology, Inc. + * All Rights Reserved. + * + * This program is OPEN SOURCE software: you can redistribute it and/or modify it + * under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd, + * either version 1.0 of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the Phytium Public License for more details. + * + * + * FilePath: fgpio_table.c + * Date: 2023-11-6 10:33:28 + * LastEditTime: 2023-11-6 10:33:28 + * Description:  This file is for GPIO pin definition + * + * Modify History: + * Ver   Who        Date         Changes + * ----- ------     --------    -------------------------------------- + * 1.0 zhugengyu 2024/5/9 init commit + */ + +#include "fparameters.h" +#include "fgpio.h" + +#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \ + { \ + .id = FGPIO_ID(_ctrl, _pin), \ + .ctrl = _ctrl, \ + .port = _port, \ + .pin = _pin, \ + .base_addr = _base, \ + .irq_num = _irq, \ + .cap = _cap \ + } + +#define FGPIO_PIN_CONFIG_0(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_1(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_2(pin, irq) FGPIO_PIN_CONFIG(FGPIO2_BASE_ADDR, FGPIO_CTRL_2, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN) +#define FGPIO_PIN_CONFIG_3(pin, irq) FGPIO_PIN_CONFIG(FGPIO3_BASE_ADDR, FGPIO_CTRL_3, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_4(pin, irq) FGPIO_PIN_CONFIG(FGPIO4_BASE_ADDR, FGPIO_CTRL_4, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) +#define FGPIO_PIN_CONFIG_5(pin, irq) FGPIO_PIN_CONFIG(FGPIO5_BASE_ADDR, FGPIO_CTRL_5, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL) + +const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] = +{ + /* GPIO 0, IRQ 140 ~ 155 */ + FGPIO_PIN_CONFIG_0(FGPIO_PIN_0, 140U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_1, 141U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_2, 142U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_3, 143U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_4, 144U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_5, 145U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_6, 146U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_7, 147U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_8, 148U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_9, 149U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_10, 150U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_11, 151U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_12, 152U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_13, 153U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_14, 154U), + FGPIO_PIN_CONFIG_0(FGPIO_PIN_15, 155U), + + /* GPIO 1, IRQ 156 ~ 171 */ + FGPIO_PIN_CONFIG_1(FGPIO_PIN_0, 156U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_1, 157U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_2, 158U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_3, 159U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_4, 160U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_5, 161U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_6, 162U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_7, 163U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_8, 164U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_9, 165U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_10, 166U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_11, 167U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_12, 168U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_13, 169U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_14, 170U), + FGPIO_PIN_CONFIG_1(FGPIO_PIN_15, 171U), + + /* GPIO 2, IRQ 172 ~ 187 */ + FGPIO_PIN_CONFIG_2(FGPIO_PIN_0, 172U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_1, 173U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_2, 174U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_3, 175U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_4, 176U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_5, 177U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_6, 178U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_7, 179U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_8, 180U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_9, 181U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_10, 182U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_11, 183U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_12, 184U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_13, 185U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_14, 186U), + FGPIO_PIN_CONFIG_2(FGPIO_PIN_15, 187U), + + /* GPIO 3, IRQ 188 */ + FGPIO_PIN_CONFIG_3(FGPIO_PIN_0, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_1, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_2, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_3, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_4, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_5, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_6, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_7, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_8, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_9, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_10, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_11, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_12, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_13, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_14, 188U), + FGPIO_PIN_CONFIG_3(FGPIO_PIN_15, 188U), + + /* GPIO 4, IRQ 189 */ + FGPIO_PIN_CONFIG_4(FGPIO_PIN_0, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_1, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_2, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_3, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_4, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_5, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_6, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_7, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_8, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_9, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_10, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_11, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_12, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_13, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_14, 189U), + FGPIO_PIN_CONFIG_4(FGPIO_PIN_15, 189U), + + /* GPIO 5, IRQ 190 */ + FGPIO_PIN_CONFIG_5(FGPIO_PIN_0, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_1, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_2, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_3, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_4, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_5, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_6, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_7, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_8, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_9, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_10, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_11, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_12, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_13, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_14, 190U), + FGPIO_PIN_CONFIG_5(FGPIO_PIN_15, 190U) +}; + +#define FGPIO_INTR_MAP_CONFIG(_base) \ + { \ + .base_addr = _base, \ + .irq_cbs = {NULL}, \ + .irq_cb_params = {NULL},\ + } + +FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] = +{ + /* GPIO 0 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR), + + /* GPIO 1 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR), + + /* GPIO 2 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO2_BASE_ADDR), + + /* GPIO 3 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO3_BASE_ADDR), + + /* GPIO 4 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO4_BASE_ADDR), + + /* GPIO 5 IRQ Map */ + FGPIO_INTR_MAP_CONFIG(FGPIO5_BASE_ADDR) +}; + +const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num) +{ + u32 index; + const FGpioConfig *ptr = NULL; + + for (index = 0; index < FGPIO_NUM; index++) + { + /* 如果引脚单独上报中断，返回对应引脚的配置 + 如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置 + 如果引脚不支持中断，返回 NULL */ + if (fgpio_cfg_tbl[index].irq_num == irq_num) + { + ptr = &fgpio_cfg_tbl[index]; + break; + } + } + + return ptr; +} \ No newline at end of file diff --git a/soc/phytiumpi/fparameters_comm.h b/soc/phytiumpi/fparameters_comm.h index b1a28267e..8e0eff792 100644 --- a/soc/phytiumpi/fparameters_comm.h +++ b/soc/phytiumpi/fparameters_comm.h @@ -190,28 +190,6 @@ extern "C" #define GICV3_RD_SIZE (8U << 16) /* GPIO */ -#define FGPIO0_ID 0 -#define FGPIO1_ID 1 -#define FGPIO2_ID 2 -#define FGPIO3_ID 3 -#define FGPIO4_ID 4 -#define FGPIO5_ID 5 -#define FGPIO_NUM 6 - -/* gpio特性 -bit0： 中断类型，1表示单独中断，0表示合成中断 -bit1： port分组，1表示有port a/b分组，0表示无分组 - */ -#define FGPIO_CAPACITY_IRQ_TYPE BIT(0) -#define FGPIO_CAPACITY_PORT_TYPE BIT(1) - -#define FGPIO0_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO1_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO2_CAPACITY FGPIO_CAPACITY_IRQ_TYPE -#define FGPIO3_CAPACITY 0 -#define FGPIO4_CAPACITY 0 -#define FGPIO5_CAPACITY 0 - #define FGPIO0_BASE_ADDR 0x28034000U #define FGPIO1_BASE_ADDR 0x28035000U #define FGPIO2_BASE_ADDR 0x28036000U @@ -219,15 +197,42 @@ bit1： port分组，1表示有port a/b分组，0表示无分组 #define FGPIO4_BASE_ADDR 0x28038000U #define FGPIO5_BASE_ADDR 0x28039000U -#define FGPIO_CTRL_PIN_NUM 16U -#define FGPIO_PIN_IRQ_BASE 140U - - -#define FGPIO_3_IRQ_NUM 188U -#define FGPIO_4_IRQ_NUM 189U -#define FGPIO_5_IRQ_NUM 190U - -#define FGPIO_PIN_IRQ_TOTAL 51U +#define FGPIO_CTRL_0 0 +#define FGPIO_CTRL_1 1 +#define FGPIO_CTRL_2 2 +#define FGPIO_CTRL_3 3 +#define FGPIO_CTRL_4 4 +#define FGPIO_CTRL_5 5 +#define FGPIO_CTRL_NUM 6U + +#define FGPIO_PORT_A 0U +#define FGPIO_PORT_NUM 1U + +#define FGPIO_PIN_0 0U +#define FGPIO_PIN_1 1U +#define FGPIO_PIN_2 2U +#define FGPIO_PIN_3 3U +#define FGPIO_PIN_4 4U +#define FGPIO_PIN_5 5U +#define FGPIO_PIN_6 6U +#define FGPIO_PIN_7 7U +#define FGPIO_PIN_8 8U +#define FGPIO_PIN_9 9U +#define FGPIO_PIN_10 10U +#define FGPIO_PIN_11 11U +#define FGPIO_PIN_12 12U +#define FGPIO_PIN_13 13U +#define FGPIO_PIN_14 14U +#define FGPIO_PIN_15 15U +#define FGPIO_PIN_NUM 16U + +#define FGPIO_NUM (FGPIO_CTRL_NUM * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + +#define FGPIO_CAP_IRQ_BY_PIN (1 << 0) /* 支持外部中断，每个引脚有单独上报的中断 */ +#define FGPIO_CAP_IRQ_BY_CTRL (1 << 1) /* 支持外部中断，引脚中断统一上报 */ +#define FGPIO_CAP_IRQ_NONE (1 << 2) /* 不支持外部中断 */ + +#define FGPIO_ID(ctrl, pin) (((ctrl) * FGPIO_PORT_NUM * FGPIO_PIN_NUM) + ((FGPIO_PORT_A) * FGPIO_PIN_NUM) + (pin)) /* SPI */ #define FSPI0_BASE_ADDR 0x2803A000U diff --git a/soc/phytiumpi/src.mk b/soc/phytiumpi/src.mk index 1cf313cbf..f72e615a1 100644 --- a/soc/phytiumpi/src.mk +++ b/soc/phytiumpi/src.mk @@ -5,3 +5,7 @@ SOC_TYPE_NAME := $(subst ",,$(CONFIG_TARGET_TYPE_NAME)) SOC_CSRCS += \ fmmu_table.c\ fcpu_affinity_mask.c + +ifeq ($(CONFIG_ENABLE_FGPIO),y) +SOC_CSRCS += fgpio_table.c +endif \ No newline at end of file diff --git a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c index aebc87e4f..f3d377c09 100644 --- a/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c +++ b/third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c @@ -92,7 +92,6 @@ typedef struct FSpim spim; #if defined(CONFIG_D2000_TEST_BOARD) || defined(CONFIG_FT2004_DSK_BOARD) FGpio gpio; - FGpioPin cs_pin; #endif } FSpimCore; @@ -101,34 +100,27 @@ static FSpimCore fspim[FSPI_NUM] = {0} ; #if defined(CONFIG_D2000_TEST_BOARD) || defined(CONFIG_FT2004_DSK_BOARD) /* 使用GPIO引脚控制片选信号 */ -static FGpioPinId cs_pin_id = -{ - .ctrl = FGPIO1_ID, - .port = FGPIO_PORT_A, - .pin = FGPIO_PIN_5 -}; +static u32 cs_pin_id = FGPIO_ID(FGPIO_CTRL_1, FGPIO_PORT_A, FGPIO_PIN_5); static int SfudSpiPortSetupCs(FSpimCore *core_p) { - FGpioConfig input_cfg = *FGpioLookupConfig(FGPIO1_ID); + FGpioConfig input_cfg = *FGpioLookupConfig(cs_pin_id); FGpio *gpio_p = &core_p->gpio; - FGpioPin *cs_p = &core_p->cs_pin; FError ret = FSPIM_SUCCESS; (void)FGpioCfgInitialize(gpio_p, &input_cfg); - (void)FGpioPinInitialize(gpio_p, cs_p, cs_pin_id); - FGpioSetDirection(cs_p, FGPIO_DIR_OUTPUT); + FGpioSetDirection(gpio_p, FGPIO_DIR_OUTPUT); return SFUD_SUCCESS; } static void SfudSpiPortCsOnOff(FSpimCore *core_p, boolean on) { - FGpioPin *cs_p = &core_p->cs_pin; + FGpio *gpio = &core_p->gpio; if (on) - FGpioSetOutputValue(cs_p, FGPIO_PIN_LOW); + FGpioSetOutputValue(gpio, FGPIO_PIN_LOW); else - FGpioSetOutputValue(cs_p, FGPIO_PIN_HIGH); + FGpioSetOutputValue(gpio, FGPIO_PIN_HIGH); } #else diff --git a/tools/export_ide/gen_proj.bat b/tools/export_ide/gen_proj.bat index d84478666..df2c78d4c 100644 --- a/tools/export_ide/gen_proj.bat +++ b/tools/export_ide/gen_proj.bat @@ -1,14 +1,15 @@ @echo off setlocal enabledelayedexpansion -set current=%CD% +set BAT_PATH=%~dp0 + if not defined PYTHON ( - set PYTHON=%current%\..\..\..\phytium-rtos-dev-tools\Python38\python + set PYTHON=%BAT_PATH%\..\..\..\phytium-rtos-dev-tools\Python38\python ) -set make_path=%current%\..\..\..\phytium-rtos-dev-tools\xpack-windows-build-tools-4.3.0-1\bin +set make_path=%BAT_PATH%\..\..\..\phytium-rtos-dev-tools\xpack-windows-build-tools-4.3.0-1\bin set PATH=%PATH%;%make_path% -set "root_dir=../../example" +set "example_path=%BAT_PATH%../../example" -call :traverseSubfolders "%root_dir%" +call :traverseSubfolders "%example_path%" goto :eof :traverseSubfolders diff --git a/tools/export_ide/gen_proj.py b/tools/export_ide/gen_proj.py index a14a897ea..ec08d65dd 100644 --- a/tools/export_ide/gen_proj.py +++ b/tools/export_ide/gen_proj.py @@ -60,6 +60,47 @@ def copy_if_exists(src_file, dest_file): os.makedirs(path) shutil.copy2(src_file, dest_file) + +def copy_folder_contents(source_folder, destination_folder): + # 检查源文件夹是否存在 + if not os.path.exists(source_folder): + print(f"源文件夹 '{source_folder}' 不存在") + return + + # 创建目标文件夹（如果不存在） + if not os.path.exists(destination_folder): + os.makedirs(destination_folder) + + # 获取源文件夹中的所有文件和文件夹 + items = os.listdir(source_folder) + + # 遍历源文件夹中的每个项目 + for item in items: + # 构建源路径和目标路径 + source_path = os.path.join(source_folder, item) + destination_path = os.path.join(destination_folder, item) + + # 如果是文件，直接复制 + if os.path.isfile(source_path): + shutil.copy2(source_path, destination_path) + # 如果是文件夹，递归地复制它的内容 + elif os.path.isdir(source_path): + copy_folder_contents(source_path, destination_path) + +def copy_makefile(make_file, dest_file): + need_copy = False + # 打开原始文件和目标文件 + with open(make_file, 'r', encoding='utf-8') as f_input, open(dest_file, 'w', encoding='utf-8') as f_output: + # 读取原始文件内容 + file_contents = f_input.read() + if '../common/inc' in file_contents or '../common/*.c' in file_contents: + need_copy = True + # 替换字符串并写入目标文件 + replaced_contents = file_contents.replace('../common', './common') + f_output.write(replaced_contents) + + return need_copy + def main(): template_path = sdkpath + "/tools/export_ide/templates/template_proj" example_path = os.path.relpath(currentPath, sdkpath + "/example") @@ -82,16 +123,23 @@ def main(): # 需要更名的文件路径 make_file = os.path.join(source_dir, 'makefile') config_file = os.path.join(source_dir, 'configs') - + # 如果makefile中引用了上层的common，则需要拷贝 + need_copy = copy_makefile(make_file, os.path.join(proj_path, '.mkfile')) + if need_copy: + copy_folder_contents(source_dir + "../common", proj_path + "/common") # 如果只想拷贝文件，而不是整个文件夹，可以使用 shutil.copy() 方法 # 注意：这种方法不能拷贝文件夹结构 for root, dirs, files in os.walk(source_dir): + if root in ["./build"]: + continue for file in files: if file in [".project", ".cproject", "language.settings.xml"]: continue + src_file = os.path.join(root, file) if os.path.normcase(make_file) == os.path.normcase(src_file): - dst_file = os.path.join(proj_path, '.mkfile') + # dst_file = os.path.join(proj_path, '.mkfile') + continue #elif os.path.normcase(config_file) == os.path.normcase(root): # dst_file = os.path.join(proj_path, os.path.join('.configs', file)) else: