huanghe
3 years ago
committed by
zhugengyu
zhugengyu
210 changed files with 5625 additions and 2446 deletions
@ -0,0 +1,56 @@ |
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mainmenu "Phytium Baremetal Configuration" |
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menu "Project Configuration" |
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config TARGET_NAME |
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string "Build Target Name" |
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default "baremetal" |
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help |
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Build Target name for the demo |
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choice TEST_UART_ID |
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prompt "Select UART driver to be initialized" |
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default TARGET_UART1_ID |
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help |
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Select target to be initialized |
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config TARGET_UART1_ID |
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bool "Uart1 id" |
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config TARGET_UART0_ID |
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bool "Uart0 id" |
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endchoice # BUILD_TARGET_ARCH_TYPE |
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config TEST_UART_BAUDRATE |
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int "Uart baudrate select" |
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default "115200" |
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help |
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Assign uart baudrate in this example |
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config TEST_UART_DATA_BIT_LENGTH |
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int "Number of data bits" |
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default "8" |
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help |
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Target data bits has to be between 8 and 5 |
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choice TEST_UART_PARITY |
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prompt "Select UART parity to be initialized" |
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default TARGET_UART_NO_PARITY |
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help |
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Select target to be initialized |
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config TARGET_UART_NO_PARITY |
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bool "No parity" |
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config TARGET_UART_EVEN_PARITY |
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bool "Even parity" |
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config TARGET_UART_ODD_PARITY |
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bool "Odd parity" |
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endchoice # BUILD_TARGET_ARCH_TYPE |
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config TEST_UART_STOP_BIT_LENGTH |
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int "Number of stop bits" |
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default "1" |
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help |
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Target stop bits has to be between 2 and 1 |
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endmenu |
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source "$(STANDALONE_SDK_ROOT)/Kconfig" |
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@ -0,0 +1,174 @@ |
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<!-- |
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* @Author: your name |
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* @Date: 2021-09-06 08:43:35 |
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* @LastEditTime: 2021-10-27 14:37:32 |
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* @LastEditors: Please set LastEditors |
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* @Description: In User Settings Edit |
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* @FilePath: \phytium-standalone-sdk\baremetal\example\libmetal_test\README.md |
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--> |
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<!-- |
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* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0. |
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* |
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* @Date: 2021-08-27 10:37:27 |
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* @LastEditTime: 2021-09-03 14:19:17 |
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* @Description: This files is for |
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* |
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* @Modify History: |
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* Ver Who Date Changes |
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* ----- ------ -------- -------------------------------------- |
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--> |
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# uart 测试 |
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## 1. 例程介绍 |
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><font size="1">介绍例程的用途，使用场景，相关基本概念，描述用户可以使用例程完成哪些工作</font><br /> |
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1. 基于 串口驱动 |
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2. 基于loopback模式对 串口0 驱动的轮询与中断接收发送模式进行测试 |
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## 2. 如何使用例程 |
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><font size="1">描述开发平台准备，使用例程配置，构建和下载镜像的过程</font><br /> |
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### 2.1 硬件配置方法 |
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><font size="1">哪些硬件平台是支持的，需要哪些外设，例程与开发板哪些IO口相关等（建议附录开发板照片，展示哪些IO口被引出）</font><br /> |
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1. 准备一块ft2000/4 或者d2000 开发板 |
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2. 将串口连接好电脑，波特率设为 115200-8-1-N |
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### 2.2 SDK配置方法 |
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><font size="1">依赖哪些驱动、库和第三方组件，如何完成配置（列出需要使能的关键配置项）</font><br /> |
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- 本例子已经提供好具体的编译指令，以下进行介绍： |
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1. make clean 清理已经编译好的工程 |
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2. make 编译例程代码 |
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3. make boot 将编译好的测试bin和elf 文件，拷贝至$(USR_BOOT_DIR) 变量的路径下 |
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4. make config_d2000_aarch64_default 将预设64bit d2000 下的配置加载至工程例子中 |
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5. make config_d2000_aarch32_default 将预设32bit d2000 下的配置加载至工程例子中 |
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6. make config_ft2004_aarch64_default 将预设64bit ft2004 下的配置加载至工程例子中 |
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7. make config_ft2004_aarch32_default 将预设32bit ft2004 下的配置加载至工程例子中 |
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- 具体使用方法为： |
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- 在baremetal/example/uart_test/ 下 |
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- make + 以上指令 |
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### 2.3 构建和下载 |
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><font size="1">描述构建、烧录下载镜像的过程，列出相关的命令</font><br /> |
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#### 工程下makefile 介绍 |
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``` |
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# 指定工程项目根目录为当前（只能指定一个目录） |
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export PROJECT_DIR ?= . |
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# 用户添加的源文件夹和头文件夹（可以指定多个） |
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export USR_SRC_DIR ?= . |
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export USR_INC_DIR ?= . |
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# 用户定义的编译目标文件上传路径 |
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USR_BOOT_DIR ?= /mnt/d/tftboot/ |
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# 设置启动镜像名 |
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BOOT_IMG_NAME ?= baremetal |
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# 指定编译freertos项目使用的makefile |
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include $(STANDALONE_SDK_ROOT)/make/build_baremetal.mk |
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.PHONY: boot config_d2000_aarch64_default config_d2000_aarch32_default config_ft2004_aarch32_default config_ft2004_aarch64_default |
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load_d2000_aarch64_default: |
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@cp $(PROJECT_DIR)/default_config/d2000_aarch64_sdkconfig \ |
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./$(KCONFIG_CONFIG) -f |
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load_d2000_aarch32_default: |
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@cp $(PROJECT_DIR)/default_config/d2000_aarch32_sdkconfig \ |
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./$(KCONFIG_CONFIG) -f |
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load_ft2004_aarch64_default: |
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@cp $(PROJECT_DIR)/default_config/ft2004_aarch64_sdkconfig \ |
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./$(KCONFIG_CONFIG) -f |
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load_ft2004_aarch32_default: |
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@cp $(PROJECT_DIR)/default_config/ft2004_aarch32_sdkconfig \ |
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./$(KCONFIG_CONFIG) -f |
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# 完成编译 |
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boot: |
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make -j |
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@cp ./$(CONFIG_TARGET_NAME).elf $(USR_BOOT_DIR)/$(BOOT_IMG_NAME).elf |
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@cp ./$(CONFIG_TARGET_NAME).bin $(USR_BOOT_DIR)/$(BOOT_IMG_NAME).bin |
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config_d2000_aarch64_default: load_d2000_aarch64_default genconfig clean |
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config_d2000_aarch32_default: load_d2000_aarch32_default genconfig clean |
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config_ft2004_aarch64_default: load_ft2004_aarch64_default genconfig clean |
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config_ft2004_aarch32_default: load_ft2004_aarch32_default genconfig clean |
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``` |
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其中 USR_BOOT_DIR 变量，用户可以自定义结果文件输出的位置 |
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其中 BOOT_IMG_NAME 变量，用户可以自定义结果文件自己的命名 |
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#### 工程自定义配置 |
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### 2.4 输出与实验现象 |
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><font size="1">描述输入输出情况，列出存在哪些输入，对应的输出是什么（建议附录相关现象图片）</font><br /> |
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#### 编译操作步骤 |
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1. 在开发环境下搭建好tftp 环境 |
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2. 切换至工程所在目录 |
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3. 根据需求，使用 'make config_xxxx_aarchxx_default' 切换至目标芯片与工作模式 |
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4. 使用make clean 命令清空当前工程 |
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5. 执行make boot 对所有工程进行编译，并且输出目标文件 |
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#### 开发板载入步骤 |
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``` |
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setenv ipaddr 192.168.4.20 /* 设置开发板上ip */ |
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setenv serverip 192.168.4.50 /* 设置目标tftp服务器ip */ |
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setenv gatewayip 192.168.4.1 /* 设置网关ip */ |
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tftpboot f0000000 baremetal.elf /* 通过tftp通信,将例程中 elf 拷贝至内存中 */ |
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bootelf -p f0000000 /* 加载代码 */ |
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``` |
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- 运行结果如下： |
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 |
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- Select UART driver to be initialized 可以选择那个串口驱动进行实例，并且用它进行实验 |
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- Uart baudrate select 填入串口驱动的目标波特率 |
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- Number of data bits 位域长度 |
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- Select UART parity to be initialized 校验方式选择 |
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- Number of stop bits 停止域的位数 |
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## 3. 如何解决问题 (Q&A) |
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><font size="1">主要记录使用例程中可能会遇到的问题，给出相应的解决方案</font><br /> |
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## 4. api 指南 |
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[pl011](../../../doc/reference/driver/fpl011.md) |
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## 5. 修改历史记录 |
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><font size="1">记录例程的重大修改记录，标明修改发生的版本号 </font><br /> |
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- 2021-10-16 : v0.1.1 增加中断与轮询两种实现 |
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@ -0,0 +1,121 @@ |
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# |
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# Project Configuration |
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# |
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CONFIG_TARGET_NAME="d2000_baremetal_a32" |
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# CONFIG_TARGET_UART1_ID is not set |
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CONFIG_TARGET_UART0_ID=y |
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CONFIG_TEST_UART_BAUDRATE=115200 |
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CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
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CONFIG_TARGET_UART_NO_PARITY=y |
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# CONFIG_TARGET_UART_EVEN_PARITY is not set |
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# CONFIG_TARGET_UART_ODD_PARITY is not set |
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CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
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# end of Project Configuration |
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# |
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# Platform Setting |
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# |
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# |
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# Arch Configuration |
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# |
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CONFIG_TARGET_ARMV8_AARCH32=y |
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# CONFIG_TARGET_ARMV8_AARCH64 is not set |
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# CONFIG_TARGET_ARMV7 is not set |
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CONFIG_USE_CACHE=y |
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# CONFIG_USE_L3CACHE is not set |
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CONFIG_USE_MMU=y |
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# CONFIG_USE_SYS_TICK is not set |
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CONFIG_USE_AARCH64_L1_TO_AARCH32=y |
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# end of Arch Configuration |
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# |
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# Board Configuration |
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# |
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# CONFIG_TARGET_F2000_4 is not set |
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# CONFIG_TARGET_E2000 is not set |
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CONFIG_TARGET_D2000=y |
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# end of Board Configuration |
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# |
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# Components Configuration |
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# |
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# CONFIG_USE_SPI is not set |
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# CONFIG_USE_QSPI is not set |
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CONFIG_USE_GIC=y |
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CONFIG_EBABLE_GICV3=y |
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CONFIG_USE_SERIAL=y |
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# |
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# Usart Configuration |
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# |
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CONFIG_ENABLE_Pl011_UART=y |
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# end of Usart Configuration |
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# CONFIG_USE_GPIO is not set |
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# CONFIG_USE_IOMUX is not set |
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# CONFIG_USE_ETH is not set |
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# CONFIG_USE_CAN is not set |
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# CONFIG_USE_I2C is not set |
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# CONFIG_USE_TIMER is not set |
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# CONFIG_USE_SDMMC is not set |
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# CONFIG_USE_PCIE is not set |
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# CONFIG_USE_WDT is not set |
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# CONFIG_USE_DMA is not set |
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# CONFIG_USE_NAND is not set |
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# end of Components Configuration |
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# end of Platform Setting |
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# |
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# Building Option |
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# |
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# |
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# Cross-Compiler Setting |
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# |
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CONFIG_COMPILER_NO_STD_STARUP=y |
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# CONFIG_USE_EXT_COMPILER is not set |
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# end of Cross-Compiler Setting |
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CONFIG_LOG_VERBOS=y |
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# CONFIG_LOG_DEBUG is not set |
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# CONFIG_LOG_INFO is not set |
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# CONFIG_LOG_WARN is not set |
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# CONFIG_LOG_ERROR is not set |
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# CONFIG_LOG_NONE is not set |
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# |
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# Linker Options |
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# |
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CONFIG_AARCH32_RAM_LD=y |
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# CONFIG_AARCH64_RAM_LD is not set |
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# CONFIG_QEMU_AARCH32_RAM_LD is not set |
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# CONFIG_USER_DEFINED_LD is not set |
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CONFIG_LINK_SCRIPT_ROM=y |
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CONFIG_ROM_START_UP_ADDR=0x80100000 |
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CONFIG_ROM_SIZE_MB=1 |
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CONFIG_LINK_SCRIPT_RAM=y |
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CONFIG_RAM_START_UP_ADDR=0x81000000 |
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CONFIG_RAM_SIZE_MB=64 |
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CONFIG_HEAP_SIZE=0x04000 |
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CONFIG_STACK_SIZE=0x1000 |
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# end of Linker Options |
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# end of Building Option |
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# |
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# Library Configuration |
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# |
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# CONFIG_USE_G_LIBC is not set |
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CONFIG_USE_NEW_LIBC=y |
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# end of Library Configuration |
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# |
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# Third-Party Configuration |
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# |
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# CONFIG_USE_LWIP is not set |
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# CONFIG_USE_LETTER_SHELL is not set |
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# CONFIG_USE_AMP is not set |
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# CONFIG_USE_YAFFS2 is not set |
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# CONFIG_USE_SDMMC_CMD is not set |
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# end of Third-Party Configuration |
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@ -0,0 +1,120 @@ |
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# |
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# Project Configuration |
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# |
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CONFIG_TARGET_NAME="d2000_baremetal_a64" |
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# CONFIG_TARGET_UART1_ID is not set |
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CONFIG_TARGET_UART0_ID=y |
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CONFIG_TEST_UART_BAUDRATE=115200 |
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CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
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CONFIG_TARGET_UART_NO_PARITY=y |
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# CONFIG_TARGET_UART_EVEN_PARITY is not set |
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# CONFIG_TARGET_UART_ODD_PARITY is not set |
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CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
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# end of Project Configuration |
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# |
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# Platform Setting |
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# |
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# |
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# Arch Configuration |
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# |
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# CONFIG_TARGET_ARMV8_AARCH32 is not set |
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CONFIG_TARGET_ARMV8_AARCH64=y |
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# CONFIG_TARGET_ARMV7 is not set |
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CONFIG_USE_CACHE=y |
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# CONFIG_USE_L3CACHE is not set |
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CONFIG_USE_MMU=y |
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# CONFIG_USE_SYS_TICK is not set |
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# end of Arch Configuration |
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# |
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# Board Configuration |
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# |
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# CONFIG_TARGET_F2000_4 is not set |
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# CONFIG_TARGET_E2000 is not set |
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CONFIG_TARGET_D2000=y |
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# end of Board Configuration |
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# |
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# Components Configuration |
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# |
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# CONFIG_USE_SPI is not set |
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# CONFIG_USE_QSPI is not set |
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CONFIG_USE_GIC=y |
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CONFIG_EBABLE_GICV3=y |
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CONFIG_USE_SERIAL=y |
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# |
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# Usart Configuration |
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# |
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CONFIG_ENABLE_Pl011_UART=y |
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# end of Usart Configuration |
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# CONFIG_USE_GPIO is not set |
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# CONFIG_USE_IOMUX is not set |
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# CONFIG_USE_ETH is not set |
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# CONFIG_USE_CAN is not set |
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# CONFIG_USE_I2C is not set |
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# CONFIG_USE_TIMER is not set |
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# CONFIG_USE_SDMMC is not set |
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# CONFIG_USE_PCIE is not set |
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# CONFIG_USE_WDT is not set |
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# CONFIG_USE_DMA is not set |
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# CONFIG_USE_NAND is not set |
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# end of Components Configuration |
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# end of Platform Setting |
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# |
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# Building Option |
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# |
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|
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# |
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# Cross-Compiler Setting |
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# |
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|
CONFIG_COMPILER_NO_STD_STARUP=y |
||||
|
# CONFIG_USE_EXT_COMPILER is not set |
||||
|
# end of Cross-Compiler Setting |
||||
|
|
||||
|
CONFIG_LOG_VERBOS=y |
||||
|
# CONFIG_LOG_DEBUG is not set |
||||
|
# CONFIG_LOG_INFO is not set |
||||
|
# CONFIG_LOG_WARN is not set |
||||
|
# CONFIG_LOG_ERROR is not set |
||||
|
# CONFIG_LOG_NONE is not set |
||||
|
|
||||
|
# |
||||
|
# Linker Options |
||||
|
# |
||||
|
# CONFIG_AARCH32_RAM_LD is not set |
||||
|
CONFIG_AARCH64_RAM_LD=y |
||||
|
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
||||
|
# CONFIG_USER_DEFINED_LD is not set |
||||
|
CONFIG_LINK_SCRIPT_ROM=y |
||||
|
CONFIG_ROM_START_UP_ADDR=0x80100000 |
||||
|
CONFIG_ROM_SIZE_MB=1 |
||||
|
CONFIG_LINK_SCRIPT_RAM=y |
||||
|
CONFIG_RAM_START_UP_ADDR=0x81000000 |
||||
|
CONFIG_RAM_SIZE_MB=64 |
||||
|
CONFIG_HEAP_SIZE=0x04000 |
||||
|
CONFIG_STACK_TOP_ADDR=0x82000000 |
||||
|
# end of Linker Options |
||||
|
# end of Building Option |
||||
|
|
||||
|
# |
||||
|
# Library Configuration |
||||
|
# |
||||
|
# CONFIG_USE_G_LIBC is not set |
||||
|
CONFIG_USE_NEW_LIBC=y |
||||
|
# end of Library Configuration |
||||
|
|
||||
|
# |
||||
|
# Third-Party Configuration |
||||
|
# |
||||
|
# CONFIG_USE_LWIP is not set |
||||
|
# CONFIG_USE_LETTER_SHELL is not set |
||||
|
# CONFIG_USE_AMP is not set |
||||
|
# CONFIG_USE_YAFFS2 is not set |
||||
|
# CONFIG_USE_SDMMC_CMD is not set |
||||
|
# end of Third-Party Configuration |
||||
@ -0,0 +1,121 @@ |
|||||
|
|
||||
|
# |
||||
|
# Project Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_NAME="FT2004_baremetal_a32" |
||||
|
# CONFIG_TARGET_UART1_ID is not set |
||||
|
CONFIG_TARGET_UART0_ID=y |
||||
|
CONFIG_TEST_UART_BAUDRATE=115200 |
||||
|
CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
||||
|
CONFIG_TARGET_UART_NO_PARITY=y |
||||
|
# CONFIG_TARGET_UART_EVEN_PARITY is not set |
||||
|
# CONFIG_TARGET_UART_ODD_PARITY is not set |
||||
|
CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
||||
|
# end of Project Configuration |
||||
|
|
||||
|
# |
||||
|
# Platform Setting |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Arch Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_ARMV8_AARCH32=y |
||||
|
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
||||
|
# CONFIG_TARGET_ARMV7 is not set |
||||
|
CONFIG_USE_CACHE=y |
||||
|
# CONFIG_USE_L3CACHE is not set |
||||
|
CONFIG_USE_MMU=y |
||||
|
# CONFIG_USE_SYS_TICK is not set |
||||
|
CONFIG_USE_AARCH64_L1_TO_AARCH32=y |
||||
|
# end of Arch Configuration |
||||
|
|
||||
|
# |
||||
|
# Board Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_F2000_4=y |
||||
|
# CONFIG_TARGET_E2000 is not set |
||||
|
# CONFIG_TARGET_D2000 |
||||
|
# end of Board Configuration |
||||
|
|
||||
|
# |
||||
|
# Components Configuration |
||||
|
# |
||||
|
# CONFIG_USE_SPI is not set |
||||
|
# CONFIG_USE_QSPI is not set |
||||
|
CONFIG_USE_GIC=y |
||||
|
CONFIG_EBABLE_GICV3=y |
||||
|
CONFIG_USE_SERIAL=y |
||||
|
|
||||
|
# |
||||
|
# Usart Configuration |
||||
|
# |
||||
|
CONFIG_ENABLE_Pl011_UART=y |
||||
|
# end of Usart Configuration |
||||
|
|
||||
|
# CONFIG_USE_GPIO is not set |
||||
|
# CONFIG_USE_IOMUX is not set |
||||
|
# CONFIG_USE_ETH is not set |
||||
|
# CONFIG_USE_CAN is not set |
||||
|
# CONFIG_USE_I2C is not set |
||||
|
# CONFIG_USE_TIMER is not set |
||||
|
# CONFIG_USE_SDMMC is not set |
||||
|
# CONFIG_USE_PCIE is not set |
||||
|
# CONFIG_USE_WDT is not set |
||||
|
# CONFIG_USE_DMA is not set |
||||
|
# CONFIG_USE_NAND is not set |
||||
|
# end of Components Configuration |
||||
|
# end of Platform Setting |
||||
|
|
||||
|
# |
||||
|
# Building Option |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Cross-Compiler Setting |
||||
|
# |
||||
|
CONFIG_COMPILER_NO_STD_STARUP=y |
||||
|
# CONFIG_USE_EXT_COMPILER is not set |
||||
|
# end of Cross-Compiler Setting |
||||
|
|
||||
|
CONFIG_LOG_VERBOS=y |
||||
|
# CONFIG_LOG_DEBUG is not set |
||||
|
# CONFIG_LOG_INFO is not set |
||||
|
# CONFIG_LOG_WARN is not set |
||||
|
# CONFIG_LOG_ERROR is not set |
||||
|
# CONFIG_LOG_NONE is not set |
||||
|
|
||||
|
# |
||||
|
# Linker Options |
||||
|
# |
||||
|
CONFIG_AARCH32_RAM_LD=y |
||||
|
# CONFIG_AARCH64_RAM_LD is not set |
||||
|
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
||||
|
# CONFIG_USER_DEFINED_LD is not set |
||||
|
CONFIG_LINK_SCRIPT_ROM=y |
||||
|
CONFIG_ROM_START_UP_ADDR=0x80100000 |
||||
|
CONFIG_ROM_SIZE_MB=1 |
||||
|
CONFIG_LINK_SCRIPT_RAM=y |
||||
|
CONFIG_RAM_START_UP_ADDR=0x81000000 |
||||
|
CONFIG_RAM_SIZE_MB=64 |
||||
|
CONFIG_HEAP_SIZE=0x04000 |
||||
|
CONFIG_STACK_SIZE=0x1000 |
||||
|
# end of Linker Options |
||||
|
# end of Building Option |
||||
|
|
||||
|
# |
||||
|
# Library Configuration |
||||
|
# |
||||
|
# CONFIG_USE_G_LIBC is not set |
||||
|
CONFIG_USE_NEW_LIBC=y |
||||
|
# end of Library Configuration |
||||
|
|
||||
|
# |
||||
|
# Third-Party Configuration |
||||
|
# |
||||
|
# CONFIG_USE_LWIP is not set |
||||
|
# CONFIG_USE_LETTER_SHELL is not set |
||||
|
# CONFIG_USE_AMP is not set |
||||
|
# CONFIG_USE_YAFFS2 is not set |
||||
|
# CONFIG_USE_SDMMC_CMD is not set |
||||
|
# end of Third-Party Configuration |
||||
@ -0,0 +1,120 @@ |
|||||
|
|
||||
|
# |
||||
|
# Project Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_NAME="FT2004_baremetal_a64" |
||||
|
# CONFIG_TARGET_UART1_ID is not set |
||||
|
CONFIG_TARGET_UART0_ID=y |
||||
|
CONFIG_TEST_UART_BAUDRATE=115200 |
||||
|
CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
||||
|
CONFIG_TARGET_UART_NO_PARITY=y |
||||
|
# CONFIG_TARGET_UART_EVEN_PARITY is not set |
||||
|
# CONFIG_TARGET_UART_ODD_PARITY is not set |
||||
|
CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
||||
|
# end of Project Configuration |
||||
|
|
||||
|
# |
||||
|
# Platform Setting |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Arch Configuration |
||||
|
# |
||||
|
# CONFIG_TARGET_ARMV8_AARCH32 is not set |
||||
|
CONFIG_TARGET_ARMV8_AARCH64=y |
||||
|
# CONFIG_TARGET_ARMV7 is not set |
||||
|
CONFIG_USE_CACHE=y |
||||
|
# CONFIG_USE_L3CACHE is not set |
||||
|
CONFIG_USE_MMU=y |
||||
|
# CONFIG_USE_SYS_TICK is not set |
||||
|
# end of Arch Configuration |
||||
|
|
||||
|
# |
||||
|
# Board Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_F2000_4=y |
||||
|
# CONFIG_TARGET_E2000 is not set |
||||
|
# CONFIG_TARGET_D2000 |
||||
|
# end of Board Configuration |
||||
|
|
||||
|
# |
||||
|
# Components Configuration |
||||
|
# |
||||
|
# CONFIG_USE_SPI is not set |
||||
|
# CONFIG_USE_QSPI is not set |
||||
|
CONFIG_USE_GIC=y |
||||
|
CONFIG_EBABLE_GICV3=y |
||||
|
CONFIG_USE_SERIAL=y |
||||
|
|
||||
|
# |
||||
|
# Usart Configuration |
||||
|
# |
||||
|
CONFIG_ENABLE_Pl011_UART=y |
||||
|
# end of Usart Configuration |
||||
|
|
||||
|
# CONFIG_USE_GPIO is not set |
||||
|
# CONFIG_USE_IOMUX is not set |
||||
|
# CONFIG_USE_ETH is not set |
||||
|
# CONFIG_USE_CAN is not set |
||||
|
# CONFIG_USE_I2C is not set |
||||
|
# CONFIG_USE_TIMER is not set |
||||
|
# CONFIG_USE_SDMMC is not set |
||||
|
# CONFIG_USE_PCIE is not set |
||||
|
# CONFIG_USE_WDT is not set |
||||
|
# CONFIG_USE_DMA is not set |
||||
|
# CONFIG_USE_NAND is not set |
||||
|
# end of Components Configuration |
||||
|
# end of Platform Setting |
||||
|
|
||||
|
# |
||||
|
# Building Option |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Cross-Compiler Setting |
||||
|
# |
||||
|
CONFIG_COMPILER_NO_STD_STARUP=y |
||||
|
# CONFIG_USE_EXT_COMPILER is not set |
||||
|
# end of Cross-Compiler Setting |
||||
|
|
||||
|
CONFIG_LOG_VERBOS=y |
||||
|
# CONFIG_LOG_DEBUG is not set |
||||
|
# CONFIG_LOG_INFO is not set |
||||
|
# CONFIG_LOG_WARN is not set |
||||
|
# CONFIG_LOG_ERROR is not set |
||||
|
# CONFIG_LOG_NONE is not set |
||||
|
|
||||
|
# |
||||
|
# Linker Options |
||||
|
# |
||||
|
# CONFIG_AARCH32_RAM_LD is not set |
||||
|
CONFIG_AARCH64_RAM_LD=y |
||||
|
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
||||
|
# CONFIG_USER_DEFINED_LD is not set |
||||
|
CONFIG_LINK_SCRIPT_ROM=y |
||||
|
CONFIG_ROM_START_UP_ADDR=0x80100000 |
||||
|
CONFIG_ROM_SIZE_MB=1 |
||||
|
CONFIG_LINK_SCRIPT_RAM=y |
||||
|
CONFIG_RAM_START_UP_ADDR=0x81000000 |
||||
|
CONFIG_RAM_SIZE_MB=64 |
||||
|
CONFIG_HEAP_SIZE=0x04000 |
||||
|
CONFIG_STACK_TOP_ADDR=0x82000000 |
||||
|
# end of Linker Options |
||||
|
# end of Building Option |
||||
|
|
||||
|
# |
||||
|
# Library Configuration |
||||
|
# |
||||
|
# CONFIG_USE_G_LIBC is not set |
||||
|
CONFIG_USE_NEW_LIBC=y |
||||
|
# end of Library Configuration |
||||
|
|
||||
|
# |
||||
|
# Third-Party Configuration |
||||
|
# |
||||
|
# CONFIG_USE_LWIP is not set |
||||
|
# CONFIG_USE_LETTER_SHELL is not set |
||||
|
# CONFIG_USE_AMP is not set |
||||
|
# CONFIG_USE_YAFFS2 is not set |
||||
|
# CONFIG_USE_SDMMC_CMD is not set |
||||
|
# end of Third-Party Configuration |
||||
@ -0,0 +1,120 @@ |
|||||
|
|
||||
|
# |
||||
|
# Project Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_NAME="FT2004_baremetal_a64" |
||||
|
# CONFIG_TARGET_UART1_ID is not set |
||||
|
CONFIG_TARGET_UART0_ID=y |
||||
|
CONFIG_TEST_UART_BAUDRATE=115200 |
||||
|
CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
||||
|
CONFIG_TARGET_UART_NO_PARITY=y |
||||
|
# CONFIG_TARGET_UART_EVEN_PARITY is not set |
||||
|
# CONFIG_TARGET_UART_ODD_PARITY is not set |
||||
|
CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
||||
|
# end of Project Configuration |
||||
|
|
||||
|
# |
||||
|
# Platform Setting |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Arch Configuration |
||||
|
# |
||||
|
# CONFIG_TARGET_ARMV8_AARCH32 is not set |
||||
|
CONFIG_TARGET_ARMV8_AARCH64=y |
||||
|
# CONFIG_TARGET_ARMV7 is not set |
||||
|
CONFIG_USE_CACHE=y |
||||
|
# CONFIG_USE_L3CACHE is not set |
||||
|
CONFIG_USE_MMU=y |
||||
|
# CONFIG_USE_SYS_TICK is not set |
||||
|
# end of Arch Configuration |
||||
|
|
||||
|
# |
||||
|
# Board Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_F2000_4=y |
||||
|
# CONFIG_TARGET_E2000 is not set |
||||
|
# CONFIG_TARGET_D2000 is not set |
||||
|
# end of Board Configuration |
||||
|
|
||||
|
# |
||||
|
# Components Configuration |
||||
|
# |
||||
|
# CONFIG_USE_SPI is not set |
||||
|
# CONFIG_USE_QSPI is not set |
||||
|
CONFIG_USE_GIC=y |
||||
|
CONFIG_EBABLE_GICV3=y |
||||
|
CONFIG_USE_SERIAL=y |
||||
|
|
||||
|
# |
||||
|
# Usart Configuration |
||||
|
# |
||||
|
CONFIG_ENABLE_Pl011_UART=y |
||||
|
# end of Usart Configuration |
||||
|
|
||||
|
# CONFIG_USE_GPIO is not set |
||||
|
# CONFIG_USE_IOMUX is not set |
||||
|
# CONFIG_USE_ETH is not set |
||||
|
# CONFIG_USE_CAN is not set |
||||
|
# CONFIG_USE_I2C is not set |
||||
|
# CONFIG_USE_TIMER is not set |
||||
|
# CONFIG_USE_SDMMC is not set |
||||
|
# CONFIG_USE_PCIE is not set |
||||
|
# CONFIG_USE_WDT is not set |
||||
|
# CONFIG_USE_DMA is not set |
||||
|
# CONFIG_USE_NAND is not set |
||||
|
# end of Components Configuration |
||||
|
# end of Platform Setting |
||||
|
|
||||
|
# |
||||
|
# Building Option |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Cross-Compiler Setting |
||||
|
# |
||||
|
CONFIG_COMPILER_NO_STD_STARUP=y |
||||
|
# CONFIG_USE_EXT_COMPILER is not set |
||||
|
# end of Cross-Compiler Setting |
||||
|
|
||||
|
CONFIG_LOG_VERBOS=y |
||||
|
# CONFIG_LOG_DEBUG is not set |
||||
|
# CONFIG_LOG_INFO is not set |
||||
|
# CONFIG_LOG_WARN is not set |
||||
|
# CONFIG_LOG_ERROR is not set |
||||
|
# CONFIG_LOG_NONE is not set |
||||
|
|
||||
|
# |
||||
|
# Linker Options |
||||
|
# |
||||
|
# CONFIG_AARCH32_RAM_LD is not set |
||||
|
CONFIG_AARCH64_RAM_LD=y |
||||
|
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
||||
|
# CONFIG_USER_DEFINED_LD is not set |
||||
|
CONFIG_LINK_SCRIPT_ROM=y |
||||
|
CONFIG_ROM_START_UP_ADDR=0x80100000 |
||||
|
CONFIG_ROM_SIZE_MB=1 |
||||
|
CONFIG_LINK_SCRIPT_RAM=y |
||||
|
CONFIG_RAM_START_UP_ADDR=0x81000000 |
||||
|
CONFIG_RAM_SIZE_MB=64 |
||||
|
CONFIG_HEAP_SIZE=0x04000 |
||||
|
CONFIG_STACK_TOP_ADDR=0x82000000 |
||||
|
# end of Linker Options |
||||
|
# end of Building Option |
||||
|
|
||||
|
# |
||||
|
# Library Configuration |
||||
|
# |
||||
|
# CONFIG_USE_G_LIBC is not set |
||||
|
CONFIG_USE_NEW_LIBC=y |
||||
|
# end of Library Configuration |
||||
|
|
||||
|
# |
||||
|
# Third-Party Configuration |
||||
|
# |
||||
|
# CONFIG_USE_LWIP is not set |
||||
|
# CONFIG_USE_LETTER_SHELL is not set |
||||
|
# CONFIG_USE_AMP is not set |
||||
|
# CONFIG_USE_YAFFS2 is not set |
||||
|
# CONFIG_USE_SDMMC_CMD is not set |
||||
|
# end of Third-Party Configuration |
||||
|
After Width: | Height: | Size: 22 KiB |
|
After Width: | Height: | Size: 32 KiB |
@ -0,0 +1,55 @@ |
|||||
|
/*
|
||||
|
* Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-07-09 08:08:39 |
||||
|
* @LastEditTime: 2021-10-26 15:43:57 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#include <stdio.h> |
||||
|
#include "uart_test.h" |
||||
|
#include "ft_error_code.h" |
||||
|
#include "ft_debug.h" |
||||
|
#define UART_TEST_TEST_DEBUG_TAG "UART_TEST_TEST" |
||||
|
|
||||
|
#define UART_TEST_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(UART_TEST_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define UART_TEST_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(UART_TEST_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define UART_TEST_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(UART_TEST_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
|
||||
|
|
||||
|
|
||||
|
int main() |
||||
|
{ |
||||
|
FError ret; |
||||
|
ret = TestUartInit(); |
||||
|
|
||||
|
if(ret != FT_SUCCESS) |
||||
|
{ |
||||
|
UART_TEST_TEST_DEBUG_E("TestUartInit is error"); |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
UartHelloWorld(&uart_p); |
||||
|
ret = UartPolled(&uart_p); |
||||
|
if(ret != FT_SUCCESS) |
||||
|
{ |
||||
|
UART_TEST_TEST_DEBUG_E("UartPolled is error"); |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
ret = UartIntr(&uart_p); |
||||
|
if(ret != FT_SUCCESS) |
||||
|
{ |
||||
|
UART_TEST_TEST_DEBUG_E("UartIntr is error"); |
||||
|
return 0; |
||||
|
} |
||||
|
|
||||
|
printf("test is finished \r\n"); |
||||
|
return 0; |
||||
|
} |
||||
@ -0,0 +1,120 @@ |
|||||
|
|
||||
|
# |
||||
|
# Project Configuration |
||||
|
# |
||||
|
CONFIG_TARGET_NAME="d2000_baremetal_a64" |
||||
|
# CONFIG_TARGET_UART1_ID is not set |
||||
|
CONFIG_TARGET_UART0_ID=y |
||||
|
CONFIG_TEST_UART_BAUDRATE=115200 |
||||
|
CONFIG_TEST_UART_DATA_BIT_LENGTH=8 |
||||
|
CONFIG_TARGET_UART_NO_PARITY=y |
||||
|
# CONFIG_TARGET_UART_EVEN_PARITY is not set |
||||
|
# CONFIG_TARGET_UART_ODD_PARITY is not set |
||||
|
CONFIG_TEST_UART_STOP_BIT_LENGTH=1 |
||||
|
# end of Project Configuration |
||||
|
|
||||
|
# |
||||
|
# Platform Setting |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Arch Configuration |
||||
|
# |
||||
|
# CONFIG_TARGET_ARMV8_AARCH32 is not set |
||||
|
CONFIG_TARGET_ARMV8_AARCH64=y |
||||
|
# CONFIG_TARGET_ARMV7 is not set |
||||
|
CONFIG_USE_CACHE=y |
||||
|
# CONFIG_USE_L3CACHE is not set |
||||
|
CONFIG_USE_MMU=y |
||||
|
# CONFIG_USE_SYS_TICK is not set |
||||
|
# end of Arch Configuration |
||||
|
|
||||
|
# |
||||
|
# Board Configuration |
||||
|
# |
||||
|
# CONFIG_TARGET_F2000_4 is not set |
||||
|
# CONFIG_TARGET_E2000 is not set |
||||
|
CONFIG_TARGET_D2000=y |
||||
|
# end of Board Configuration |
||||
|
|
||||
|
# |
||||
|
# Components Configuration |
||||
|
# |
||||
|
# CONFIG_USE_SPI is not set |
||||
|
# CONFIG_USE_QSPI is not set |
||||
|
CONFIG_USE_GIC=y |
||||
|
CONFIG_EBABLE_GICV3=y |
||||
|
CONFIG_USE_SERIAL=y |
||||
|
|
||||
|
# |
||||
|
# Usart Configuration |
||||
|
# |
||||
|
CONFIG_ENABLE_Pl011_UART=y |
||||
|
# end of Usart Configuration |
||||
|
|
||||
|
# CONFIG_USE_GPIO is not set |
||||
|
# CONFIG_USE_IOMUX is not set |
||||
|
# CONFIG_USE_ETH is not set |
||||
|
# CONFIG_USE_CAN is not set |
||||
|
# CONFIG_USE_I2C is not set |
||||
|
# CONFIG_USE_TIMER is not set |
||||
|
# CONFIG_USE_SDMMC is not set |
||||
|
# CONFIG_USE_PCIE is not set |
||||
|
# CONFIG_USE_WDT is not set |
||||
|
# CONFIG_USE_DMA is not set |
||||
|
# CONFIG_USE_NAND is not set |
||||
|
# end of Components Configuration |
||||
|
# end of Platform Setting |
||||
|
|
||||
|
# |
||||
|
# Building Option |
||||
|
# |
||||
|
|
||||
|
# |
||||
|
# Cross-Compiler Setting |
||||
|
# |
||||
|
CONFIG_COMPILER_NO_STD_STARUP=y |
||||
|
# CONFIG_USE_EXT_COMPILER is not set |
||||
|
# end of Cross-Compiler Setting |
||||
|
|
||||
|
CONFIG_LOG_VERBOS=y |
||||
|
# CONFIG_LOG_DEBUG is not set |
||||
|
# CONFIG_LOG_INFO is not set |
||||
|
# CONFIG_LOG_WARN is not set |
||||
|
# CONFIG_LOG_ERROR is not set |
||||
|
# CONFIG_LOG_NONE is not set |
||||
|
|
||||
|
# |
||||
|
# Linker Options |
||||
|
# |
||||
|
# CONFIG_AARCH32_RAM_LD is not set |
||||
|
CONFIG_AARCH64_RAM_LD=y |
||||
|
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
||||
|
# CONFIG_USER_DEFINED_LD is not set |
||||
|
CONFIG_LINK_SCRIPT_ROM=y |
||||
|
CONFIG_ROM_START_UP_ADDR=0x80100000 |
||||
|
CONFIG_ROM_SIZE_MB=1 |
||||
|
CONFIG_LINK_SCRIPT_RAM=y |
||||
|
CONFIG_RAM_START_UP_ADDR=0x81000000 |
||||
|
CONFIG_RAM_SIZE_MB=64 |
||||
|
CONFIG_HEAP_SIZE=0x04000 |
||||
|
CONFIG_STACK_TOP_ADDR=0x82000000 |
||||
|
# end of Linker Options |
||||
|
# end of Building Option |
||||
|
|
||||
|
# |
||||
|
# Library Configuration |
||||
|
# |
||||
|
# CONFIG_USE_G_LIBC is not set |
||||
|
CONFIG_USE_NEW_LIBC=y |
||||
|
# end of Library Configuration |
||||
|
|
||||
|
# |
||||
|
# Third-Party Configuration |
||||
|
# |
||||
|
# CONFIG_USE_LWIP is not set |
||||
|
# CONFIG_USE_LETTER_SHELL is not set |
||||
|
# CONFIG_USE_AMP is not set |
||||
|
# CONFIG_USE_YAFFS2 is not set |
||||
|
# CONFIG_USE_SDMMC_CMD is not set |
||||
|
# end of Third-Party Configuration |
||||
@ -0,0 +1,109 @@ |
|||||
|
#ifndef SDK_CONFIG_H__ |
||||
|
#define SDK_CONFIG_H__ |
||||
|
|
||||
|
/* Project Configuration */ |
||||
|
|
||||
|
#define CONFIG_TARGET_NAME "d2000_baremetal_a64" |
||||
|
/* CONFIG_TARGET_UART1_ID is not set */ |
||||
|
#define CONFIG_TARGET_UART0_ID |
||||
|
#define CONFIG_TEST_UART_BAUDRATE 115200 |
||||
|
#define CONFIG_TEST_UART_DATA_BIT_LENGTH 8 |
||||
|
#define CONFIG_TARGET_UART_NO_PARITY |
||||
|
/* CONFIG_TARGET_UART_EVEN_PARITY is not set */ |
||||
|
/* CONFIG_TARGET_UART_ODD_PARITY is not set */ |
||||
|
#define CONFIG_TEST_UART_STOP_BIT_LENGTH 1 |
||||
|
/* end of Project Configuration */ |
||||
|
|
||||
|
/* Platform Setting */ |
||||
|
|
||||
|
/* Arch Configuration */ |
||||
|
|
||||
|
/* CONFIG_TARGET_ARMV8_AARCH32 is not set */ |
||||
|
#define CONFIG_TARGET_ARMV8_AARCH64 |
||||
|
/* CONFIG_TARGET_ARMV7 is not set */ |
||||
|
#define CONFIG_USE_CACHE |
||||
|
/* CONFIG_USE_L3CACHE is not set */ |
||||
|
#define CONFIG_USE_MMU |
||||
|
/* CONFIG_USE_SYS_TICK is not set */ |
||||
|
/* end of Arch Configuration */ |
||||
|
|
||||
|
/* Board Configuration */ |
||||
|
|
||||
|
/* CONFIG_TARGET_F2000_4 is not set */ |
||||
|
/* CONFIG_TARGET_E2000 is not set */ |
||||
|
#define CONFIG_TARGET_D2000 |
||||
|
/* end of Board Configuration */ |
||||
|
|
||||
|
/* Components Configuration */ |
||||
|
|
||||
|
/* CONFIG_USE_SPI is not set */ |
||||
|
/* CONFIG_USE_QSPI is not set */ |
||||
|
#define CONFIG_USE_GIC |
||||
|
#define CONFIG_EBABLE_GICV3 |
||||
|
#define CONFIG_USE_SERIAL |
||||
|
|
||||
|
/* Usart Configuration */ |
||||
|
|
||||
|
#define CONFIG_ENABLE_Pl011_UART |
||||
|
/* end of Usart Configuration */ |
||||
|
/* CONFIG_USE_GPIO is not set */ |
||||
|
/* CONFIG_USE_IOMUX is not set */ |
||||
|
/* CONFIG_USE_ETH is not set */ |
||||
|
/* CONFIG_USE_CAN is not set */ |
||||
|
/* CONFIG_USE_I2C is not set */ |
||||
|
/* CONFIG_USE_TIMER is not set */ |
||||
|
/* CONFIG_USE_SDMMC is not set */ |
||||
|
/* CONFIG_USE_PCIE is not set */ |
||||
|
/* CONFIG_USE_WDT is not set */ |
||||
|
/* CONFIG_USE_DMA is not set */ |
||||
|
/* CONFIG_USE_NAND is not set */ |
||||
|
/* end of Components Configuration */ |
||||
|
/* end of Platform Setting */ |
||||
|
|
||||
|
/* Building Option */ |
||||
|
|
||||
|
/* Cross-Compiler Setting */ |
||||
|
|
||||
|
#define CONFIG_COMPILER_NO_STD_STARUP |
||||
|
/* CONFIG_USE_EXT_COMPILER is not set */ |
||||
|
/* end of Cross-Compiler Setting */ |
||||
|
#define CONFIG_LOG_VERBOS |
||||
|
/* CONFIG_LOG_DEBUG is not set */ |
||||
|
/* CONFIG_LOG_INFO is not set */ |
||||
|
/* CONFIG_LOG_WARN is not set */ |
||||
|
/* CONFIG_LOG_ERROR is not set */ |
||||
|
/* CONFIG_LOG_NONE is not set */ |
||||
|
|
||||
|
/* Linker Options */ |
||||
|
|
||||
|
/* CONFIG_AARCH32_RAM_LD is not set */ |
||||
|
#define CONFIG_AARCH64_RAM_LD |
||||
|
/* CONFIG_QEMU_AARCH32_RAM_LD is not set */ |
||||
|
/* CONFIG_USER_DEFINED_LD is not set */ |
||||
|
#define CONFIG_LINK_SCRIPT_ROM |
||||
|
#define CONFIG_ROM_START_UP_ADDR 0x80100000 |
||||
|
#define CONFIG_ROM_SIZE_MB 1 |
||||
|
#define CONFIG_LINK_SCRIPT_RAM |
||||
|
#define CONFIG_RAM_START_UP_ADDR 0x81000000 |
||||
|
#define CONFIG_RAM_SIZE_MB 64 |
||||
|
#define CONFIG_HEAP_SIZE 0x04000 |
||||
|
#define CONFIG_STACK_TOP_ADDR 0x82000000 |
||||
|
/* end of Linker Options */ |
||||
|
/* end of Building Option */ |
||||
|
|
||||
|
/* Library Configuration */ |
||||
|
|
||||
|
/* CONFIG_USE_G_LIBC is not set */ |
||||
|
#define CONFIG_USE_NEW_LIBC |
||||
|
/* end of Library Configuration */ |
||||
|
|
||||
|
/* Third-Party Configuration */ |
||||
|
|
||||
|
/* CONFIG_USE_LWIP is not set */ |
||||
|
/* CONFIG_USE_LETTER_SHELL is not set */ |
||||
|
/* CONFIG_USE_AMP is not set */ |
||||
|
/* CONFIG_USE_YAFFS2 is not set */ |
||||
|
/* CONFIG_USE_SDMMC_CMD is not set */ |
||||
|
/* end of Third-Party Configuration */ |
||||
|
|
||||
|
#endif |
||||
@ -0,0 +1,42 @@ |
|||||
|
/*
|
||||
|
* Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-08-27 10:49:10 |
||||
|
* @LastEditTime: 2021-10-26 09:15:21 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#include "ft_types.h" |
||||
|
#include "fpl011.h" |
||||
|
#include "stdio.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include <string.h> |
||||
|
|
||||
|
#define HELLO_TEST_DEBUG_TAG "HELLO_TEST" |
||||
|
|
||||
|
#define HELLO_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(HELLO_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define HELLO_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(HELLO_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define HELLO_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(HELLO_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
|
||||
|
|
||||
|
|
||||
|
|
||||
|
void UartHelloWorld(FPl011 *uart_p) |
||||
|
{ |
||||
|
u8 HelloWorld[] = "Hello World"; |
||||
|
u32 i = 0; |
||||
|
|
||||
|
while (i < (sizeof(HelloWorld) - 1)) { |
||||
|
/* Transmit the data */ |
||||
|
i += FPl011Send(uart_p, |
||||
|
&HelloWorld[i], 1); |
||||
|
} |
||||
|
|
||||
|
HELLO_TEST_DEBUG_I("uart_hello_world is passed "); |
||||
|
} |
||||
@ -0,0 +1,115 @@ |
|||||
|
/*
|
||||
|
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-10-18 19:32:46 |
||||
|
* @LastEditTime: 2021-10-26 09:16:12 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#include "fpl011.h" |
||||
|
#include "ft_error_code.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include "parameters.h" |
||||
|
#include <string.h> |
||||
|
|
||||
|
#define UART_INIT_TEST_DEBUG_TAG "UART_INIT_TEST" |
||||
|
|
||||
|
#define UART_INIT_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(UART_INIT_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define UART_INIT_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(UART_INIT_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define UART_INIT_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(UART_INIT_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
|
||||
|
#ifdef CONFIG_TARGET_UART1_ID |
||||
|
#define UART_SELECT_TARGET FUART1_ID |
||||
|
#endif |
||||
|
|
||||
|
#ifdef CONFIG_TARGET_UART0_ID |
||||
|
#define UART_SELECT_TARGET FUART0_ID |
||||
|
#endif |
||||
|
|
||||
|
FPl011 uart_p; |
||||
|
FPl011Format format; |
||||
|
|
||||
|
FError TestUartInit(void) |
||||
|
{ |
||||
|
FPl011Config config_value; |
||||
|
const FPl011Config *config_p; |
||||
|
FError ret; |
||||
|
config_p = FPl011LookupConfig(UART_SELECT_TARGET); |
||||
|
if (NULL == config_p) |
||||
|
{ |
||||
|
UART_INIT_TEST_DEBUG_E("Lookup ID is error "); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
memcpy(&config_value,config_p,sizeof(FPl011Config)) ; |
||||
|
|
||||
|
ret = FPl011CfgInitialize(&uart_p,&config_value); |
||||
|
if(ret != FT_SUCCESS) |
||||
|
{ |
||||
|
UART_INIT_TEST_DEBUG_E("Uart initialize is error "); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
|
||||
|
format.baudrate = CONFIG_TEST_UART_BAUDRATE; /* In bps, ie 1200 */ |
||||
|
|
||||
|
switch(CONFIG_TEST_UART_DATA_BIT_LENGTH) |
||||
|
{ |
||||
|
case 8: |
||||
|
format.data_bits = FPL011_FORMAT_WORDLENGTH_8BIT; |
||||
|
break; |
||||
|
case 7: |
||||
|
format.data_bits = FPL011_FORMAT_WORDLENGTH_7BIT; |
||||
|
break; |
||||
|
case 6: |
||||
|
format.data_bits = FPL011_FORMAT_WORDLENGTH_6BIT; |
||||
|
break; |
||||
|
case 5: |
||||
|
format.data_bits = FPL011_FORMAT_WORDLENGTH_5BIT; |
||||
|
break; |
||||
|
default: |
||||
|
format.data_bits = FPL011_FORMAT_WORDLENGTH_8BIT; |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
#if defined(CONFIG_TARGET_UART_NO_PARITY) |
||||
|
format.parity = FPL011_FORMAT_NO_PARITY; |
||||
|
#elif defined(CONFIG_TARGET_UART_EVEN_PARITY) |
||||
|
format.parity = (FPL011_FORMAT_EN_PARITY | FPL011_FORMAT_EVEN_PARITY); |
||||
|
#elif defined(CONFIG_TARGET_UART_ODD_PARITY) |
||||
|
format.parity = (FPL011_FORMAT_EN_PARITY | FPL011_FORMAT_ODD_PARITY); |
||||
|
#else |
||||
|
format.parity = FPL011_FORMAT_NO_PARITY; |
||||
|
#endif |
||||
|
|
||||
|
switch(CONFIG_TEST_UART_STOP_BIT_LENGTH) |
||||
|
{ |
||||
|
case 1: |
||||
|
format.stopbits = FPL011_FORMAT_1_STOP_BIT; |
||||
|
break; |
||||
|
case 2: |
||||
|
format.stopbits = FPL011_FORMAT_2_STOP_BIT; |
||||
|
break; |
||||
|
default: |
||||
|
format.stopbits = FPL011_FORMAT_1_STOP_BIT; |
||||
|
break; |
||||
|
|
||||
|
} |
||||
|
|
||||
|
ret = FPl011SetDataFormat(&uart_p,&format); |
||||
|
if(ret != FT_SUCCESS) |
||||
|
{ |
||||
|
UART_INIT_TEST_DEBUG_E("Pl011SetDataFormat is error "); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
|
||||
|
/* Start Uart */ |
||||
|
FPl011SetOptions(&uart_p,FPL011_OPTION_UARTEN|FPL011_OPTION_RXEN|FPL011_OPTION_TXEN|FPL011_OPTION_DTR|FPL011_OPTION_RTS); |
||||
|
|
||||
|
UART_INIT_TEST_DEBUG_I("TestUartInit is ok"); |
||||
|
return FT_SUCCESS; |
||||
|
} |
||||
@ -0,0 +1,155 @@ |
|||||
|
/*
|
||||
|
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-10-20 16:33:37 |
||||
|
* @LastEditTime: 2021-10-26 11:31:46 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#include "Fpl011.h" |
||||
|
#include "Fpl011_hw.h" |
||||
|
#include "interrupt.h" |
||||
|
#include "ft_error_code.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include "fsleep.h" |
||||
|
#include "parameters.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include <string.h> |
||||
|
|
||||
|
#define INTR_TEST_DEBUG_TAG "INTR_TEST" |
||||
|
|
||||
|
#define INTR_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(INTR_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define INTR_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(INTR_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define INTR_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(INTR_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
|
||||
|
/*
|
||||
|
* The following constant controls the length of the buffers to be sent |
||||
|
* and received with the UART, |
||||
|
*/ |
||||
|
#define TEST_BUFFER_SIZE 60 |
||||
|
|
||||
|
/*
|
||||
|
* The following buffers are used in this example to send and receive data |
||||
|
* with the UART. |
||||
|
*/ |
||||
|
static u8 send_buffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ |
||||
|
static u8 recv_buffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ |
||||
|
|
||||
|
/*
|
||||
|
* The following counters are used to determine when the entire buffer has |
||||
|
* been sent and received. |
||||
|
*/ |
||||
|
volatile int total_received_count; |
||||
|
volatile int total_sent_count; |
||||
|
int total_error_count; |
||||
|
|
||||
|
static void IntrTestHandler(void *args, u32 event, u32 event_data) |
||||
|
{ |
||||
|
/* All of the data has been sent */ |
||||
|
if (event == FPL011_EVENT_SENT_DATA) { |
||||
|
total_sent_count = event_data; |
||||
|
} |
||||
|
|
||||
|
/* All of the data has been received */ |
||||
|
if (event == FPL011_EVENT_RECV_DATA) { |
||||
|
total_received_count = event_data; |
||||
|
} |
||||
|
/*
|
||||
|
* Data was received, but not the expected number of bytes, a |
||||
|
* timeout just indicates the data stopped for 8 character times |
||||
|
*/ |
||||
|
if (event == FPL011_EVENT_RECV_TOUT) { |
||||
|
total_received_count = event_data; |
||||
|
} |
||||
|
|
||||
|
/*
|
||||
|
* Data was received with an error, keep the data but determine |
||||
|
* what kind of errors occurred |
||||
|
*/ |
||||
|
if (event == FPL011_EVENT_RECV_ERROR) { |
||||
|
total_received_count = event_data; |
||||
|
total_error_count++; |
||||
|
} |
||||
|
|
||||
|
/*
|
||||
|
* Data was received with an parity or frame or break error, keep the data |
||||
|
* but determine what kind of errors occurred. Specific to Zynq Ultrascale+ |
||||
|
* MP. |
||||
|
*/ |
||||
|
if (event == FPL011_EVENT_PARE_FRAME_BRKE) { |
||||
|
total_received_count = event_data; |
||||
|
total_error_count++; |
||||
|
} |
||||
|
|
||||
|
/*
|
||||
|
* Data was received with an overrun error, keep the data but determine |
||||
|
* what kind of errors occurred. Specific to Zynq Ultrascale+ MP. |
||||
|
*/ |
||||
|
if (event == FPL011_EVENT_RECV_ERROR) { |
||||
|
total_received_count = event_data; |
||||
|
total_error_count++; |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
|
||||
|
|
||||
|
FError UartIntr(FPl011 *uart_p) |
||||
|
{ |
||||
|
u32 intr_mask; |
||||
|
int i; |
||||
|
int bad_byte_count = 0; |
||||
|
InterruptInstall(uart_p->config.irq_num, (IrqHandler)FPl011InterruptHandler, uart_p, "uart"); |
||||
|
InterruptUmask(uart_p->config.irq_num); |
||||
|
FPl011SetHandler(uart_p, IntrTestHandler, NULL); |
||||
|
FPl011SetRxFifoThreadhold(uart_p,FPL011IFLS_RXIFLSEL_1_4); |
||||
|
FPl011SetTxFifoThreadHold(uart_p,FPL011IFLS_TXIFLSEL_1_2); |
||||
|
|
||||
|
intr_mask = (FPL011IMSC_RXIM | |
||||
|
FPL011IMSC_TXIM | |
||||
|
FPL011IMSC_RTIM | |
||||
|
FPL011IMSC_FEIM | |
||||
|
FPL011IMSC_PEIM | |
||||
|
FPL011IMSC_BEIM | |
||||
|
FPL011IMSC_OEIM); |
||||
|
|
||||
|
FPl011SetInterruptMask(uart_p,intr_mask); |
||||
|
|
||||
|
/* Use local loopback mode. */ |
||||
|
FPl011SetOperMode(uart_p, FPL011_OPER_MODE_LOCAL_LOOP); |
||||
|
|
||||
|
for (i = 0; i < TEST_BUFFER_SIZE; i++) { |
||||
|
send_buffer[i] = (i % 26) + 'A'; |
||||
|
recv_buffer[i] = 0; |
||||
|
} |
||||
|
|
||||
|
FPl011Receive(uart_p,recv_buffer,TEST_BUFFER_SIZE); |
||||
|
FPl011Send(uart_p, send_buffer, TEST_BUFFER_SIZE); |
||||
|
|
||||
|
while ((total_error_count == 0) && ((total_sent_count != TEST_BUFFER_SIZE)|| (total_received_count != TEST_BUFFER_SIZE))) |
||||
|
; |
||||
|
|
||||
|
for (i = 0; i < TEST_BUFFER_SIZE; i++) |
||||
|
{ |
||||
|
if (recv_buffer[i] != send_buffer[i]) { |
||||
|
bad_byte_count++; |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
FPl011SetOperMode(uart_p, FPL011_OPER_MODE_NORMAL); |
||||
|
FPl011SetInterruptMask(uart_p,~intr_mask); |
||||
|
|
||||
|
if (bad_byte_count != 0) { |
||||
|
INTR_TEST_DEBUG_E("uart_intr is error %d \r\n",bad_byte_count); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
|
||||
|
INTR_TEST_DEBUG_I("uart_intr is ok"); |
||||
|
|
||||
|
return FT_SUCCESS; |
||||
|
} |
||||
@ -0,0 +1,85 @@ |
|||||
|
/*
|
||||
|
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-10-19 13:42:58 |
||||
|
* @LastEditTime: 2021-10-26 15:47:11 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#include "fpl011.h" |
||||
|
#include "fpl011_hw.h" |
||||
|
#include "ft_error_code.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include "parameters.h" |
||||
|
#include "ft_debug.h" |
||||
|
#include <string.h> |
||||
|
|
||||
|
#define POLLED_TEST_DEBUG_TAG "POLLED_TEST" |
||||
|
|
||||
|
#define POLLED_TEST_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(POLLED_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define POLLED_TEST_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(POLLED_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
#define POLLED_TEST_DEBUG_E(format, ...) FT_DEBUG_PRINT_E(POLLED_TEST_DEBUG_TAG, format, ##__VA_ARGS__) |
||||
|
|
||||
|
|
||||
|
#define TEST_BUFFER_SIZE 10 |
||||
|
/*
|
||||
|
* The following buffers are used in this example to send and receive data |
||||
|
* with the UART. |
||||
|
*/ |
||||
|
static u8 send_buffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ |
||||
|
static u8 recv_buffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ |
||||
|
|
||||
|
|
||||
|
FError UartPolled(FPl011 *uart_p) |
||||
|
{ |
||||
|
int i = 0; |
||||
|
u32 total_send_count ,recv_count,bad_byte_count = 0; |
||||
|
/* Use local loopback mode. */ |
||||
|
FPl011SetOperMode(uart_p, FPL011_OPER_MODE_LOCAL_LOOP); |
||||
|
for (i = 0; i < TEST_BUFFER_SIZE; i++) |
||||
|
{ |
||||
|
send_buffer[i] = (i % 26) + 'A'; |
||||
|
recv_buffer[i] = 0; |
||||
|
} |
||||
|
|
||||
|
total_send_count = FPl011Send(uart_p, send_buffer, TEST_BUFFER_SIZE); |
||||
|
while (FUART_ISTRANSMITBUSY(uart_p->config.base_address)) |
||||
|
; |
||||
|
if(total_send_count != TEST_BUFFER_SIZE) |
||||
|
{ |
||||
|
POLLED_TEST_DEBUG_E("Polled send is error %d",total_send_count); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
|
||||
|
recv_count = 0; |
||||
|
while (recv_count < TEST_BUFFER_SIZE) |
||||
|
{ |
||||
|
recv_count += FPl011Receive(uart_p,&recv_buffer[recv_count],(TEST_BUFFER_SIZE - recv_count)); |
||||
|
} |
||||
|
|
||||
|
/* Verify the entire receive buffer was successfully received */ |
||||
|
for (i = 0; i < TEST_BUFFER_SIZE;i++) |
||||
|
{ |
||||
|
if(recv_buffer[i] != send_buffer[i]) |
||||
|
{ |
||||
|
bad_byte_count++; |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
/* Set the UART in Normal Mode */ |
||||
|
FPl011SetOperMode(uart_p, FPL011_OPER_MODE_NORMAL); |
||||
|
|
||||
|
if(bad_byte_count != 0) |
||||
|
{ |
||||
|
POLLED_TEST_DEBUG_E("uart_polled recv is error "); |
||||
|
return ERR_GENERAL; |
||||
|
} |
||||
|
POLLED_TEST_DEBUG_I("uart_polled is ok "); |
||||
|
return ERR_SUCCESS; |
||||
|
} |
||||
@ -0,0 +1,38 @@ |
|||||
|
/*
|
||||
|
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-10-26 13:45:50 |
||||
|
* @LastEditTime: 2021-10-26 13:49:51 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
|
||||
|
#ifndef BAREMETAL_EXAMPLE_UART_TEST |
||||
|
#define BAREMETAL_EXAMPLE_UART_TEST |
||||
|
|
||||
|
|
||||
|
#ifdef __cplusplus |
||||
|
extern "C" |
||||
|
{ |
||||
|
#endif |
||||
|
|
||||
|
#include "ft_error_code.h" |
||||
|
#include "fpl011.h" |
||||
|
|
||||
|
|
||||
|
extern FPl011 uart_p; |
||||
|
extern FError TestUartInit(void); |
||||
|
extern FError UartIntr(FPl011 *uart_p); |
||||
|
extern FError UartPolled(FPl011 *uart_p); |
||||
|
extern void UartHelloWorld(FPl011 *uart_p); |
||||
|
|
||||
|
#ifdef __cplusplus |
||||
|
} |
||||
|
#endif |
||||
|
|
||||
|
#endif |
||||
@ -1,69 +0,0 @@ |
|||||
/*
|
|
||||
* Copyright (c) 2021 Phytium Information Technology, Inc. |
|
||||
* |
|
||||
* SPDX-License-Identifier: Apache-2.0. |
|
||||
* |
|
||||
* @Date: 2021-08-30 08:25:47 |
|
||||
* @LastEditTime: 2021-09-06 14:55:11 |
|
||||
* @Description: This files is for |
|
||||
* |
|
||||
* @Modify History: |
|
||||
* Ver Who Date Changes |
|
||||
* ----- ------ -------- -------------------------------------- |
|
||||
*/ |
|
||||
#include <stdio.h> |
|
||||
#include "parameters.h" |
|
||||
#include "pl011_uart.h" |
|
||||
// #include "gicv3.h"
|
|
||||
#include "interrupt.h" |
|
||||
|
|
||||
Pl011 pl011_obj; |
|
||||
volatile u32 get_uart_rx_flg = 0; |
|
||||
volatile u8 set_irq_priority = 50; |
|
||||
|
|
||||
static void UartIrqCallback(void *args, u32 event, u32 event_data) |
|
||||
{ |
|
||||
get_uart_rx_flg = 1; |
|
||||
Pl011IrqClearReciveTimeOut(&pl011_obj); |
|
||||
} |
|
||||
|
|
||||
static void UartIrqHandler(s32 vector, void *param) |
|
||||
{ |
|
||||
Pl011InterruptHandler(param); |
|
||||
} |
|
||||
|
|
||||
void UartInit(void) |
|
||||
{ |
|
||||
Pl011Config config = *Pl011LookupConfig(FT_UART1_ID); |
|
||||
Pl011CfgInitialize(&pl011_obj, &config); |
|
||||
Pl011SetHandler(&pl011_obj, UartIrqCallback, NULL); |
|
||||
InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); |
|
||||
InterruptInstall(pl011_obj.config.irq_num, UartIrqHandler, &pl011_obj, "uart1"); |
|
||||
InterruptUmask(pl011_obj.config.irq_num); |
|
||||
Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); |
|
||||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|
||||
} |
|
||||
|
|
||||
void TestUart() |
|
||||
{ |
|
||||
char Byte; |
|
||||
|
|
||||
UartInit(); |
|
||||
while (1) |
|
||||
{ |
|
||||
while (get_uart_rx_flg == 0) |
|
||||
{ |
|
||||
|
|
||||
} |
|
||||
|
|
||||
Byte = Pl011BlockReceive(&pl011_obj); |
|
||||
printf("-->recv %c\r\n", Byte); |
|
||||
Pl011BlockSend(&pl011_obj, &Byte, 1); |
|
||||
InterruptMask(pl011_obj.config.irq_num); |
|
||||
set_irq_priority++; |
|
||||
InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); |
|
||||
InterruptUmask(pl011_obj.config.irq_num); |
|
||||
get_uart_rx_flg = 0; |
|
||||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|
||||
} |
|
||||
} |
|
||||
@ -0,0 +1,398 @@ |
|||||
|
/*
|
||||
|
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
||||
|
* |
||||
|
* SPDX-License-Identifier: Apache-2.0. |
||||
|
* |
||||
|
* @Date: 2021-09-27 13:38:29 |
||||
|
* @LastEditTime: 2021-10-19 19:37:07 |
||||
|
* @Description: This files is for |
||||
|
* |
||||
|
* @Modify History: |
||||
|
* Ver Who Date Changes |
||||
|
* ----- ------ -------- -------------------------------------- |
||||
|
*/ |
||||
|
#include <stdlib.h> |
||||
|
#include <string.h> |
||||
|
#include <stdio.h> |
||||
|
#include "strto.h" |
||||
|
#include "fsleep.h" |
||||
|
#include "sdkconfig.h" |
||||
|
#ifndef SDK_CONFIG_H__ |
||||
|
#warning "Please include sdkconfig.h" |
||||
|
#endif |
||||
|
#include "ft_debug.h" |
||||
|
#include "cache.h" |
||||
|
#include "parameters.h" |
||||
|
#include "../src/shell.h" |
||||
|
#include "../port/shell_port.h" |
||||
|
#include "parameters.h" |
||||
|
#include "f_sdio.h" |
||||
|
#include "f_sdio_hw.h" |
||||
|
|
||||
|
static u32 base_addr = FSDIO_HOST_0_BASE_ADDR; |
||||
|
|
||||
|
#define FSDIO_OUT32(reg_off, reg_val) FtOut32(base_addr + (u32)(reg_off), (u32)(reg_val)) |
||||
|
#define FSDIO_IN32(reg_off) FtIn32(base_addr + (u32)(reg_off)) |
||||
|
|
||||
|
static void SdioSendPrivateCmd(u32 cmd, u32 arg) |
||||
|
{ |
||||
|
FSDIO_OUT32(FSDIO_REG_CMDARG_OFFSET, arg); |
||||
|
|
||||
|
int retries = 0; |
||||
|
do |
||||
|
{ |
||||
|
if ((0 == retries % 100) && (0 != retries)) |
||||
|
printf("card busy\r\n"); |
||||
|
fsleep_microsec(1); |
||||
|
} while ((FSDIO_STATUS_CARD_BUSY & FSDIO_IN32(FSDIO_REG_STATUS_OFFSET)) && |
||||
|
(FSDIO_TIMEOUT > ++retries)); |
||||
|
|
||||
|
if (FSDIO_TIMEOUT <= retries) |
||||
|
{ |
||||
|
printf("wait card busy timeout\r\n"); |
||||
|
} |
||||
|
|
||||
|
FSDIO_OUT32(FSDIO_REG_CMD_OFFSET, cmd | FSDIO_CMD_START); |
||||
|
|
||||
|
retries = 0; |
||||
|
do |
||||
|
{ |
||||
|
if ((0 == retries % 100) && (0 != retries)) |
||||
|
printf("cmd sending\r\n"); |
||||
|
fsleep_microsec(1); |
||||
|
} while ((FSDIO_IN32(FSDIO_CMD_START & FSDIO_REG_CMD_OFFSET)) && |
||||
|
(FSDIO_TIMEOUT > ++retries)); |
||||
|
|
||||
|
if (FSDIO_TIMEOUT <= retries) |
||||
|
{ |
||||
|
printf("wait cmd sending timeout\r\n"); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
static void SdioWaitCmd() |
||||
|
{ |
||||
|
u32 raw_stats, dma_status; |
||||
|
int retries = 0; |
||||
|
|
||||
|
//wait cmd
|
||||
|
while(1) |
||||
|
{ |
||||
|
raw_stats = FSDIO_IN32(FSDIO_REG_RAW_INTS_OFFSET); |
||||
|
//dma_status = FSDIO_IN32(FSDIO_REG_DMAC_STATUS_OFFSET);
|
||||
|
|
||||
|
if (FSDIO_INT_CMD_BIT & raw_stats) |
||||
|
{ |
||||
|
printf("cmd success\r\n"); |
||||
|
break; |
||||
|
} |
||||
|
else if (raw_stats) |
||||
|
{ |
||||
|
printf("cmd exit 0x%x\r\n", raw_stats); |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
FSDIO_OUT32(FSDIO_REG_RAW_INTS_OFFSET, 0xffffffff); |
||||
|
|
||||
|
if (1000 < ++retries) |
||||
|
{ |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
if ((0 == retries % 100) && (0 != retries)) |
||||
|
printf("status: 0x%x \r\n", FSDIO_IN32(FSDIO_REG_STATUS_OFFSET)); |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
static void SdioSendCmd(u32 cmd, u32 arg, u32 opcode, const char *cmd_str) |
||||
|
{ |
||||
|
printf("====cmd %d [%s] start=======\r\n", opcode, cmd_str); |
||||
|
|
||||
|
if (FSDIO_CARD_DETECTED == (FSDIO_CARD_DETECTED & FSDIO_IN32(FSDIO_REG_CARD_DETECT_OFFSET))) |
||||
|
{ |
||||
|
printf("card not exists\r\n"); |
||||
|
return; |
||||
|
} |
||||
|
|
||||
|
SdioSendPrivateCmd(cmd, arg); |
||||
|
SdioWaitCmd(); |
||||
|
printf("====cmd %d done=======\r\n", opcode); |
||||
|
} |
||||
|
|
||||
|
static void SdioWaitDat() |
||||
|
{ |
||||
|
u32 status, raw_ints, dma_status; |
||||
|
int retries = 0; |
||||
|
|
||||
|
printf("====wait data start===\r\n"); |
||||
|
|
||||
|
while (1) |
||||
|
{ |
||||
|
status = FSDIO_IN32(FSDIO_REG_STATUS_OFFSET); |
||||
|
raw_ints = FSDIO_IN32(FSDIO_REG_RAW_INTS_OFFSET); |
||||
|
dma_status = FSDIO_IN32(FSDIO_REG_DMAC_STATUS_OFFSET); |
||||
|
|
||||
|
if (raw_ints & FSDIO_INT_DTO_BIT) |
||||
|
{ |
||||
|
printf("data transfer success 0x%x 0x%x\r\n", raw_ints, dma_status); |
||||
|
if (FSDIO_DMAC_STATUS_TI & dma_status) |
||||
|
{ |
||||
|
printf("send data done \r\n"); |
||||
|
} |
||||
|
|
||||
|
if (FSDIO_DMAC_STATUS_RI & dma_status) |
||||
|
{ |
||||
|
printf("recv data done \r\n"); |
||||
|
} |
||||
|
break; |
||||
|
} |
||||
|
else if (raw_ints) |
||||
|
{ |
||||
|
/*
|
||||
|
0x1114 bit 12, 8, 4, 2 HLE, Response timeout, Transmit FIFO data request, Command done |
||||
|
*/ |
||||
|
printf("data transfer exit with status: 0x%x raw_ints: 0x%x dma_status: 0X%x\r\n", |
||||
|
status, raw_ints, dma_status); |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
FSDIO_OUT32(FSDIO_REG_RAW_INTS_OFFSET, 0xffffffff); |
||||
|
|
||||
|
if (1000 < ++retries) |
||||
|
{ |
||||
|
break; |
||||
|
} |
||||
|
|
||||
|
/*
|
||||
|
WRITE: |
||||
|
status: 0x80001906 bit 31 12 11 8 3 2: DMA ACK, FIFO COUNT, DAT[3] FIFO FULL FIFO EMPTY |
||||
|
raw_ints: 0x114 bit 8 4 2: RESP TIMEOUT, TX FIFO, COMMAND DONE |
||||
|
dma: 0x2000 bit 13: SUSPEND |
||||
|
|
||||
|
READ: |
||||
|
status: 0x1906 bit 12 11 8 3 2 |
||||
|
raw_ints: 0x114 |
||||
|
dma: 0x2000 |
||||
|
*/ |
||||
|
/*
|
||||
|
WRITE |
||||
|
status: 0x8001f906 bit 31 16 15 14 13 12 11 8 3 2: |
||||
|
|
||||
|
ints: 0x1114 bit 12 8 4 2 HLE |
||||
|
dma: 0x2000 |
||||
|
*/ |
||||
|
if ((0 == retries % 100) && (0 != retries)) |
||||
|
printf("status: 0x%x, ints: 0x%x dma: 0x%x\r\n", status, raw_ints, dma_status); |
||||
|
} |
||||
|
|
||||
|
printf("====wait data end===\r\n"); |
||||
|
} |
||||
|
|
||||
|
static int SdioVerifyEntry(int argc, char *argv[]) |
||||
|
{ |
||||
|
int i; |
||||
|
printf("====init=======\r\n"); |
||||
|
|
||||
|
FSDIO_OUT32(FSDIO_REG_FIFOTH_OFFSET, 0x20070008); |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x0); |
||||
|
FSDIO_OUT32((FSDIO_REG_UHS_REG_EXT_OFFSET), 0x0502); |
||||
|
|
||||
|
FSDIO_OUT32((FSDIO_REG_UHS_REG_OFFSET), 0x0); //设置电压为3.3v
|
||||
|
FSDIO_OUT32((FSDIO_REG_PWREN_OFFSET), 0x1); //打开供电开关
|
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x1); |
||||
|
|
||||
|
/* reset dma and fifo */ |
||||
|
FSDIO_OUT32(FSDIO_REG_CNTRL_OFFSET, FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET | FSDIO_CNTRL_CONTROLLER_RESET); |
||||
|
|
||||
|
do |
||||
|
{ |
||||
|
printf("wait fifo and dma reset done\r\n"); |
||||
|
} while ((FSDIO_CNTRL_FIFO_RESET | FSDIO_CNTRL_DMA_RESET | FSDIO_CNTRL_CONTROLLER_RESET) & FSDIO_IN32(FSDIO_REG_CNTRL_OFFSET)); |
||||
|
|
||||
|
FSDIO_OUT32((FSDIO_REG_BUS_MODE_OFFSET), 0x80); //bit[7] 使能idma
|
||||
|
/* this lead to cmd timeout */ |
||||
|
//FSDIO_OUT32((FSDIO_REG_CNTRL_OFFSET), FSDIO_CNTRL_INT_ENABLE | FSDIO_CNTRL_USE_INTERNAL_DMAC);//bit[23,4] card voltage, enable int
|
||||
|
|
||||
|
FSDIO_OUT32((FSDIO_REG_TMOUT_OFFSET), 0xffffffff); //set timeout
|
||||
|
|
||||
|
/* reset card */ |
||||
|
FSDIO_OUT32(FSDIO_REG_CARD_RESET_OFFSET, FSDIO_CARD_RESET_ENABLE); |
||||
|
|
||||
|
/* clr intr */ |
||||
|
FSDIO_OUT32(FSDIO_REG_INT_MASK_OFFSET, 0); |
||||
|
FSDIO_OUT32(FSDIO_REG_RAW_INTS_OFFSET, FSDIO_IN32(FSDIO_REG_RAW_INTS_OFFSET)); |
||||
|
FSDIO_OUT32(FSDIO_REG_DMAC_INT_ENA_OFFSET, 0); |
||||
|
FSDIO_OUT32(FSDIO_REG_DMAC_STATUS_OFFSET, FSDIO_IN32(FSDIO_REG_DMAC_STATUS_OFFSET)); |
||||
|
|
||||
|
/* update clk reg */ |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x0); |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKDIV_OFFSET), 0x7e7dfa); |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x1); |
||||
|
SdioSendPrivateCmd(0x80200000, 0); |
||||
|
|
||||
|
SdioSendCmd(0xa0008000, 0x0, 0, "MMC_GO_IDLE_STATE"); |
||||
|
|
||||
|
SdioSendCmd(0xa0000148, 0x000001aa, 8, "SD_SEND_IF_COND"); |
||||
|
|
||||
|
u32 OCR_BUSY = 0x80000000; |
||||
|
for (i = 0; i < 100; i++) |
||||
|
{ |
||||
|
SdioSendCmd(0xa0000177, 0x0, 55, "MMC_APP_CMD"); |
||||
|
|
||||
|
SdioSendCmd(0xa0000069, 0x41ff8000, 41, "SD_APP_OP_COND"); |
||||
|
|
||||
|
if (OCR_BUSY & FSDIO_IN32(FSDIO_REG_RESP0_OFFSET)) |
||||
|
{ |
||||
|
printf("CMD 8 success \r\n"); |
||||
|
break; |
||||
|
} |
||||
|
} |
||||
|
|
||||
|
SdioSendCmd(0xb000014b, 0x0, 11, "Voltage Switch"); |
||||
|
|
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x0); |
||||
|
FSDIO_OUT32(FSDIO_REG_UHS_REG_EXT_OFFSET, 0x0); |
||||
|
FSDIO_OUT32(FSDIO_REG_UHS_REG_OFFSET, 0x1); |
||||
|
FSDIO_OUT32(FSDIO_REG_UHS_REG_EXT_OFFSET, 0x00000502); |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x1); |
||||
|
SdioSendPrivateCmd(0x80200000, 0); |
||||
|
|
||||
|
SdioSendCmd(0xa00001c2, 0x0, 2, "MMC_ALL_SEND_CID"); |
||||
|
|
||||
|
SdioSendCmd(0xa0000143, 0x0, 3, "SD_SEND_RELATIVE_ADDR"); |
||||
|
u32 reg_val = FSDIO_IN32(FSDIO_REG_RESP0_OFFSET); |
||||
|
u32 t = ((GENMASK(20, 4) ®_val) >> 4); |
||||
|
printf("t: 0x%x\r\n", t); /* 0x1a0 */ |
||||
|
|
||||
|
/* 缺cmd9 */ |
||||
|
|
||||
|
SdioSendCmd(0xa0000147, t, 7, "MMC_SELECT_CARD"); |
||||
|
|
||||
|
//sd初始化完成
|
||||
|
//设置时钟25M
|
||||
|
/*
|
||||
|
printf("====update clk (25M)=======\r\n"); |
||||
|
FSDIO_OUT32((FSDIO_REG_UHS_REG_EXT_OFFSET), 0x0); |
||||
|
FSDIO_OUT32((FSDIO_REG_UHS_REG_EXT_OFFSET), 0x202); |
||||
|
printf("CCLK_READY: 0x%x\r\n", FSDIO_IN32((FSDIO_REG_CCLK_READY_OFFSET))); |
||||
|
//read bit[1] ==1
|
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x0); |
||||
|
|
||||
|
printf("use clkdiv=0x080710\r\n"); |
||||
|
FSDIO_OUT32((FSDIO_REG_CLKDIV_OFFSET), 0x080710); |
||||
|
|
||||
|
FSDIO_OUT32((FSDIO_REG_CLKENA_OFFSET), 0x1); |
||||
|
SdioSendPrivateCmd(0x80200000, 0); |
||||
|
fsleep_microsec(1); |
||||
|
printf("CMD: 0x%x\r\n", FSDIO_IN32((FSDIO_REG_CMD_OFFSET))); |
||||
|
printf("====update clk done =======\r\n"); */ |
||||
|
|
||||
|
fsleep_microsec(2); |
||||
|
|
||||
|
//设置4线宽模式：
|
||||
|
SdioSendCmd(0xa0000177, t, 55, "MMC_APP_CMD"); |
||||
|
|
||||
|
FSDIO_OUT32(FSDIO_REG_CTYPE_OFFSET, 1); |
||||
|
SdioSendCmd(0xa0000146, 0x00000002, 6, "MMC_SWITCH"); |
||||
|
printf("set 4 width\r\n"); |
||||
|
|
||||
|
SdioSendCmd(0xa0000150, 0x00000200, 16, "MMC_SET_BLOCKLEN"); |
||||
|
printf("set block length\r\n"); |
||||
|
|
||||
|
//设置描述符表，写，首地址：0x234fb02000
|
||||
|
//FtOut32(0x234fb00000 0x8000002c
|
||||
|
FtOut32(0x234fb00000, 0x8000000c); |
||||
|
FtOut32(0x234fb00004, 0x0); |
||||
|
FtOut32(0x234fb00008, 0x200); |
||||
|
FtOut32(0x234fb0000c, 0x0); |
||||
|
FtOut32(0x234fb00010, 0x4fb02000); |
||||
|
FtOut32(0x234fb00014, 0x23); |
||||
|
FtOut32(0x234fb00018, 0x0); |
||||
|
FtOut32(0x234fb0001c, 0x0); |
||||
|
|
||||
|
//写数据物理地址：234f002000 及地址+8K偏移：
|
||||
|
FtOut32(0x234fb02000, 0x55555555); |
||||
|
FtOut32(0x234fb02004, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02008, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0200c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02010, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02014, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02018, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0201c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02020, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02024, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02028, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0202c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02030, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02034, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02038, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0203c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02040, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02044, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02048, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0204c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02050, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02054, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02058, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb0205c, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02060, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02064, 0xaaaaaaaa); |
||||
|
FtOut32(0x234fb02068, 0x55555555); |
||||
|
|
||||
|
/* invalidate cache for write buffer */ |
||||
|
FCacheDCacheInvalidateRange(0x234fb02000, 0x200); |
||||
|
|
||||
|
//10）设置写描述符地址：
|
||||
|
FSDIO_OUT32((FSDIO_REG_DESC_LIST_ADDRL_OFFSET), 0x4fb00000); |
||||
|
FSDIO_OUT32((FSDIO_REG_DESC_LIST_ADDRH_OFFSET), 0x23); |
||||
|
FSDIO_OUT32(FSDIO_REG_BLKSIZ_OFFSET, 0x200); |
||||
|
FSDIO_OUT32(FSDIO_REG_BYTCNT_OFFSET, 0x200); |
||||
|
|
||||
|
SdioSendCmd(0xa0000758, 0, 24, "MMC_WRITE_BLOCK_SINGLE"); |
||||
|
SdioWaitDat(); |
||||
|
|
||||
|
//设置读描述符表：描述符表基地址addr:234f000000
|
||||
|
//FtOut32(0x234fb00000 0x8000002c
|
||||
|
FtOut32(0x234fb00000,0x8000000c); |
||||
|
FtOut32(0x234fb00004,0x0); |
||||
|
FtOut32(0x234fb00008,0x200); |
||||
|
FtOut32(0x234fb0000c,0x0); |
||||
|
FtOut32(0x234fb00010,0x4fb01000); |
||||
|
FtOut32(0x234fb00014,0x23); |
||||
|
FtOut32(0x234fb00018,0x0); |
||||
|
FtOut32(0x234fb0001c,0x0); |
||||
|
|
||||
|
//10）设置读描述符地址：
|
||||
|
FSDIO_OUT32((FSDIO_REG_DESC_LIST_ADDRL_OFFSET), 0x4fb00000); |
||||
|
FSDIO_OUT32((FSDIO_REG_DESC_LIST_ADDRH_OFFSET), 0x23); |
||||
|
FSDIO_OUT32(FSDIO_REG_BLKSIZ_OFFSET, 0x200); |
||||
|
FSDIO_OUT32((FSDIO_REG_BYTCNT_OFFSET), 0x200); |
||||
|
|
||||
|
FtOut32(0x234fb01000,0); |
||||
|
FtOut32(0x234fb01004,0); |
||||
|
FtOut32(0x234fb01008,0); |
||||
|
FtOut32(0x234fb0100c,0); |
||||
|
FtOut32(0x234fb01010,0); |
||||
|
FtOut32(0x234fb01014,0); |
||||
|
FtOut32(0x234fb01018,0); |
||||
|
FtOut32(0x234fb0101c,0); |
||||
|
FtOut32(0x234fb01020,0); |
||||
|
FtOut32(0x234fb01024,0); |
||||
|
FtOut32(0x234fb01028,0); |
||||
|
FtOut32(0x234fb0102c,0); |
||||
|
FtOut32(0x234fb01030,0); |
||||
|
FtOut32(0x234fb01034,0); |
||||
|
FtOut32(0x234fb01038,0); |
||||
|
FtOut32(0x234fb0103c,0); |
||||
|
FtOut32(0x234fb01040,0); |
||||
|
FtOut32(0x234fb01044,0); |
||||
|
FtOut32(0x234fb01048,0); |
||||
|
|
||||
|
SdioSendCmd(0xa0000351, 0x0, 17, "MMC_READ_BLOCK_SINGLE"); |
||||
|
SdioWaitDat(); |
||||
|
|
||||
|
FCacheDCacheInvalidateRange(0x234fb01000, 0x200); |
||||
|
FtDumpHexByte((u8 *)(void *)0x234fb01000, 30); |
||||
|
|
||||
|
return 0; |
||||
|
} |
||||
|
SHELL_EXPORT_CMD(SHELL_CMD_TYPE(SHELL_TYPE_CMD_MAIN), sdio_verify, SdioVerifyEntry, test sdio register); |
||||
Some files were not shown because too many files changed in this diff
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Reference in new issue