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!176 修复d2000下的spi例程bug,适配RTEMS

1. 修复在d2000下的spi例程bug。
2. 适配RTEMS.
pull/177/head
liyilun 2 months ago
committed by huanghe
parent
commit
cfcda52ca0
  1. 15
      arch/armv8/common/fgic_its.c
  2. 25
      doc/ChangeLog.md
  3. 2
      doc/reference/driver/fspim.md
  4. 6
      drivers/spi/fspim/fspim.c
  5. 2
      drivers/spi/fspim/fspim.h
  6. 8
      drivers/spi/fspim/fspim_g.c
  7. 4
      drivers/spi/fspim/fspim_hw.c
  8. 2
      example/peripherals/spi/src/spim_intr_loopback_mode_example.c
  9. 2
      example/peripherals/spi/src/spim_intr_trigger_test.c
  10. 2
      example/peripherals/spi/src/spim_polled_loopback_mode_example.c
  11. 97
      example/peripherals/spi/src/spim_pressure_test.c
  12. 1
      soc/d2000/fcpu_affinity_mask.c
  13. 7
      soc/d2000/fparameters.h
  14. 1
      soc/e2000/d/fcpu_affinity_mask.c
  15. 4
      soc/e2000/fparameters_comm.h
  16. 1
      soc/e2000/q/fcpu_affinity_mask.c
  17. 1
      soc/e2000/s/fcpu_affinity_mask.c
  18. 1
      soc/ft2004/fcpu_affinity_mask.c
  19. 7
      soc/ft2004/fparameters.h
  20. 1
      soc/pd2308/fcpu_affinity_mask.c
  21. 5
      soc/pd2308/fparameters.h
  22. 1
      soc/phytiumpi/fcpu_affinity_mask.c
  23. 4
      soc/phytiumpi/fparameters_comm.h
  24. 1
      soc/qemu_virt_64/fcpu_affinity_mask.c
  25. 2
      third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c

15
arch/armv8/common/fgic_its.c

@ -720,13 +720,22 @@ FError FGicItsDeviceIdInit(const FGic *instanse_p, u32 device_id,
}
}
if((!data->device_table[i].valid_flg) || (i == FGIC_DEVICE_MAX_ID))
if (i == FGIC_DEVICE_MAX_ID)
{
if(alloc_addr)
{
tlsf_free((tlsf_t)data->mem_poll_p,(void *)alloc_addr) ;
tlsf_free((tlsf_t)data->mem_poll_p,(void *)alloc_addr);
}
tlsf_free((tlsf_t)data->mem_poll_p,(void *)itt);
return FGIC_ITS_DEVICE_TABLE_IS_EXHAUST;
}
else if (!data->device_table[i].valid_flg)
{
if(alloc_addr)
{
tlsf_free((tlsf_t)data->mem_poll_p,(void *)alloc_addr);
}
tlsf_free((tlsf_t)data->mem_poll_p,(void *)itt) ;
tlsf_free((tlsf_t)data->mem_poll_p,(void *)itt);
return FGIC_ITS_DEVICE_TABLE_IS_EXHAUST;
}

25
doc/ChangeLog.md

@ -1,3 +1,28 @@
# Phytium Standalone SDK 2024-09-10 ChangeLog
Change Log since 2024-09-09
## example
- repair error about spi sclk_hz on d2000
## driver
- rename freq_hz to sclk_hz
- reset sclk_hz in fspim_g.c
# Phytium Standalone SDK 2024-09-09 ChangeLog
Change Log since 2024-09-05
## soc
- remove ftypes.h from fparameters.h
## arch
- fix fgic_its.c boundary issue
# Phytium Standalone SDK 2024-09-05 ChangeLog
Change Log since 2024-09-05

2
doc/reference/driver/fspim.md

@ -74,7 +74,7 @@ typedef struct
u32 irq_num; /* Device interrupt id */
u32 irq_prority; /* Device interrupt priority */
FSpimSlaveDevice slave_dev_id; /* Slave device id */
u32 freq_hz; /* Clock frequency in Hz */
u32 sclk_hz; /* Spi transfer clock frequency in Hz */
FSpimTransByte n_bytes; /* Bytes in transfer */
FSpimCpolType cpol; /* Polarity of the clock */
FSpimCphaType cpha; /* Phase of the clock */

6
drivers/spi/fspim/fspim.c

@ -191,7 +191,7 @@ FError FSpimReset(FSpim *instance_p)
FSpimSetRxDMALevel(base_addr, instance_p->config.rx_dma_level);
FSpimSetTxDMALevel(base_addr, instance_p->config.tx_dma_level);
ret = FSpimSetSpeed(base_addr, instance_p->config.freq_hz);
ret = FSpimSetSpeed(base_addr, instance_p->config.sclk_hz);
if (FSPIM_SUCCESS != ret)
{
return ret;
@ -264,12 +264,12 @@ FError FSpimSetOption(FSpim *instance_p, FSpimOption option, u32 value)
{
return ret;
}
instance_p->config.freq_hz = value;
instance_p->config.sclk_hz = value;
FSPIM_INFO("Set spim freqency to %d", value);
}
else
{
FSPIM_ERROR("Input error, spim freqency value should be no more than 25M.");
FSPIM_ERROR("Input error, spim freqency value should be no more than %ld.", FSPI_CLK_FREQ_HZ / 2);
return FSPIM_ERR_INVAL_PARAM;
}
}

2
drivers/spi/fspim/fspim.h

@ -147,7 +147,7 @@ typedef struct
u32 irq_prority; /* Device interrupt priority */
FSpimWorkMode work_mode; /* Device work mode */
FSpimSlaveDevice slave_dev_id; /* Slave device id */
u32 freq_hz; /* Clock frequency in Hz */
u32 sclk_hz; /* Spi transfer clock frequency in Hz */
FSpimTransByte n_bytes; /* Bytes in transfer */
FSpimCpolType cpol; /* Polarity of the clock */
FSpimCphaType cpha; /* Phase of the clock */

8
drivers/spi/fspim/fspim_g.c

@ -51,7 +51,7 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
.irq_prority = 0,
.work_mode = FSPIM_DEV_MASTER_MODE,
.slave_dev_id = FSPIM_SLAVE_DEV_0,
.freq_hz = 5000000,
.sclk_hz = FSPI_DEFAULT_SCLK,
.n_bytes = 1,
.en_test = FALSE,
.en_dma = FALSE,
@ -70,7 +70,7 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
.irq_prority = 0,
.work_mode = FSPIM_DEV_MASTER_MODE,
.slave_dev_id = FSPIM_SLAVE_DEV_0,
.freq_hz = 5000000,
.sclk_hz = FSPI_DEFAULT_SCLK,
.n_bytes = 1,
.en_test = FALSE,
.en_dma = FALSE,
@ -89,7 +89,7 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
.irq_prority = 0,
.work_mode = FSPIM_DEV_MASTER_MODE,
.slave_dev_id = FSPIM_SLAVE_DEV_0,
.freq_hz = 5000000,
.sclk_hz = FSPI_DEFAULT_SCLK,
.n_bytes = 1,
.en_test = FALSE,
.en_dma = FALSE,
@ -110,7 +110,7 @@ const FSpimConfig FSPIM_CONFIG_TBL[FSPI_NUM] =
.irq_prority = 0,
.work_mode = FSPIM_DEV_MASTER_MODE,
.slave_dev_id = FSPIM_SLAVE_DEV_0,
.freq_hz = 5000000,
.sclk_hz = FSPI_DEFAULT_SCLK,
.n_bytes = 1,
.en_test = FALSE,
.en_dma = FALSE,

4
drivers/spi/fspim/fspim_hw.c

@ -125,7 +125,7 @@ FError FSpimSetSpeed(uintptr base_addr, u32 clk_freq)
if (clk_freq == 0)
{
FSPIM_ERROR("Input spi clock frequency is %d => do not support, this parameter should not be 0.");
FSPIM_ERROR("Input spi clock frequency is %d => do not support, this parameter should not be 0.", clk_freq);
return FSPIM_ERR_NOT_SUPPORT;
}
else
@ -148,7 +148,7 @@ FError FSpimSetSpeed(uintptr base_addr, u32 clk_freq)
}
else
{
FSPIM_ERROR("Input spi clock divider is %d => do not support, this parameter should be set as an even from 2 to 65534.", clk_div);
FSPIM_ERROR("Input spi clock frequency is %ld, this parameter be set wrong. spi clock divider = %d, this parameter should be an even from 2 to 65534.", clk_freq, clk_div);
return FSPIM_ERR_NOT_SUPPORT;
}
}

2
example/peripherals/spi/src/spim_intr_loopback_mode_example.c

@ -145,7 +145,7 @@ static FError FSpimSetupConfig(void)
spim_config.cpha = FSPIM_CPHA_2_EDGE;
spim_config.cpol = FSPIM_CPOL_LOW;
spim_config.n_bytes = FSPIM_1_BYTE;
spim_config.freq_hz = 25000000;
spim_config.sclk_hz = FSPI_DEFAULT_SCLK;
spim_config.trans_way = TRANS_WAY_POLL;
ret = FSpimCfgInitialize(spim_p, &spim_config);
if (FSPIM_SUCCESS != ret)

2
example/peripherals/spi/src/spim_intr_trigger_test.c

@ -242,7 +242,7 @@ static FError FSpimSetupConfig(void)
spim_config.cpha = FSPIM_CPHA_2_EDGE;
spim_config.cpol = FSPIM_CPOL_HIGH;
spim_config.n_bytes = FSPIM_1_BYTE;
spim_config.freq_hz = 5000000;
spim_config.sclk_hz = FSPI_DEFAULT_SCLK;
ret = FSpimCfgInitialize(spim_p, &spim_config);
if (FSPIM_SUCCESS != ret)
{

2
example/peripherals/spi/src/spim_polled_loopback_mode_example.c

@ -141,7 +141,7 @@ static FError FSpimSetupConfig(void)
spim_config.cpha = FSPIM_CPHA_2_EDGE;
spim_config.cpol = FSPIM_CPOL_LOW;
spim_config.n_bytes = FSPIM_1_BYTE;
spim_config.freq_hz = 25000000;
spim_config.sclk_hz = FSPI_DEFAULT_SCLK;
spim_config.trans_way = TRANS_WAY_POLL;
ret = FSpimCfgInitialize(spim_p, &spim_config);
if (FSPIM_SUCCESS != ret)

97
example/peripherals/spi/src/spim_pressure_test.c

@ -32,7 +32,7 @@
#include "sdkconfig.h"
#ifndef SDK_CONFIG_H__
#warning "Please include sdkconfig.h"
#warning "Please include sdkconfig.h"
#endif
#include "fio_mux.h"
@ -81,12 +81,9 @@ static volatile boolean tx_dma_done = FALSE;
#endif
#define EN_TEST TRUE
#define FSPIM_DELAY_MS 50000 /*timer Delay in milli-seconds */
#define FSPIM_DELAY_MS 100000 /*timer Delay in milli-seconds */
enum
{
@ -115,8 +112,6 @@ static boolean rx_done = FALSE;
static u8 tx_buff[RX_TX_LENGTH_MAX] = {0};
static u8 rx_buff[RX_TX_LENGTH_MAX] = {0};
#if defined(CONFIG_D2000_TEST_BOARD) || defined(CONFIG_FT2004_DSK_BOARD)
#include "fgpio.h"
/* D2000/FT2000-4 使用GPIO引脚控制片选信号 */
@ -197,7 +192,7 @@ static inline u32 FSpimTickCastSeconds(u64 tick)
static inline u32 FSpimTickCastMilliSec(u64 tick)
{
return (u32)(tick % (u64) GenericTimerFrequecy() / (((u64)GenericTimerFrequecy() * 1 + 999) / 1000));
return (u32)(tick % (u64)GenericTimerFrequecy() / (((u64)GenericTimerFrequecy() * 1 + 999) / 1000));
}
static int FSpimClearConfig(FSpim *spim_p)
@ -217,6 +212,25 @@ static int FSpimClearConfig(FSpim *spim_p)
return FSPIM_OPS_OK;
}
static int FSpimIntrWaitRxDone(int timeout)
{
while (TRUE != rx_done)
{
fsleep_microsec(2);
if (0 >= --timeout)
{
break;
}
}
if (0 >= timeout)
{
FSPIM_ERROR("Wait for rx timeout");
return FSPIM_OPS_TRANS_TIMEOUT;
}
return FSPIM_OPS_OK;
}
static void FSpimSendRxDoneEvent(void *instance_p, void *param)
{
@ -464,7 +478,7 @@ static FError FSpimSetupConfig(FSpimTransWay trans_way)
spim_config.cpha = FSPIM_CPHA_2_EDGE;
spim_config.cpol = FSPIM_CPOL_LOW;
spim_config.n_bytes = FSPIM_1_BYTE;
spim_config.freq_hz = 25000000;
spim_config.sclk_hz = FSPI_DEFAULT_SCLK;
spim_config.trans_way = trans_way;
ret = FSpimCfgInitialize(spim_p, &spim_config);
if (FSPIM_SUCCESS != ret)
@ -493,18 +507,16 @@ static void printProgressBar(int progress, int total)
fflush(stdout);
}
int FSpimPressureTest(void)
{
FError ret = 0;
FSpim *spim_instance = &spim;
u32 trans_size = RX_TX_LENGTH_MAX;;
u32 trans_size = RX_TX_LENGTH_MAX;
u32 total_times = 50;
int current_times = 0;
int poll_success_flag = 0;
int intr_success_flag = 0;
int ddma_success_flag = 1;
@ -533,7 +545,7 @@ int FSpimPressureTest(void)
total_ticks_poll += FSpimGetTick() - start_ticks;
ret += compare_tx_rx(trans_size);
current_times++;
if(current_times % 10 == 0)
if (current_times % 10 == 0)
{
printProgressBar(current_times, total_times);
}
@ -554,7 +566,6 @@ int FSpimPressureTest(void)
trans_size);
}
/* 中断模式下的持续压力测试,总共执行total_times次 */
current_times = 0;
@ -562,7 +573,6 @@ int FSpimPressureTest(void)
FSpimSetupConfig(TRANS_WAY_INTERRUPT);
printf("Spim pressure test start (interrupt).\r\n");
FSpimCsOnOff(TRUE);
@ -570,19 +580,31 @@ int FSpimPressureTest(void)
while (current_times < total_times)
{
FSpimSetupInterrupt(spim_instance);
InitRxTxBuff(trans_size);
start_ticks = FSpimGetTick();
ret += FSpimTransferByInterrupt(spim_instance, tx_buff, rx_buff, trans_size);
while(FALSE == rx_done);
if (FSPIM_OPS_OK != FSpimIntrWaitRxDone(FSPIM_DELAY_MS))
{
FSPIM_DEBUG("Wait for rx timeout !!!");
ret = FSPIM_OPS_TRANS_TIMEOUT;
goto exit;
}
total_ticks_intr += FSpimGetTick() - start_ticks;
ret += compare_tx_rx(trans_size);
current_times++;
if(current_times % 10 == 0)
if (current_times % 10 == 0)
{
printProgressBar(current_times, total_times);
}
}
exit:
if (ret != FT_SUCCESS)
{
printf("%s@%d: Spim (interrupt mode) pressure test [failure].\r\n", __func__, __LINE__);
@ -600,10 +622,10 @@ int FSpimPressureTest(void)
FSpimCsOnOff(FALSE);
FSpimClearConfig(spim_instance);
#ifdef CONFIG_ENABLE_FDDMA
u64 total_ticks_ddma = 0;
ddma_success_flag = 0;
u32 timeout = 100000;
/* DDMA 模式下的持续压力测试,总共执行total_times次 */
current_times = 0;
ret = 0;
@ -623,12 +645,42 @@ int FSpimPressureTest(void)
ret += FSpimTransferDMA(spim_instance);
FDdmaStart(&ddma_instance);
while (!tx_dma_done || !rx_dma_done);
while (FALSE == tx_dma_done)
{
if (--timeout <= 0)
{
break;
}
fsleep_millisec(1);
}
if (0 >= timeout)
{
FSPIM_ERROR("Wait DDMA TX end timeout %d!", timeout);
}
timeout = 100000;
while (FALSE == rx_dma_done)
{
if (--timeout <= 0)
{
break;
}
fsleep_millisec(1);
}
if (0 >= timeout)
{
FSPIM_ERROR("Wait DDMA RX end timeout %d!", timeout);
}
total_ticks_ddma += FSpimGetTick() - start_ticks;
ret += compare_dma_tx_rx(trans_size);
current_times++;
if(current_times % 10 == 0)
if (current_times % 10 == 0)
{
printProgressBar(current_times, total_times);
}
@ -654,8 +706,6 @@ int FSpimPressureTest(void)
}
#endif
if (poll_success_flag && intr_success_flag && ddma_success_flag)
{
printf("%s@%d: Spim pressure test [success].\r\n", __func__, __LINE__);
@ -665,5 +715,4 @@ int FSpimPressureTest(void)
printf("%s@%d: Spim pressure test [failure].\r\n", __func__, __LINE__);
}
return FT_SUCCESS;
}

1
soc/d2000/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
/**
* @name: GetCpuMaskToAffval

7
soc/d2000/fparameters.h

@ -29,10 +29,6 @@ extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define SOC_TARGET_D2000
#define CORE0_AFF 0x0
@ -269,7 +265,8 @@ extern "C"
#define FSPI1_BASE_ADDR 0x28013000
#define FSPI0_ID 0
#define FSPI1_ID 1
#define FSPI_CLK_FREQ_HZ 48000000
#define FSPI_CLK_FREQ_HZ 48000000U
#define FSPI_DEFAULT_SCLK 4800000U
#define FSPI_NUM 2
#define FSPI0_IRQ_NUM 50
#define FSPI1_IRQ_NUM 51

1
soc/e2000/d/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{

4
soc/e2000/fparameters_comm.h

@ -30,9 +30,6 @@ extern "C"
#endif
/***************************** Include Files *********************************/
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define SOC_TARGET_E2000
/************************** Constant Definitions *****************************/
@ -280,6 +277,7 @@ extern "C"
#define FSPI3_IRQ_NUM 194U
#define FSPI_CLK_FREQ_HZ 50000000U
#define FSPI_DEFAULT_SCLK 5000000U
#define FSPI_NUM 4U
#define FSPI_DMA_CAPACITY BIT(0)

1
soc/e2000/q/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{

1
soc/e2000/s/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{

1
soc/ft2004/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{

7
soc/ft2004/fparameters.h

@ -29,10 +29,6 @@ extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define SOC_TARGET_FT2004
#define CORE0_AFF 0x0
@ -186,7 +182,8 @@ extern "C"
#define FSPI1_BASE_ADDR 0x28013000
#define FSPI0_ID 0
#define FSPI1_ID 1
#define FSPI_CLK_FREQ_HZ 48000000
#define FSPI_CLK_FREQ_HZ 48000000U
#define FSPI_DEFAULT_SCLK 4800000U
#define FSPI_NUM 2
#define FSPI0_IRQ_NUM 50
#define FSPI1_IRQ_NUM 51

1
soc/pd2308/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
const int cluster_ids[FCORE_NUM] = {
CORE0_AFF,

5
soc/pd2308/fparameters.h

@ -29,10 +29,6 @@ extern "C"
{
#endif
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
#define SOC_TARGET_PD2308
#define CORE0_AFF 0x000
@ -266,6 +262,7 @@ enum
#define FSPI1_IRQ_NUM 111U
#define FSPI_CLK_FREQ_HZ 50000000U
#define FSPI_DEFAULT_SCLK 5000000U
#define PLAT_AHCI_HOST_MAX_COUNT 5
#define AHCI_BASE_0 0

1
soc/phytiumpi/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
u32 GetCpuMaskToAffval(u32 *cpu_mask, u32 *cluster_id, u32 *target_list)
{

4
soc/phytiumpi/fparameters_comm.h

@ -30,9 +30,6 @@ extern "C"
#endif
/***************************** Include Files *********************************/
#if !defined(__ASSEMBLER__)
#include "ftypes.h"
#endif
/************************** Constant Definitions *****************************/
/* CACHE */
@ -251,6 +248,7 @@ extern "C"
#define FSPI3_IRQ_NUM 194U
#define FSPI_CLK_FREQ_HZ 50000000U
#define FSPI_DEFAULT_SCLK 5000000U
#define FSPI_NUM 4U
#define FSPI_DMA_CAPACITY BIT(0)

1
soc/qemu_virt_64/fcpu_affinity_mask.c

@ -22,6 +22,7 @@
* 1.0 zhangyan 2023/11/6 init commit
*/
#include "fparameters.h"
#include "ftypes.h"
/**
* @name: GetCpuMaskToAffval

2
third-party/sfud-1.1.0/ports/fspim/fspim_sfud_core.c

@ -608,7 +608,7 @@ sfud_err FSpimProbe(sfud_flash *flash)
input_cfg.cpha = FSPIM_CPHA_1_EDGE;
input_cfg.cpol = FSPIM_CPOL_LOW;
input_cfg.n_bytes = FSPIM_1_BYTE; /* sfud only support 1 bytes read/write */
input_cfg.freq_hz = 12500000;
input_cfg.sclk_hz = FSPI_DEFAULT_SCLK;
#ifdef CONFIG_SFUD_TRANS_MODE_DDMA

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