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| Author | SHA1 | Date |
|---|---|---|
zhangyan
|
153686dbec | 11 months ago |
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zhangyan
|
c6506df28d | 12 months ago |
|
zhangyan
|
84ecd7f76f | 12 months ago |
213 changed files with 24 additions and 31696 deletions
@ -1,13 +0,0 @@ |
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### 该问题是怎么引起的？ |
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### 重现步骤 |
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### 报错信息 |
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@ -1,14 +0,0 @@ |
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### 相关的Issue |
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### 原因（目的、解决的问题等） |
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### 描述（做了什么，变更了什么） |
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### 测试用例（新增、改动、可能影响的功能） |
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@ -1,61 +0,0 @@ |
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# Prerequisites |
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*.d |
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*.uimg |
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*.img |
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|
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# Object files |
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*.o |
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*.ko |
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*.obj |
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*.elf |
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|
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# Linker output |
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*.ilk |
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*.map |
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*.exp |
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|
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# Precompiled Headers |
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*.gch |
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*.pch |
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|
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# Libraries |
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*.lib |
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*.a |
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*.la |
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*.lo |
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|
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# Shared objects (inc. Windows DLLs) |
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*.dll |
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*.so |
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*.so.* |
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*.dylib |
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|
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# Executables |
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*.exe |
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*.out |
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*.app |
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*.i*86 |
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*.x86_64 |
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*.hex |
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*.bin |
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*.dis |
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app* |
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|
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# Debug files |
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*.dSYM/ |
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*.su |
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*.idb |
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*.pdb |
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|
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# Kernel Module Compile Results |
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*.mod* |
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*.cmd |
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.tmp_versions/ |
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modules.order |
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Module.symvers |
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Mkfile.old |
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dkms.conf |
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|
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# Download gcc compiler |
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/tools/gcc-*/* |
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/tools/gcc-* |
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@ -1,30 +0,0 @@ |
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{ |
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// Use IntelliSense to learn about possible attributes. |
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// Hover to view descriptions of existing attributes. |
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// For more information, visit: https://go.microsoft.com/fwlink/?linkid=830387 |
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"version": "0.2.0", |
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"configurations": [ |
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{ |
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"name": "(gdb) Launch", |
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"type": "cppdbg", |
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"request": "launch", |
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"program": "${workspaceFolder}/baremetal/qemu_genric_timer_irq/qemu_generic_irq_test", # 需要调试的二进制文件 |
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"args": [], |
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"stopAtEntry": true, |
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"cwd": "${workspaceFolder}", |
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"environment": [], |
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"externalConsole": true, |
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"MIMode": "gdb", |
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"miDebuggerPath": "/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 |
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// "miDebuggerPath": "D:/ubuntu/rootfs/usr/local/bin/aarch64-linux-gnu-gdb", # gdb 工具的位置 |
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"miDebuggerServerAddress": "127.0.0.1:1234", # gdb 开启之后的端口号 |
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"setupCommands": [ |
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{ |
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"description": "Enable pretty-printing for gdb", |
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"text": "-enable-pretty-printing", |
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"ignoreFailures": true |
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} |
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] |
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} |
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] |
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} |
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@ -1,22 +0,0 @@ |
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{ |
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"files.associations": { |
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"irq_test.h": "c", |
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"parameters.h": "c", |
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"ft_gicv3.h": "c", |
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"ft_debug.h": "c", |
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"ft_types.h": "c", |
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"gicv3.h": "c", |
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"exception.h": "c", |
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"generic_timer.h": "c", |
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"freertos.h": "c", |
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"fsleep.h": "c", |
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"printf-stdarg.h": "c", |
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"ft_assert.h": "c", |
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"ft_os_uart.h": "c", |
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"event_groups.h": "c", |
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"pl011_uart.h": "c", |
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"early_uart.h": "c", |
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"message_buffer.h": "c", |
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"early_uart.h": "c" |
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} |
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} |
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@ -1,73 +0,0 @@ |
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# entry of menuconfig |
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# mainmenu "Phytium Standalone SDK Configuration" |
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|
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menu "Target Setting" |
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choice BUILD_TARGET_ARCH_TYPE |
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prompt "Arch" |
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default TARGET_ARMV8_AARCH32 |
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help |
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Select arch for build |
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config TARGET_ARMV8_AARCH32 |
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bool "Armv8 Aarch32" |
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config TARGET_ARMV8_AARCH64 |
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bool "Armv8 Aarch64" |
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config TARGET_ARMV7 |
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bool "Armv7" |
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endchoice # BUILD_TARGET_ARCH_TYPE |
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|
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choice BUILD_TARGET_CHIP_TYPE |
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prompt "Chip" |
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default TARGET_AARCH32_QEMU |
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help |
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Select chip type for build |
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|
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config TARGET_F2000_4 |
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bool "FT2000-4" |
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config TARGET_AARCH32_QEMU |
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bool "QEMU-AARCH32(V9-Express)" |
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config TARGET_AARCH64_QEMU |
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bool "QEMU-AARCH64" |
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config TARGET_E2000 |
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bool "E2000" |
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endchoice # BUILD_TARGET_CHIP_TYPE |
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endmenu |
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|
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menu "Building Option" |
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choice SDK_ENVI_TYPE |
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prompt "SDK Develope Platfrom" |
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default ENVI_UBUNTU_20_04 |
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help |
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SDK development host environment type. |
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|
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config ENVI_UBUNTU_20_04 |
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bool |
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prompt "Ubuntu 20.04" |
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config ENVI_WINDOWS10_MINGW |
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bool |
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prompt "MinGW on Windows10" |
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endchoice # SDK_ENVI_TYPE |
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menu "Cross-Compiler Setting" |
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config COMPILER_NO_STD_STARUP |
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bool "Non-Use GCC Provide Startup Files" |
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default y if TARGET_BARE_METAL |
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help |
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Select if do not want to gcc provide startup file |
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config USE_EXT_COMPILER |
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bool "Use User-Specified Compiler" |
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default n |
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config EXT_COMPILER_PREFIX |
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depends on USE_EXT_COMPILER |
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string "" |
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default "arm-none-eabi-" if TARGET_ARMV8_AARCH32 |
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default "aarch64-none-elf-" if TARGET_ARMV8_AARCH64 |
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endmenu |
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source "$(SDK_ROOT)/make/ld/Kconfig" |
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endmenu |
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# add all kconfig source files, but specify their depends |
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source "$(SDK_ROOT)/bsp/Kconfig" |
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source "$(SDK_ROOT)/lib/Kconfig" |
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@ -1,201 +0,0 @@ |
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Apache License |
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Version 2.0, January 2004 |
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http://www.apache.org/licenses/ |
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|
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TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION |
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@ -1,23 +0,0 @@ |
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<!-- |
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0. |
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* |
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* @Date: 2021-07-02 09:04:12 |
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* @LastEditTime: 2021-07-02 09:45:42 |
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* @Description: This files is for |
|||
* |
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* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
--> |
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# Phytium-Standalone-SDK |
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|
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## Install SDK |
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|
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``` |
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$ ./sdk/export.sh |
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fatal: not in a git directory |
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Gcc compiler package non found!!! |
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$ source ~/.profile |
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``` |
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@ -1,190 +0,0 @@ |
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<!-- |
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* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
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* |
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* SPDX-License-Identifier: Apache-2.0. |
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* |
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* @Date: 2021-07-01 18:12:33 |
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* @LastEditTime: 2021-07-01 19:40:51 |
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* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
--> |
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|
|||
# Phytium-Standalone-SDK |
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|
|||
## 1. 介绍 |
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本项目发布了Phytium系列CPU的BSP源码，Baremetal参考例程及其配置编译工具 |
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|
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## 2. Ubuntu 20.04 x86_64环境下使用Standalone SDK |
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|
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### 2.1. 配置SDK |
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|
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#### 2.1.1. 下载SDK源代码 |
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|
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- 通过Gitee拉取源代码 |
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``` |
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$ git clone https://gitee.com/zhugengyu/phytium-mangosteen-sdk.git ./ft_sdk |
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$ cd ./ft_sdk |
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``` |
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|
|||
#### 2.1.2 选择在线方式安装SDK |
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|
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- 选择在线方式安装Standalone SDK在~/ft_sdk |
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``` |
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$ ./export.sh -online |
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|
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``` |
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 |
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|
|||
#### 2.1.3 选择离线方式安装SDK |
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|
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- 在ARM官网下载[AARCH32](https://developer.arm.com/-/media/Files/downloads/gnu-rm/10-2020q4/gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz)和[AARCH64](https://developer.arm.com/-/media/Files/downloads/gnu-a/10.2-2020.11/binrel/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz)编译器 |
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- 将下载的编译器安装包放置在'~/ft_sdk/tools'路径下 |
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- 安装SDK开发环境，没有打印错误信息表示安装成功 |
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``` |
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$ ./export.sh |
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Please type in 'source ./export.sh' |
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Phytium Embedded SDK Setup Done!! |
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Install AARCH32 Compiler at /home/ubuntu/ft_sdk/tools/gcc-arm-none-eabi-10-2020-q4-major |
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Install AARCH64 Compiler at /home/ubuntu/ft_sdk/tools/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf |
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SDK Path is set as /home/ubuntu/ft_sdk/standalone-sdk-master |
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``` |
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|
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- **通过离线/在线方式完成安装后，关闭当前窗口或者运行以下命令，立即生效SDK环境变量** |
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``` |
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$ source ~/.profile |
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``` |
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|
|||
### 2.2 快速使用例程 |
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|
|||
#### 2.2.1 使用FT2000-4开发板，快速体验SDK |
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>ft_sdk/baremetal/example/aarch32/hello_world |
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- 编译例程hello_world |
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|
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 |
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|
|||
- 通过TFTP服务器下载到开发板上 |
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|
|||
 |
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|
|||
- 跳转启动例程 |
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|
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 |
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|
|||
#### 2.2.2 没有开发板，可以通过模拟器体验一下SDK |
|||
>ft_sdk/baremetal/example/aarch32/qemu_debug |
|||
- 编译例程qemu_debug |
|||
``` |
|||
$ make |
|||
``` |
|||
|
|||
 |
|||
|
|||
- 运行例程qemu_debug |
|||
``` |
|||
$ make run |
|||
``` |
|||
|
|||
 |
|||
|
|||
#### 2.2.3 新建Baremetal应用工程 |
|||
|
|||
- 复制例程hello_world |
|||
- 在工程目录下添加源文件 |
|||
- 通过'make menuconfig'修改配置 |
|||
 |
|||
|
|||
``` |
|||
Project Configuration --> 当前工程的私有配置 |
|||
Target Setting --> 配置目标硬件平台 |
|||
Building Option --> 配置编译开发环境 |
|||
Board Configuration --> 配置开发板组件 |
|||
Library Configuration --> 配置依赖库 |
|||
``` |
|||
- 通过'make info'观察构建信息 |
|||
``` |
|||
$make info --> 查看交叉编译器的信号，编译输出路径，SDK根目录等信息 |
|||
$make info-srcs --> 查看编译过程中用到的源文件 |
|||
$make info-incs --> 查看编译过程中引用的目录 |
|||
$make info-flags --> 查看编译过程中的flags |
|||
``` |
|||
- 通过'make'完成编译构建 |
|||
|
|||
## 3. Standalone源码结构 |
|||
``` |
|||
. |
|||
├── Kconfig --> 顶层配置选项定义 |
|||
├── LICENSE |
|||
├── README.en.md |
|||
├── README.md |
|||
├── baremetal |
|||
│ └── example --> 已经配置好的baremetal例程 |
|||
├── bsp --> 板级支持包 |
|||
│ ├── Kconfig |
|||
│ ├── arch --> 架构相关源码 armv7/a32/a64 |
|||
│ ├── bsp.mk |
|||
│ ├── common --> BSP 不同平台的共用源码 |
|||
│ └── drivers --> 各类驱动 |
|||
├── configs --> 各平台默认匹配文件 |
|||
│ ├── aarch32_defconfig |
|||
│ └── aarch64_defconfig |
|||
├── doc |
|||
│ ├── ChangeLog.md --> 版本变更日志 |
|||
│ ├── baremetal.dio |
|||
│ └── baremetal.png |
|||
├── export.sh --> SDK注册安装脚本 |
|||
├── lib |
|||
│ ├── Kconfig |
|||
│ ├── Kconfiglib |
|||
│ ├── lib.mk |
|||
│ ├── libc |
|||
│ └── nostdlib |
|||
├── make --> SDK共用Makefile |
|||
│ ├── build_baremetal.mk |
|||
│ ├── buildinfo.mk |
|||
│ ├── complier.mk |
|||
│ ├── ld |
|||
│ ├── ld.mk |
|||
│ ├── menuconfig.mk |
|||
│ ├── packsource.mk |
|||
│ └── preconfig.mk |
|||
├── scripts |
|||
│ ├── kill_qemu_instance.sh |
|||
│ └── mount2vxbox.sh |
|||
└── tools --> 必要的工具，编译器安装在这个路径下 |
|||
├── README.md |
|||
├── gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf |
|||
├── gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf.tar.xz |
|||
├── gcc-arm-none-eabi-10-2020-q4-major --> SDK注册过程中下载安装 |
|||
└── gcc-arm-none-eabi-10-2020-q4-major-x86_64-linux.tar.bz |
|||
``` |
|||
|
|||
## 4. 驱动描述 |
|||
|
|||
## 5. 硬件平台 |
|||
|
|||
## 6. 参考资源 |
|||
|
|||
- ARM Architecture Reference Manual |
|||
|
|||
- FT-2000／4 软件编程手册-V1.4 |
|||
|
|||
- Mastering the FreeRTOS Real Time Kernel-A Hands-On Tutorial Guide |
|||
|
|||
--- |
|||
|
|||
## 7. 贡献方法 |
|||
|
|||
请联系飞腾嵌入式软件部 |
|||
|
|||
huanghe@phytium.com.cn |
|||
|
|||
zhugengyu@phytium.com.cn |
|||
|
|||
--- |
|||
|
|||
## 8. 许可协议 |
|||
|
|||
Apache-2.0 |
|||
@ -1,13 +0,0 @@ |
|||
# Compiling all examples
|
|||
TOPTARGETS := all clean |
|||
|
|||
SUBDIRS := $(wildcard */.) |
|||
|
|||
$(TOPTARGETS): $(SUBDIRS) |
|||
@for i in $(SUBDIRS); do \
|
|||
echo -e "\033[44;37;1m +++ Compiling $$i...\033[0m"; \
|
|||
$(MAKE) -C $$i $(MAKECMDGOALS) > /dev/null || exit $$?; \
|
|||
echo -e "\033[44;37;1m +++ Compiled OK $$i...\033[0m"; \
|
|||
done |
|||
|
|||
.PHONY: $(TOPTARGETS) $(SUBDIRS) |
|||
@ -1,19 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
mainmenu "Phytium Baremetal Configuration" |
|||
|
|||
menu "Project Configuration" |
|||
menu "Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "ft2004_baremetal" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
@ -1,13 +0,0 @@ |
|||
export PROJECT_DIR ?= . |
|||
export DEF_KCONFIG = ft20004_aarch32_baremetal_defconfig |
|||
|
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
rebuild: |
|||
make clean |
|||
make |
|||
|
|||
boot: |
|||
make |
|||
@cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ |
|||
@ -1,52 +0,0 @@ |
|||
<!-- |
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-23 18:47:28 |
|||
* @LastEditTime: 2021-06-23 18:48:31 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
--> |
|||
|
|||
# host侧设置 |
|||
- 重启host侧tftp服务器 |
|||
``` |
|||
sudo service tftpd-hpa restart |
|||
``` |
|||
|
|||
# 开发板侧设置 |
|||
|
|||
## 使用go命令跳转 |
|||
- 关闭D-cache和I-cache |
|||
``` |
|||
icache off |
|||
dcache off |
|||
``` |
|||
|
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
go 0x80100000 |
|||
``` |
|||
|
|||
``` |
|||
tftpboot 80100000 ft2004_test_irq.bin |
|||
``` |
|||
|
|||
## 使用bootvx32命令跳转 |
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
``` |
|||
@ -1,30 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 08:06:52 |
|||
* @LastEditTime: 2021-06-29 13:26:51 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include <stdio.h> |
|||
|
|||
extern void CacheTest(); |
|||
extern void MMUTest(); |
|||
int main() |
|||
{ |
|||
printf("cache & mmu test on qemu!!\r\n"); |
|||
CacheTest(); |
|||
MMUTest(); |
|||
return 0; |
|||
} |
|||
|
|||
void AsmStub() |
|||
{ |
|||
printf("stub\r\n"); |
|||
} |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="cache_test" |
|||
# end of Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
# CONFIG_TARGET_F2000_4 is not set |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
CONFIG_TARGET_E2000=y |
|||
CONFIG_TARGET_BARE_METAL=y |
|||
# CONFIG_TARGET_FREE_RTOS is not set |
|||
# CONFIG_TARGET_RT_THREAD is not set |
|||
# CONFIG_TARGET_U_BOOT is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
# CONFIG_USE_USART is not set |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
CONFIG_USE_CACHE=y |
|||
CONFIG_USE_L3CACHE=y |
|||
CONFIG_USE_MMU=y |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,14 +0,0 @@ |
|||
#define CONFIG_TARGET_NAME "cache_test" |
|||
#define CONFIG_TARGET_ARMV8_AARCH32 1 |
|||
#define CONFIG_TARGET_E2000 1 |
|||
#define CONFIG_TARGET_BARE_METAL 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_COMPILER_NO_STD_STARUP 1 |
|||
#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_CACHE 1 |
|||
#define CONFIG_USE_L3CACHE 1 |
|||
#define CONFIG_USE_MMU 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="cache_test" |
|||
# end of Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
CONFIG_TARGET_BARE_METAL=y |
|||
# CONFIG_TARGET_FREE_RTOS is not set |
|||
# CONFIG_TARGET_RT_THREAD is not set |
|||
# CONFIG_TARGET_U_BOOT is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
# CONFIG_USE_USART is not set |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
CONFIG_USE_CACHE=y |
|||
CONFIG_USE_L3CACHE=y |
|||
CONFIG_USE_MMU=y |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,61 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 10:36:06 |
|||
* @LastEditTime: 2021-06-29 15:26:04 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include <stdio.h> |
|||
#include "cache.h" |
|||
#include "aarch32.h" |
|||
#include "ft_debug.h" |
|||
|
|||
#define DATA_LENGTH 128 |
|||
#define MAGIC_NUM1 0xA0A00505 |
|||
#define MAGIC_NUM2 0xB0B00606 |
|||
#define MAGIC_NUM3 0xC0C00707 |
|||
|
|||
static u32 Data[DATA_LENGTH] __attribute__((aligned(64))); |
|||
|
|||
void CacheTest() |
|||
{ |
|||
s32 i; |
|||
u32 reg; |
|||
|
|||
printf("case 1: cache write\r\n"); |
|||
|
|||
/* 1. enable cache, write to cache */ |
|||
reg = aarch32_sctrl_get(); |
|||
printf("sctrl : 0x%x \r\n", reg); |
|||
reg |= AARCH32_SCTRL_CACHE_BIT; |
|||
aarch32_sctrl_set(reg); |
|||
|
|||
for (i = 0; i < DATA_LENGTH; i++) |
|||
{ |
|||
Data[i] = MAGIC_NUM1; |
|||
} |
|||
|
|||
FtDumpHexWord(Data, DATA_LENGTH); |
|||
|
|||
/* 2. disable cahche, write to cache then discard */ |
|||
printf("case 2: cache invalidate\r\n"); |
|||
for (i = 0; i < DATA_LENGTH; i++) |
|||
{ |
|||
Data[i] = MAGIC_NUM2; |
|||
} |
|||
|
|||
reg = aarch32_sctrl_get(); |
|||
printf("sctrl : 0x%x \r\n", reg); |
|||
reg &= ~AARCH32_SCTRL_CACHE_BIT; |
|||
aarch32_sctrl_set(reg); |
|||
|
|||
DcacheOps(CACHE_INVALIDATE, (void *)Data, sizeof(Data)); |
|||
FtDumpHexWord(Data, DATA_LENGTH); |
|||
} |
|||
@ -1,20 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 10:36:56 |
|||
* @LastEditTime: 2021-06-29 10:43:36 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include <stdio.h> |
|||
|
|||
void MMUTest() |
|||
{ |
|||
|
|||
|
|||
} |
|||
@ -1,19 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
mainmenu "Phytium Baremetal Configuration" |
|||
|
|||
menu "Project Configuration" |
|||
menu "FT2000-4 AARCH32 Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "ft2004_baremetal" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
@ -1,12 +0,0 @@ |
|||
export PROJECT_DIR ?= . |
|||
|
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
rebuild: |
|||
make clean |
|||
make |
|||
|
|||
boot: |
|||
make |
|||
@cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ |
|||
@ -1,26 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 17:12:55 |
|||
* @LastEditTime: 2021-07-01 17:13:03 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "fsleep.h" |
|||
#include <stdio.h> |
|||
|
|||
int main(void) |
|||
{ |
|||
while (1) |
|||
{ |
|||
/* code */ |
|||
printf("hello world \r\n "); |
|||
fsleep_seconds(10); |
|||
} |
|||
} |
|||
@ -1,95 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,12 +0,0 @@ |
|||
#define CONFIG_TARGET_NAME "ft2004_baremetal" |
|||
#define CONFIG_TARGET_ARMV8_AARCH32 1 |
|||
#define CONFIG_TARGET_F2000_4 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_COMPILER_NO_STD_STARUP 1 |
|||
#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_USART 1 |
|||
#define CONFIG_ENABLE_Pl011_UART 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,19 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
mainmenu "Phytium Baremetal Configuration" |
|||
|
|||
menu "Project Configuration" |
|||
menu "Qemu AARCH32 Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "qemu_baremetal" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
@ -1,28 +0,0 @@ |
|||
export PROJECT_DIR ?= . |
|||
|
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
GDB ?= $(CONFIG_SDK_TOOL_PREFIX)gdb |
|||
QEMU_EMULATOR ?= qemu-system-arm |
|||
QEMU_MACHINE ?= vexpress-a9 |
|||
QEMU_MEMORY ?= 1024M |
|||
|
|||
.phony: rebuild run step quit attach |
|||
rebuild: |
|||
make clean |
|||
make |
|||
|
|||
run: |
|||
$(QEMU_EMULATOR) -machine $(QEMU_MACHINE) -m $(QEMU_MEMORY) \
|
|||
-serial stdio -kernel $(CONFIG_TARGET_NAME).elf |
|||
|
|||
step: |
|||
$(QEMU_EMULATOR) -machine $(QEMU_MACHINE) -m $(QEMU_MEMORY) \
|
|||
-serial stdio -kernel $(CONFIG_TARGET_NAME).elf -S -s |
|||
|
|||
quit: |
|||
$(SDK_ROOT)/scripts/kill_qemu_instance.sh |
|||
|
|||
attach: |
|||
$(GDB) $(CONFIG_TARGET_NAME).elf |
|||
@ -1,21 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 08:06:52 |
|||
* @LastEditTime: 2021-07-01 17:53:28 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include <stdio.h> |
|||
|
|||
int main() |
|||
{ |
|||
printf("hello qemu num <%d>!!\r\n", 123); |
|||
return 0; |
|||
} |
|||
@ -1,89 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# Qemu AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="qemu_baremetal" |
|||
# end of Qemu AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
# CONFIG_TARGET_F2000_4 is not set |
|||
CONFIG_TARGET_AARCH32_QEMU=y |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
# CONFIG_COMPILER_NO_STD_STARUP is not set |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
CONFIG_QEMU_AARCH32_RAM_LD=y |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
# CONFIG_USE_USART is not set |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,9 +0,0 @@ |
|||
#define CONFIG_TARGET_NAME "qemu_baremetal" |
|||
#define CONFIG_TARGET_ARMV8_AARCH32 1 |
|||
#define CONFIG_TARGET_AARCH32_QEMU 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_QEMU_AARCH32_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
@ -1,19 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
mainmenu "Phytium Baremetal Configuration" |
|||
|
|||
menu "Project Configuration" |
|||
menu "FT2000-4 AARCH32 Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "ft2004_baremetal" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
@ -1,12 +0,0 @@ |
|||
export PROJECT_DIR ?= . |
|||
|
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
rebuild: |
|||
make clean |
|||
make |
|||
|
|||
boot: |
|||
make |
|||
@cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ |
|||
@ -1,52 +0,0 @@ |
|||
<!-- |
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-23 18:47:28 |
|||
* @LastEditTime: 2021-06-23 18:48:31 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
--> |
|||
|
|||
# host侧设置 |
|||
- 重启host侧tftp服务器 |
|||
``` |
|||
sudo service tftpd-hpa restart |
|||
``` |
|||
|
|||
# 开发板侧设置 |
|||
|
|||
## 使用go命令跳转 |
|||
- 关闭D-cache和I-cache |
|||
``` |
|||
icache off |
|||
dcache off |
|||
``` |
|||
|
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
go 0x80100000 |
|||
``` |
|||
|
|||
``` |
|||
tftpboot 80100000 ft2004_test_irq.bin |
|||
``` |
|||
|
|||
## 使用bootvx32命令跳转 |
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
``` |
|||
@ -1,30 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 16:49:09 |
|||
* @LastEditTime: 2021-07-02 09:42:27 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include <stdio.h> |
|||
#include "generic_timer.h" |
|||
|
|||
extern void ArchTimerTest(); |
|||
int main() |
|||
{ |
|||
printf("timer test\r\n"); |
|||
ArchTimerTest(); |
|||
while (1) |
|||
{ |
|||
Aarch32Delay(1000); //wait for 1 second
|
|||
printf("loop tick\r\n"); |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,12 +0,0 @@ |
|||
#define CONFIG_TARGET_NAME "ft2004_baremetal" |
|||
#define CONFIG_TARGET_ARMV8_AARCH32 1 |
|||
#define CONFIG_TARGET_F2000_4 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_COMPILER_NO_STD_STARUP 1 |
|||
#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_USART 1 |
|||
#define CONFIG_ENABLE_Pl011_UART 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
@ -1,101 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
CONFIG_TARGET_BARE_METAL=y |
|||
# CONFIG_TARGET_FREE_RTOS is not set |
|||
# CONFIG_TARGET_RT_THREAD is not set |
|||
# CONFIG_TARGET_U_BOOT is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,55 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 15:45:48 |
|||
* @LastEditTime: 2021-07-01 15:47:10 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include <stdio.h> |
|||
#include "parameters.h" |
|||
#include "ft_types.h" |
|||
#include "generic_timer.h" |
|||
#include "gicv3.h" |
|||
#include "interrupt.h" |
|||
|
|||
const u32 tickRateHz = GENERIC_TIMER_CLK_FREQ * 2; // set as 2 sec pre tick
|
|||
const u32 irqPriority = 50; |
|||
const u32 irqID = 30; |
|||
|
|||
void TickHandler(s32 vector, void *param) |
|||
{ |
|||
printf("irq ticked\r\n"); |
|||
Aarch32TimerCompare(tickRateHz); |
|||
} |
|||
|
|||
u32 PlatformGetGicDistBase(void) |
|||
{ |
|||
return GICV3_BASEADDRESS; |
|||
} |
|||
|
|||
void ArchTimerTest() |
|||
{ |
|||
Aarch32TimerCompare(tickRateHz); |
|||
Aarch32TimerStart(); |
|||
Aarch32TimerInterruptEnable(); |
|||
|
|||
printf("timer init done\r\n"); |
|||
|
|||
ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); |
|||
InterruptInit(); |
|||
InterruptSetPriority(irqID, irqPriority); |
|||
InterruptInstall(irqID, TickHandler, NULL, "tick"); |
|||
|
|||
InterruptUmask(irqID); |
|||
|
|||
while (1) |
|||
{ |
|||
|
|||
} |
|||
} |
|||
@ -1,19 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
mainmenu "Phytium Baremetal Configuration" |
|||
|
|||
menu "Project Configuration" |
|||
menu "FT2000-4 AARCH32 Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "ft2004_baremetal" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
@ -1,11 +0,0 @@ |
|||
export PROJECT_DIR ?= . |
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
rebuild: |
|||
make clean |
|||
make |
|||
|
|||
boot: |
|||
make |
|||
@cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/tftboot/ |
|||
@ -1,52 +0,0 @@ |
|||
<!-- |
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-23 18:47:28 |
|||
* @LastEditTime: 2021-07-01 16:56:27 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
--> |
|||
|
|||
# host侧设置 |
|||
- 重启host侧tftp服务器 |
|||
``` |
|||
sudo service tftpd-hpa restart |
|||
``` |
|||
|
|||
# 开发板侧设置 |
|||
|
|||
## 使用go命令跳转 |
|||
- 关闭D-cache和I-cache |
|||
``` |
|||
icache off |
|||
dcache off |
|||
``` |
|||
|
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
go 0x80100000 |
|||
``` |
|||
|
|||
``` |
|||
tftpboot 80100000 ft2004_test_irq.bin |
|||
``` |
|||
|
|||
## 使用bootvx32命令跳转 |
|||
- 下载新版本到FT2000-4 |
|||
``` |
|||
setenv ipaddr 192.168.4.20 |
|||
setenv serverip 192.168.4.50 |
|||
setenv gatewayip 192.168.4.1 |
|||
tftpboot 80100000 ft2004_baremetal.bin |
|||
bootvx32 |
|||
``` |
|||
@ -1,31 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 16:21:17 |
|||
* @LastEditTime: 2021-07-01 16:23:03 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include <stdio.h> |
|||
|
|||
|
|||
extern void IrqInit(); |
|||
extern void Uart1TestIrq(void); |
|||
extern void Uart1Init(void); |
|||
int main() |
|||
{ |
|||
printf("irq test\r\n"); |
|||
IrqInit(); |
|||
Uart1Init(); |
|||
Uart1TestIrq(); |
|||
while (1) |
|||
{ |
|||
} |
|||
|
|||
return 0; |
|||
} |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,12 +0,0 @@ |
|||
#define CONFIG_TARGET_NAME "ft2004_baremetal" |
|||
#define CONFIG_TARGET_ARMV8_AARCH32 1 |
|||
#define CONFIG_TARGET_F2000_4 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_COMPILER_NO_STD_STARUP 1 |
|||
#define CONFIG_E2000_FT2004_AARCH32_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_USART 1 |
|||
#define CONFIG_ENABLE_Pl011_UART 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
@ -1,101 +0,0 @@ |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# FT2000-4 AARCH32 Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="ft2004_baremetal" |
|||
# end of FT2000-4 AARCH32 Baremetal Configuration |
|||
# end of Project Configuration |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
CONFIG_TARGET_ARMV8_AARCH32=y |
|||
# CONFIG_TARGET_ARMV8_AARCH64 is not set |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
CONFIG_TARGET_BARE_METAL=y |
|||
# CONFIG_TARGET_FREE_RTOS is not set |
|||
# CONFIG_TARGET_RT_THREAD is not set |
|||
# CONFIG_TARGET_U_BOOT is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
CONFIG_E2000_FT2004_AARCH32_RAM_LD=y |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_RAM_LD is not set |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
# CONFIG_USE_CACHE is not set |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
@ -1,81 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 16:12:35 |
|||
* @LastEditTime: 2021-07-01 17:10:43 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "parameters.h" |
|||
#include "pl011_uart.h" |
|||
#include "gicv3.h" |
|||
#include "interrupt.h" |
|||
|
|||
Pl011 pl011_obj; |
|||
|
|||
volatile u64 get_uart_rx_flg = 0; |
|||
volatile u8 set_irq_priority = 50; |
|||
|
|||
u32 PlatformGetGicDistBase(void) |
|||
{ |
|||
return GICV3_BASEADDRESS; |
|||
} |
|||
|
|||
static void UartIrqCallback(void *args, u32 event, u32 event_data) |
|||
{ |
|||
get_uart_rx_flg = 1; |
|||
Pl011IrqClearReciveTimeOut(&pl011_obj); |
|||
} |
|||
|
|||
static void UartIrqHandler(s32 vector, void *param) |
|||
{ |
|||
Pl011InterruptHandler(param); |
|||
} |
|||
|
|||
void Uart1Init(void) |
|||
{ |
|||
Pl011Config config = *Pl011LookupConfig(1); |
|||
printf("config addr: 0x%x \r\n", config.base_address); |
|||
Pl011CfgInitialize(&pl011_obj, &config); |
|||
Pl011SetHandler(&pl011_obj, UartIrqCallback, NULL); |
|||
InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); |
|||
InterruptInstall(pl011_obj.config.irq_num, UartIrqHandler, &pl011_obj, "uart1"); |
|||
InterruptUmask(pl011_obj.config.irq_num); |
|||
Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); |
|||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|||
} |
|||
|
|||
void IrqInit() |
|||
{ |
|||
/* interrupt init */ |
|||
ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); |
|||
InterruptInit(); |
|||
} |
|||
|
|||
void Uart1TestIrq(void) |
|||
{ |
|||
char Byte; |
|||
while (1) |
|||
{ |
|||
while (get_uart_rx_flg == 0) |
|||
{ |
|||
|
|||
} |
|||
|
|||
Byte = Pl011BlockReceive(&pl011_obj); |
|||
printf("-->recv %c\r\n", Byte); |
|||
Pl011BlockSend(&pl011_obj, &Byte, 1); |
|||
InterruptMask(pl011_obj.config.irq_num); |
|||
set_irq_priority++; |
|||
InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); |
|||
InterruptUmask(pl011_obj.config.irq_num); |
|||
get_uart_rx_flg = 0; |
|||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|||
} |
|||
} |
|||
@ -1,17 +0,0 @@ |
|||
# |
|||
# For a description of the syntax of this configuration file, |
|||
# see tools/kconfiglib/kconfig-language.txt. |
|||
# |
|||
|
|||
source "$(SDK_ROOT)/Kconfig" |
|||
|
|||
menu "Project Configuration" |
|||
menu "Baremetal Configuration" |
|||
|
|||
config TARGET_NAME |
|||
string "Build Target Name" |
|||
default "uart_irq_send" |
|||
help |
|||
Build Target name for the demo |
|||
endmenu |
|||
endmenu |
|||
@ -1,17 +0,0 @@ |
|||
|
|||
|
|||
|
|||
# specify src code dir
|
|||
export PROJECT_DIR ?= . |
|||
|
|||
export DEF_KCONFIG = ft2004_aarch64_baremetal_defconfig |
|||
|
|||
# prepare output dir and start make
|
|||
include $(SDK_ROOT)/make/build_baremetal.mk |
|||
|
|||
boot: |
|||
make clean |
|||
make |
|||
@cp ./$(CONFIG_TARGET_NAME).bin /mnt/d/project/tftp/ |
|||
|
|||
|
|||
@ -1,108 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-22 10:23:24 |
|||
* @LastEditTime: 2021-06-30 21:12:16 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "fsleep.h" |
|||
#include <stdio.h> |
|||
#include "parameters.h" |
|||
#include "gicv3.h" |
|||
#include "exception.h" |
|||
#include "trap.h" |
|||
#include "generic_timer.h" |
|||
#include "interrupt.h" |
|||
#include "ft_assert.h" |
|||
#include "stdio.h" |
|||
|
|||
extern void Uart1Init(void); |
|||
extern void Uart1TestIrq(void); |
|||
|
|||
void float_test() |
|||
{ |
|||
float a = 0; |
|||
float b = 0; |
|||
float c; |
|||
|
|||
/* trap an floating exception */ |
|||
c = 0.0 / 0.0; |
|||
|
|||
printf("a %f, b %f, c %f\n", a, b, c); |
|||
} |
|||
|
|||
void common_trap_handler(exception_frame *exc) |
|||
{ |
|||
if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) |
|||
{ |
|||
// printf("AARCH64_EXC_SYNC_SPX)\r\n");
|
|||
SerrHandle(exc); |
|||
} |
|||
|
|||
if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) |
|||
{ |
|||
// printf("AARCH64_EXC_IRQ_SPX)\r\n");
|
|||
IrqHandleException(exc); |
|||
} |
|||
return; |
|||
} |
|||
|
|||
static void irq_timer(void *param) |
|||
{ |
|||
printf("irq is under process \r\n"); |
|||
GenericTimerCompare(48000000 * 2); |
|||
} |
|||
|
|||
u32 PlatformGetGicDistBase(void) |
|||
{ |
|||
return GICV3_BASEADDRESS; |
|||
} |
|||
|
|||
void irq_test_init(void) |
|||
{ |
|||
/* interrupt init */ |
|||
ArmGicRedistAddressSet(0, GICV3_RD_BASEADDRESS + 0, 0); |
|||
InterruptInit(); |
|||
|
|||
ArmGicDumpType(0); |
|||
ArmGicDump(0); |
|||
|
|||
// GenericTimerCompare(48000000 * 2);
|
|||
// Aarch64TimerStart();
|
|||
// Aarch64TimerInterruptEnable();
|
|||
|
|||
// InterruptSetPriority(30, 0);
|
|||
// InterruptInstall(30, irq_timer, NULL, "tick");
|
|||
// InterruptUmask(30);
|
|||
} |
|||
|
|||
void vMainAssertCalled(const char *pcFileName, uint32_t ulLineNumber) |
|||
{ |
|||
printf("Assert Error is %s : %d \r\n", pcFileName, ulLineNumber); |
|||
for (;;) |
|||
; |
|||
} |
|||
|
|||
static void AssertCallback(const char *File, s32 Line) |
|||
{ |
|||
printf("Assert Error is %s : %d \r\n", File, Line); |
|||
} |
|||
|
|||
int main(void) |
|||
{ |
|||
FtAssertSetCb((FtAssertCallback)AssertCallback); |
|||
irq_test_init(); |
|||
float_test(); |
|||
Uart1Init(); |
|||
Uart1TestIrq(); |
|||
while (1) |
|||
{ |
|||
} |
|||
} |
|||
@ -1,97 +0,0 @@ |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
# CONFIG_TARGET_ARMV8_AARCH32 is not set |
|||
CONFIG_TARGET_ARMV8_AARCH64=y |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
CONFIG_COMPILER_NO_STD_STARUP=y |
|||
# CONFIG_USE_EXT_COMPILER is not set |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set |
|||
CONFIG_E2000_FT20004_AARCH64_RAM_LD=y |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
CONFIG_USE_CACHE=y |
|||
CONFIG_USE_L3CACHE=y |
|||
CONFIG_USE_MMU=y |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="uart_irq_send" |
|||
# end of Baremetal Configuration |
|||
# end of Project Configuration |
|||
@ -1,15 +0,0 @@ |
|||
#define CONFIG_TARGET_ARMV8_AARCH64 1 |
|||
#define CONFIG_TARGET_F2000_4 1 |
|||
#define CONFIG_ENVI_UBUNTU_20_04 1 |
|||
#define CONFIG_COMPILER_NO_STD_STARUP 1 |
|||
#define CONFIG_E2000_FT20004_AARCH64_RAM_LD 1 |
|||
#define CONFIG_LOG_ERROR 1 |
|||
#define CONFIG_USE_GIC 1 |
|||
#define CONFIG_EBABLE_GICV3 1 |
|||
#define CONFIG_USE_USART 1 |
|||
#define CONFIG_ENABLE_Pl011_UART 1 |
|||
#define CONFIG_USE_CACHE 1 |
|||
#define CONFIG_USE_L3CACHE 1 |
|||
#define CONFIG_USE_MMU 1 |
|||
#define CONFIG_USE_NOSTD_LIBC 1 |
|||
#define CONFIG_TARGET_NAME "uart_irq_send" |
|||
@ -1,104 +0,0 @@ |
|||
|
|||
# |
|||
# Build Target |
|||
# |
|||
# CONFIG_TARGET_ARMV8_AARCH32 is not set |
|||
CONFIG_TARGET_ARMV8_AARCH64=y |
|||
# CONFIG_TARGET_ARMV7 is not set |
|||
CONFIG_TARGET_F2000_4=y |
|||
# CONFIG_TARGET_AARCH32_QEMU is not set |
|||
# CONFIG_TARGET_AARCH64_QEMU is not set |
|||
# CONFIG_TARGET_E2000 is not set |
|||
CONFIG_TARGET_BARE_METAL=y |
|||
# CONFIG_TARGET_FREE_RTOS is not set |
|||
# CONFIG_TARGET_RT_THREAD is not set |
|||
# CONFIG_TARGET_U_BOOT is not set |
|||
# end of Build Target |
|||
|
|||
# |
|||
# General Setting |
|||
# |
|||
CONFIG_ENVI_UBUNTU_20_04=y |
|||
# CONFIG_ENVI_WINDOWS10_MINGW is not set |
|||
|
|||
# |
|||
# Cross-Compiler Setting |
|||
# |
|||
# CONFIG_COMPILER_NO_STD_STARUP is not set |
|||
CONFIG_USE_EXT_COMPILER=y |
|||
CONFIG_EXT_COMPILER_PREFIX="/home/carl/aarch64/gcc-arm-10.2-2020.11-x86_64-aarch64-none-elf" |
|||
# end of Cross-Compiler Setting |
|||
|
|||
# |
|||
# GNU linker |
|||
# |
|||
# CONFIG_E2000_FT2004_AARCH32_RAM_LD is not set |
|||
# CONFIG_E2000_FT2004_AARCH32_FLASH_LD is not set |
|||
CONFIG_E2000_FT20004_AARCH64_RAM_LD=y |
|||
# CONFIG_E2000_FT20004_AARCH64_FLASH_LD is not set |
|||
# CONFIG_QEMU_AARCH32_RAM_LD is not set |
|||
# end of GNU linker |
|||
# end of General Setting |
|||
|
|||
# |
|||
# Board Configuration |
|||
# |
|||
|
|||
# |
|||
# Common Configuration |
|||
# |
|||
# CONFIG_LOG_VERBOS is not set |
|||
# CONFIG_LOG_DEBUG is not set |
|||
# CONFIG_LOG_INFO is not set |
|||
# CONFIG_LOG_WARN is not set |
|||
CONFIG_LOG_ERROR=y |
|||
# end of Common Configuration |
|||
|
|||
# |
|||
# Components Configuration |
|||
# |
|||
# CONFIG_USE_SPI is not set |
|||
# CONFIG_USE_QSPI is not set |
|||
CONFIG_USE_GIC=y |
|||
|
|||
# |
|||
# Gic Configuration |
|||
# |
|||
CONFIG_EBABLE_GICV3=y |
|||
# end of Gic Configuration |
|||
|
|||
CONFIG_USE_USART=y |
|||
|
|||
# |
|||
# Usart Configuration |
|||
# |
|||
CONFIG_ENABLE_Pl011_UART=y |
|||
# end of Usart Configuration |
|||
# end of Components Configuration |
|||
|
|||
# |
|||
# Arch Configuration |
|||
# |
|||
CONFIG_USE_CACHE=y |
|||
CONFIG_USE_L3CACHE=y |
|||
CONFIG_USE_MMU=y |
|||
# end of Arch Configuration |
|||
# end of Board Configuration |
|||
|
|||
# |
|||
# Library Configuration |
|||
# |
|||
CONFIG_USE_NOSTD_LIBC=y |
|||
# CONFIG_USE_LIBC is not set |
|||
# end of Library Configuration |
|||
|
|||
# |
|||
# Project Configuration |
|||
# |
|||
|
|||
# |
|||
# Baremetal Configuration |
|||
# |
|||
CONFIG_TARGET_NAME="uart_irq_send" |
|||
# end of Baremetal Configuration |
|||
# end of Project Configuration |
|||
@ -1,63 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-22 10:23:24 |
|||
* @LastEditTime: 2021-07-01 18:03:51 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "pl011_uart.h" |
|||
#include "interrupt.h" |
|||
#include "gicv3_cpuif.h" |
|||
#include "interrupt.h" |
|||
#include "stdio.h" |
|||
#include "string.h" |
|||
|
|||
Pl011 pl011_obj; |
|||
|
|||
volatile u64 get_uart_rx_flg = 0; |
|||
volatile u8 set_irq_priority = 0; |
|||
u8 get_byte; |
|||
|
|||
static void FtFreeUartCallback(void *args, u32 event, u32 event_data) |
|||
{ |
|||
get_uart_rx_flg = 1; |
|||
// printf("%x %x \r\n", set_irq_priority, getRunningPriority());
|
|||
get_byte = Pl011BlockReceive(&pl011_obj); |
|||
Pl011IrqClearReciveTimeOut(&pl011_obj); |
|||
} |
|||
|
|||
static void FtFreertosUartIrq(s32 vector, void *param) |
|||
{ |
|||
Pl011InterruptHandler(param); |
|||
} |
|||
|
|||
void Uart1Init(void) |
|||
{ |
|||
Pl011CfgInitialize(&pl011_obj, Pl011LookupConfig(1)); |
|||
Pl011SetHandler(&pl011_obj, FtFreeUartCallback, NULL); |
|||
InterruptSetPriority(pl011_obj.config.irq_num, set_irq_priority); |
|||
InterruptInstall(pl011_obj.config.irq_num, FtFreertosUartIrq, &pl011_obj, "uart1"); |
|||
InterruptUmask(pl011_obj.config.irq_num); |
|||
Pl011SetOptions(&pl011_obj, FUART_OPTION_UARTEN | FUART_OPTION_RXEN | FUART_OPTION_TXEN | FUART_OPTION_FIFOEN); |
|||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|||
} |
|||
|
|||
void Uart1TestIrq(void) |
|||
{ |
|||
char temp_buffer[] = "0123456789abcdefghijklnmopqrstuvwxyz"; |
|||
while (1) |
|||
{ |
|||
while (get_uart_rx_flg == 0) |
|||
; |
|||
Pl011Send(&pl011_obj, temp_buffer, strlen(temp_buffer)); |
|||
get_uart_rx_flg = 0; |
|||
Pl011IrqEnableReciveTimeOut(&pl011_obj); |
|||
} |
|||
} |
|||
@ -1,7 +0,0 @@ |
|||
menu "Board Configuration" |
|||
|
|||
source "$(SDK_ROOT)/bsp/common/Kconfig" |
|||
source "$(SDK_ROOT)/bsp/drivers/Kconfig" |
|||
source "$(SDK_ROOT)/bsp/arch/Kconfig" |
|||
|
|||
endmenu |
|||
@ -1,27 +0,0 @@ |
|||
menu "Arch Configuration" |
|||
|
|||
config USE_CACHE |
|||
bool |
|||
prompt "Use Cache" |
|||
default n |
|||
help |
|||
Activate the MMU and TLB functions |
|||
|
|||
if USE_CACHE |
|||
config USE_L3CACHE |
|||
bool |
|||
prompt "Use external L3 Cache" |
|||
default n |
|||
help |
|||
Include L3 Cache and enable |
|||
|
|||
config USE_MMU |
|||
bool |
|||
prompt "Use MMU" |
|||
default n |
|||
help |
|||
Include platform mmu setting |
|||
endif |
|||
|
|||
endmenu |
|||
|
|||
@ -1,393 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-23 15:01:04 |
|||
* @LastEditTime: 2021-06-29 17:30:11 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_AARCH32_ASM_H |
|||
#define BSP_AARCH32_ASM_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
#define __ASM __asm |
|||
#define __STATIC_INLINE static inline |
|||
#define __STRINGIFY(x) #x |
|||
/* C语言实现MCR指令 */ |
|||
#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ |
|||
__ASM volatile("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ |
|||
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ |
|||
: \ |
|||
: "r"(src) \ |
|||
: "memory"); |
|||
|
|||
/* C语言实现MRC指令 */ |
|||
#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ |
|||
( \ |
|||
{ \ |
|||
u32 __dst; \ |
|||
__ASM volatile("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ |
|||
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " __STRINGIFY(opcode_2) \ |
|||
: "=r"(__dst)::"memory"); \ |
|||
__dst; \ |
|||
}) |
|||
|
|||
/* C语言实现MRRC指令 */ |
|||
#define __MRRC(coproc, opcode_1, dst_1, dst_2, CRm) ( \ |
|||
{ \ |
|||
__asm__ __volatile__( \ |
|||
"MRRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " "%0,%1," __STRINGIFY(c##CRm) \ |
|||
: "=r"(dst_1), "=r"(dst_2)); \ |
|||
}) |
|||
|
|||
/**
|
|||
* @name: aarch32_cntp_ctl_get |
|||
* @msg: Read the register that holds the timer value for the EL1 physical timer. |
|||
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntp_ctl_get(void) |
|||
{ |
|||
/* MRC p15(coproc) 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ |
|||
return __MRC(15, 0, 14, 2, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: aarch32_cntp_ctl_set |
|||
* @msg: Read the register that holds the timer value for the EL1 physical timer. |
|||
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_ctl_set(u32 regVal) |
|||
{ |
|||
/* MRC p15(coproc) regVal 0(opcode1) CR14(n) CR2(m) 1(opcode2) */ |
|||
__MCR(15, 0, regVal, 14, 2, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntfrq_get |
|||
* @msg: This register is provided so that software can discover the frequency of the system counter. |
|||
* @return {__STATIC_INLINEu32}: frequency of the system counter |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_cntfrq_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 0, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: aarch32_cntpct_get |
|||
* @msg: get the 64-bit physical count value |
|||
* @return {*} |
|||
* @param {__STATIC_INLINE u64} aarch32_cntpct_get |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u64 aarch32_cntpct_get() |
|||
{ |
|||
u64 cnt = 0; |
|||
u32 cnt_low = 0, cnt_high = 0; |
|||
__MRRC(15, 0, cnt_low, cnt_high, 14); |
|||
cnt = (u64)cnt_high << 32 | cnt_low; |
|||
return cnt; |
|||
} |
|||
|
|||
/**
|
|||
* @name: aarch32_cntp_tval_set |
|||
* @msg: write the register that control register for the EL1 physical timer. |
|||
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void aarch32_cntp_tval_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 2, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: aarch32_sctrl_get |
|||
* @msg: read the register that control system |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 aarch32_sctrl_get() |
|||
{ |
|||
return __MRC(15, 0, 1, 0, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: aarch32_sctrl_set |
|||
* @msg: read the register that control system |
|||
*/ |
|||
#define AARCH32_SCTRL_CACHE_BIT (1 << 2) /* 1: enable, 0: disable */ |
|||
__attribute__((always_inline)) __STATIC_INLINE void aarch32_sctrl_set(u32 RegVal) |
|||
{ |
|||
__MCR(15, 0, RegVal, 1, 0, 0); |
|||
} |
|||
|
|||
/**********************************************/ |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 __get_VBAR(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 0, 0); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void __set_VBAR(u32 vbar) |
|||
{ |
|||
__MCR(15, 0, vbar, 12, 0, 0); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen0_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 12, 6); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen0_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 6); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_igrpen1_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 12, 7); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_igrpen1_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 7); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_ctlr_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 12, 4); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_ctlr_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 4); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir0_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 8, 2); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_bpr_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 8, 3); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_bpr_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 8, 3); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_hppir1_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 2); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir0_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 8, 1); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_eoir1_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 12, 1); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_pmr_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 4, 6, 0); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_pmr_get(void) |
|||
{ |
|||
return __MRC(15, 0, 4, 6, 0); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_iar1_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 0); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE void sys_icc_sre_set(u32 value) |
|||
{ |
|||
__MCR(15, 0, value, 12, 12, 5); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_sre_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 12, 5); |
|||
} |
|||
|
|||
__attribute__((always_inline)) __STATIC_INLINE u32 sys_icc_rpr_get(void) |
|||
{ |
|||
return __MRC(15, 0, 12, 11, 3); |
|||
} |
|||
|
|||
/* Generic Timer registers */ |
|||
/**
|
|||
* @name: arm_aarch32_cntfrq_get |
|||
* @msg: This register is provided so that software can discover the frequency of the system counter. |
|||
* @return {__STATIC_INLINEu32}: frequency of the system counter |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntfrq_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 0, 0); |
|||
} |
|||
|
|||
/* arm_aarch32_cnttimer_set */ |
|||
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnttimer_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 2, 2); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cnthv_tval_get |
|||
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. |
|||
* @return {__STATIC_INLINEu32}: EL2 virtual timer Cnt. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_tval_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 3, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cnthv_ctl_set |
|||
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer. |
|||
* @in param {u32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. |
|||
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. |
|||
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. rea-only |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_ctl_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 3, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cnthv_ctl_get |
|||
* @msg: Provides AArch32 access to the control register for the EL2 virtual timer. |
|||
* @return {__STATIC_INLINEu32}: RegValue;ENABLE: bit [0] 0 Timer disabled,1 Timer enabled. |
|||
* IMASK,bit [1]: 0 Timer interrupt is not masked by the IMASK bit. 1 Timer interrupt is masked by the IMASK bit. |
|||
* ISTATUS, bit [2]: 0 Timer condition is not met. 1 Timer condition is met. read-only |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cnthv_ctl_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 3, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cnthv_tval_set |
|||
* @msg: Provides AArch32 access to the timer value for the EL2 virtual timer. |
|||
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL2 virtual timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cnthv_tval_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 3, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntvct_get |
|||
* @msg: Read the register that holds the 64-bit virtual count value. The virtual count value is equal to the physical count value visible in CNTPCT minus the virtual offset visible in CNTVOFF. |
|||
* @return {__STATIC_INLINEu64}Bits [63:0] Virtual count value. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntvct_get(void) |
|||
{ |
|||
/* "r0" --- low,
|
|||
"r1" --- hi |
|||
*/ |
|||
u32 low; |
|||
u32 hi; |
|||
__asm__ volatile( |
|||
".word 0xec510f1e \n" /* mrrc p15, 1, r0, r1, c14 */ |
|||
"mov %0, r0 \n" |
|||
"mov %1, r1 \n" |
|||
: "=&r"(low), "=&r"(hi)); |
|||
return (((u64)hi) << 32) | low; |
|||
} |
|||
|
|||
/* physical */ |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntp_tval_get |
|||
* @msg: Read the register that holds the timer value for the EL1 physical timer. |
|||
* @return {__STATIC_INLINEu32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_tval_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 2, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntp_tval_set |
|||
* @msg: write the register that control register for the EL1 physical timer. |
|||
* @in param {u32}: TimerValue, bits [31:0] The TimerValue view of the EL1 physical timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_tval_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 2, 0); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntp_ctl_set |
|||
* @msg: write the register that control register for the EL1 physical timer. |
|||
* @in param {u32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE void arm_aarch32_cntp_ctl_set(u32 RegValue) |
|||
{ |
|||
__MCR(15, 0, RegValue, 14, 2, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntp_ctl_get |
|||
* @msg: Read the register that control register for the EL1 physical timer. |
|||
* @return {__STATIC_INLINEu32}: ENABLE, bit[0] Enables the timer ; IMASK, bit [1] Timer interrupt mask bit; ISTATUS, bit [2] The status of the timer. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u32 arm_aarch32_cntp_ctl_get(void) |
|||
{ |
|||
return __MRC(15, 0, 14, 2, 1); |
|||
} |
|||
|
|||
/**
|
|||
* @name: arm_aarch32_cntpct_get |
|||
* @msg: Read the register that holds the 64-bit physical count value. |
|||
* @return {__STATIC_INLINEu64} CompareValue, bits [63:0] Physical count value. |
|||
*/ |
|||
__attribute__((always_inline)) __STATIC_INLINE u64 arm_aarch32_cntpct_get(void) |
|||
{ |
|||
/* "r0" --- low,
|
|||
"r1" --- hi |
|||
*/ |
|||
u32 low; |
|||
u32 hi; |
|||
__asm__ volatile( |
|||
|
|||
".word 0xec510f0e \n" /* mrrc p15, 0, r0, r1, c14 */ |
|||
"mov %0, r0 \n" |
|||
"mov %1, r1 \n" |
|||
: "=&r"(low), "=&r"(hi)); |
|||
return (((u64)hi) << 32) | low; |
|||
} |
|||
|
|||
#define IRQ_DISABLE() \ |
|||
__asm volatile("CPSID i" :: \ |
|||
: "memory"); \ |
|||
__asm volatile("DSB"); \ |
|||
__asm volatile("ISB"); |
|||
|
|||
#define IRQ_ENABLE() \ |
|||
__asm volatile("CPSIE i" :: \ |
|||
: "memory"); \ |
|||
__asm volatile("DSB"); \ |
|||
__asm volatile("ISB"); |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,176 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 08:52:17 |
|||
* @LastEditTime: 2021-07-01 16:52:16 |
|||
* @Description: This files is for |
|||
* |
|||
* clean: 将cache中尚未写入到主存储器中的数据回写到主存储器中 |
|||
* flush/invalidate: 将cache中的invalid标志位设置为1/0，使本cache中的内容无效 |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "ft_types.h" |
|||
#include "cache.h" |
|||
|
|||
/* FLUSH L3 CASHE */ |
|||
#ifdef CONFIG_USE_L3CACHE |
|||
#define HNF_BASE (unsigned long)(0x3A200000) |
|||
#define HNF_COUNT 0x8 |
|||
#define HNF_PSTATE_REQ (HNF_BASE + 0x10) |
|||
#define HNF_PSTATE_STAT (HNF_BASE + 0x18) |
|||
#define HNF_PSTATE_OFF 0x0 |
|||
#define HNF_PSTATE_SFONLY 0x1 |
|||
#define HNF_PSTATE_HALF 0x2 |
|||
#define HNF_PSTATE_FULL 0x3 |
|||
#define HNF_STRIDE 0x10000 |
|||
#endif |
|||
|
|||
int AsmFlushL3Dcache(void) |
|||
{ |
|||
|
|||
#ifdef CONFIG_USE_L3CACHE |
|||
int i, pstate; |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); |
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
{ |
|||
do |
|||
{ |
|||
pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); |
|||
} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
|||
} |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); |
|||
|
|||
#endif |
|||
return 0; |
|||
} |
|||
|
|||
int AsmInvaliDateL3dcache(void) |
|||
{ |
|||
#ifdef CONFIG_USE_L3CACHE |
|||
int i, pstate; |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
{ |
|||
do |
|||
{ |
|||
pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); |
|||
} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
|||
} |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); |
|||
#endif |
|||
return 0; |
|||
} |
|||
|
|||
static inline u32 GetIcacheLineSize(void) |
|||
{ |
|||
u32 ctr; |
|||
asm volatile("mrc p15, 0, %0, c0, c0, 1" |
|||
: "=r"(ctr)); |
|||
return 4 << (ctr & 0xF); |
|||
} |
|||
|
|||
static inline u32 GetDcacheLineSize(void) |
|||
{ |
|||
u32 ctr; |
|||
asm volatile("mrc p15, 0, %0, c0, c0, 1" |
|||
: "=r"(ctr)); |
|||
return 4 << ((ctr >> 16) & 0xF); |
|||
} |
|||
|
|||
void IcacheInvalidate(void *addr, int size) |
|||
{ |
|||
u32 line_size = GetIcacheLineSize(); |
|||
u32 start_addr = (u32)addr; |
|||
u32 end_addr = (u32)addr + size + line_size - 1; |
|||
|
|||
asm volatile("dmb" :: |
|||
: "memory"); |
|||
start_addr &= ~(line_size - 1); |
|||
end_addr &= ~(line_size - 1); |
|||
while (start_addr < end_addr) |
|||
{ |
|||
asm volatile("mcr p15, 0, %0, c7, c5, 1" ::"r"(start_addr)); /* icimvau */ |
|||
start_addr += line_size; |
|||
} |
|||
asm volatile("dsb\n\tisb" :: |
|||
: "memory"); |
|||
} |
|||
|
|||
void DcacheInvalidate(void *addr, int size) |
|||
{ |
|||
u32 line_size = GetDcacheLineSize(); |
|||
u32 start_addr = (u32)addr; |
|||
u32 end_addr = (u32)addr + size + line_size - 1; |
|||
|
|||
asm volatile("dmb" :: |
|||
: "memory"); |
|||
start_addr &= ~(line_size - 1); |
|||
end_addr &= ~(line_size - 1); |
|||
while (start_addr < end_addr) |
|||
{ |
|||
asm volatile("mcr p15, 0, %0, c7, c6, 1" ::"r"(start_addr)); /* dcimvac */ |
|||
start_addr += line_size; |
|||
} |
|||
asm volatile("dsb" :: |
|||
: "memory"); |
|||
|
|||
AsmInvaliDateL3dcache(); |
|||
} |
|||
|
|||
void DcacheClean(void *addr, int size) |
|||
{ |
|||
u32 line_size = GetDcacheLineSize(); |
|||
u32 start_addr = (u32)addr; |
|||
u32 end_addr = (u32)addr + size + line_size - 1; |
|||
|
|||
asm volatile("dmb" :: |
|||
: "memory"); |
|||
start_addr &= ~(line_size - 1); |
|||
end_addr &= ~(line_size - 1); |
|||
while (start_addr < end_addr) |
|||
{ |
|||
asm volatile("mcr p15, 0, %0, c7, c10, 1" ::"r"(start_addr)); /* dccmvac */ |
|||
start_addr += line_size; |
|||
} |
|||
asm volatile("dsb" :: |
|||
: "memory"); |
|||
AsmFlushL3Dcache(); |
|||
} |
|||
|
|||
void IcacheOps(int ops, void *addr, int size) |
|||
{ |
|||
if (ops == CACHE_INVALIDATE) |
|||
IcacheInvalidate(addr, size); |
|||
} |
|||
|
|||
void DcacheOps(int ops, void *addr, int size) |
|||
{ |
|||
if (ops == CACHE_CLEAN) |
|||
DcacheClean(addr, size); |
|||
else if (ops == CACHE_INVALIDATE) |
|||
DcacheInvalidate(addr, size); |
|||
} |
|||
|
|||
int GetCpuIcacheStatus(void) |
|||
{ |
|||
return 0; |
|||
} |
|||
|
|||
int GetCpuDcacheStatus(void) |
|||
{ |
|||
return 0; |
|||
} |
|||
@ -1,32 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 08:59:15 |
|||
* @LastEditTime: 2021-06-29 11:13:18 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_AARCH32_CACHE_H |
|||
#define BSP_ARCH_AARCH32_CACHE_H |
|||
|
|||
typedef enum |
|||
{ |
|||
CACHE_CLEAN = 0x01, |
|||
CACHE_INVALIDATE = 0x02, |
|||
}cache_op; |
|||
|
|||
// void IcacheInvalidate(void *addr, int size);
|
|||
// void DcacheInvalidate(void *addr, int size);
|
|||
// void DcacheClean(void *addr, int size);
|
|||
void IcacheOps(int ops, void *addr, int size); |
|||
void DcacheOps(int ops, void *addr, int size); |
|||
int GetCpuIcacheStatus(void); |
|||
int GetCpuDcacheStatus(void); |
|||
|
|||
#endif |
|||
@ -1,41 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 14:51:38 |
|||
* @LastEditTime: 2021-06-22 15:23:59 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_CP15 |
|||
#define BSP_ARCH_ARMV8_AARCH32_CP15 |
|||
|
|||
#define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" ) |
|||
#define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" ) |
|||
#define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : "=r" (Rt) : : "memory" ) |
|||
#define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm : : "r" (Rt) : "memory" ) |
|||
|
|||
unsigned long cpu_get_smp_id(void); |
|||
void cpu_mmu_disable(void); |
|||
void cpu_mmu_enable(void); |
|||
void cpu_tlb_set(volatile unsigned long *); |
|||
void cpu_dcache_clean_flush(void); |
|||
void cpu_icache_flush(void); |
|||
void cpu_vector_set_base(unsigned int addr); |
|||
|
|||
void cpu_dcache_disable(); |
|||
void cpu_icache_disable(); |
|||
void cpu_icache_enable(); |
|||
void cpu_dcache_enable(); |
|||
|
|||
s32 cp15_get_cpu_id(); |
|||
void cp15_set_vector_base(unsigned int addr); |
|||
s32 DisableInterrupt(); |
|||
void EnableInterrupt(s32 level); |
|||
|
|||
#endif /* BSP_ARCH_ARMV8_AARCH32_CP15 */ |
|||
@ -1,20 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-25 14:42:54 |
|||
* @LastEditTime: 2021-06-25 14:43:28 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_EXCEPTION_H |
|||
#define BSP_ARCH_ARMV8_AARCH32_EXCEPTION_H |
|||
|
|||
|
|||
|
|||
#endif //!
|
|||
@ -1,35 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-07-01 18:40:52 |
|||
* @LastEditTime: 2021-07-01 18:41:47 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "fsleep.h" |
|||
#include "generic_timer.h" |
|||
#include "parameters.h" |
|||
#include "ft_types.h" |
|||
#include <stdio.h> |
|||
|
|||
u32 fsleep_seconds(u32 seconds) |
|||
{ |
|||
u64 end_time; |
|||
u64 cur_time; |
|||
Aarch32TimerStart(); |
|||
cur_time = Aarch32TimerRead(); |
|||
end_time = cur_time + ((u64)seconds * Aarch32TimerFrequecy()); |
|||
printf("%d \r\n", Aarch32TimerFrequecy()); |
|||
do |
|||
{ |
|||
cur_time = Aarch32TimerRead(); |
|||
} while (cur_time < end_time); |
|||
|
|||
return 0; |
|||
} |
|||
@ -1,22 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2020 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-05-28 08:48:40 |
|||
* @LastEditTime: 2021-05-28 09:28:55 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef _BSP_ARCH_ARMV8_FSLEEP_H |
|||
#define _BSP_ARCH_ARMV8_FSLEEP_H |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
u32 fsleep_seconds(u32 seconds); |
|||
|
|||
#endif // !
|
|||
@ -1,12 +0,0 @@ |
|||
.section .text, "ax" |
|||
|
|||
.globl DisableInterrupt |
|||
DisableInterrupt: |
|||
mrs r0, cpsr |
|||
cpsid i |
|||
bx lr |
|||
|
|||
.globl EnableInterrupt |
|||
EnableInterrupt: |
|||
msr cpsr, r0 |
|||
bx lr |
|||
@ -1,141 +0,0 @@ |
|||
.globl cpu_get_smp_id |
|||
cpu_get_smp_id: |
|||
mrc p15, #0, r0, c0, c0, #5 |
|||
bx lr |
|||
|
|||
.globl cpu_mmu_disable |
|||
cpu_mmu_disable: |
|||
mcr p15, #0, r0, c8, c7, #0 @ invalidate tlb |
|||
mrc p15, #0, r0, c1, c0, #0 |
|||
bic r0, r0, #1 |
|||
mcr p15, #0, r0, c1, c0, #0 @ clear mmu bit |
|||
dsb |
|||
bx lr |
|||
|
|||
.globl cpu_mmu_enable |
|||
cpu_mmu_enable: |
|||
mrc p15, #0, r0, c1, c0, #0 |
|||
orr r0, r0, #0x001 |
|||
mcr p15, #0, r0, c1, c0, #0 @ set mmu enable bit |
|||
dsb |
|||
bx lr |
|||
|
|||
.globl cpu_tlb_set |
|||
cpu_tlb_set: |
|||
mcr p15, #0, r0, c2, c0, #0 |
|||
dmb |
|||
bx lr |
|||
|
|||
_FLD_MAX_WAY: |
|||
.word 0x3ff |
|||
_FLD_MAX_IDX: |
|||
.word 0x7fff |
|||
|
|||
.globl cpu_dcache_clean_flush |
|||
cpu_dcache_clean_flush: |
|||
push {r4-r11} |
|||
dmb |
|||
mrc p15, #1, r0, c0, c0, #1 @ read clid register |
|||
ands r3, r0, #0x7000000 @ get level of coherency |
|||
mov r3, r3, lsr #23 |
|||
beq finished |
|||
mov r10, #0 |
|||
loop1: |
|||
add r2, r10, r10, lsr #1 |
|||
mov r1, r0, lsr r2 |
|||
and r1, r1, #7 |
|||
cmp r1, #2 |
|||
blt skip |
|||
mcr p15, #2, r10, c0, c0, #0 |
|||
isb |
|||
mrc p15, #1, r1, c0, c0, #0 |
|||
and r2, r1, #7 |
|||
add r2, r2, #4 |
|||
ldr r4, _FLD_MAX_WAY |
|||
ands r4, r4, r1, lsr #3 |
|||
clz r5, r4 |
|||
ldr r7, _FLD_MAX_IDX |
|||
ands r7, r7, r1, lsr #13 |
|||
loop2: |
|||
mov r9, r4 |
|||
loop3: |
|||
orr r11, r10, r9, lsl r5 |
|||
orr r11, r11, r7, lsl r2 |
|||
mcr p15, #0, r11, c7, c14, #2 |
|||
subs r9, r9, #1 |
|||
bge loop3 |
|||
subs r7, r7, #1 |
|||
bge loop2 |
|||
skip: |
|||
add r10, r10, #2 |
|||
cmp r3, r10 |
|||
bgt loop1 |
|||
|
|||
finished: |
|||
dsb |
|||
isb |
|||
pop {r4-r11} |
|||
bx lr |
|||
|
|||
.globl cpu_icache_flush |
|||
cpu_icache_flush: |
|||
mov r0, #0 |
|||
mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate |
|||
dsb |
|||
isb |
|||
bx lr |
|||
|
|||
.globl cpu_vector_set_base |
|||
cpu_vector_set_base: |
|||
/* clear SCTRL.V to customize the vector address */ |
|||
mrc p15, #0, r1, c1, c0, #0 |
|||
bic r1, #(1 << 13) |
|||
mcr p15, #0, r1, c1, c0, #0 |
|||
/* set up the vector address */ |
|||
mcr p15, #0, r0, c12, c0, #0 |
|||
dsb |
|||
bx lr |
|||
|
|||
.globl cpu_dcache_disable |
|||
cpu_dcache_disable: |
|||
push {r4-r11, lr} |
|||
bl cpu_dcache_clean_flush |
|||
mrc p15, #0, r0, c1, c0, #0 // Read SCTLR. |
|||
bic r0, r0, #(0x1 << 2) // Disable D Cache. |
|||
mcr p15, #0, r0, c1, c0, #0 // Write SCTLR. |
|||
pop {r4-r11, lr} |
|||
bx lr |
|||
|
|||
.globl cpu_icache_disable |
|||
cpu_icache_disable: |
|||
mrc p15, #0, r0, c1, c0, #0 |
|||
bic r0, r0, #0x00001000 |
|||
mcr p15, #0, r0, c1, c0, #0 |
|||
bx lr |
|||
|
|||
.globl cpu_icache_enable |
|||
cpu_icache_enable: |
|||
mrc p15, #0, r0, c1, c0, #0 |
|||
orr r0, r0, #0x00001000 |
|||
mcr p15, #0, r0, c1, c0, #0 |
|||
bx lr |
|||
|
|||
.globl cpu_dcache_enable |
|||
cpu_dcache_enable: |
|||
mrc p15, #0, r0, c1, c0, #0 |
|||
orr r0, r0, #0x00000004 |
|||
mcr p15, #0, r0, c1, c0, #0 |
|||
bx lr |
|||
|
|||
.globl cp15_get_cpu_id |
|||
cp15_get_cpu_id: |
|||
mrc p15, #0, r0, c0, c0, #5 @ read multiprocessor affinity register |
|||
ldr r1, =0xFFFF03 @ Affinity mask off, leaving CPU ID field, [0:1]CPU ID, [8:15]Cluster ID Aff1, [16:23]Cluster ID Aff2 |
|||
and r0, r0, r1 |
|||
bx lr |
|||
|
|||
.globl cp15_set_vector_base |
|||
cp15_set_vector_base: |
|||
mcr p15, #0, r0, c12, c0, #0 |
|||
dsb |
|||
bx lr |
|||
@ -1,7 +0,0 @@ |
|||
.file "crt0.S" |
|||
.align 2 |
|||
.text |
|||
.globl c_startup |
|||
c_startup: |
|||
bl main /* continue running in case the main function */ |
|||
b Abort_Exception /* indicate an error, never execute when main contains infinite loop */ |
|||
@ -1,235 +0,0 @@ |
|||
#include "sdkconfig.h" |
|||
|
|||
.equ MODE_FIQ, 0x11 |
|||
.equ MODE_IRQ, 0x12 |
|||
.equ MODE_SVC, 0x13 |
|||
|
|||
.section .text /* The code segment, RD, program’s executable code */ |
|||
/******************************************************************************* |
|||
* |
|||
* sysInit - start after boot |
|||
* |
|||
* This routine is the system start-up entry point for VxWorks in RAM, the |
|||
* first code executed after booting. It disables interrupts, sets up |
|||
* the stack, and jumps to the C routine usrInit() in usrConfig.c. |
|||
* |
|||
* The initial stack is set to grow down from the address of sysInit(). This |
|||
* stack is used only by usrInit() and is never used again. Memory for the |
|||
* stack must be accounted for when determining the system load address. |
|||
* |
|||
* NOTE: This routine should not be called by the user. |
|||
* |
|||
* RETURNS: N/A |
|||
* |
|||
* void sysInit (UINT32 startType) /@ THIS IS NOT A CALLABLE ROUTINE @/ |
|||
* |
|||
*/ |
|||
#include "sdkconfig.h" |
|||
|
|||
/* Qemu no need to switch from aarch64 to aarch32 */ |
|||
.section .Startup_Aarch32, "a" |
|||
.global Startup_Aarch32 |
|||
Startup_Aarch32: |
|||
#ifndef CONFIG_TARGET_AARCH32_QEMU |
|||
.long 0xd5384240 /* mrs x0, currentel */ |
|||
.long 0xd342fc00 /* lsr x0, x0, #2 */ |
|||
.long 0x92400400 /* and x0, x0, #0x3 */ |
|||
.long 0xf1000c1f /* cmp x0, #0x3 */ |
|||
.long 0x540003a1 /* b.ne 1d0080c4 <el2_mode> */ |
|||
|
|||
el3_mode: |
|||
.long 0xd53ecca0 /* mrs x0, s3_6_c12_c12_5 - ICC_SRE_EL3 */ |
|||
.long 0xb2400c00 /* orr x0, x0, #0xf */ |
|||
.long 0xd51ecca0 /* msr s3_6_c12_c12_5, x0 */ |
|||
.long 0xd5033fdf /* isb */ |
|||
.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ |
|||
.long 0xb2400c00 /* orr x0, x0, #0xf */ |
|||
.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ |
|||
.long 0xd5033fdf /* isb */ |
|||
.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ |
|||
.long 0xb2400000 /* orr x0, x0, #0x1 */ |
|||
.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ |
|||
.long 0xd5033fdf /* isb */ |
|||
|
|||
.long 0xd2803620 /* mov x0, #0x1b1 */ |
|||
.long 0xd51e1100 /* msr scr_el3, x0 */ |
|||
.long 0xd2867fe0 /* mov x0, #0x33ff */ |
|||
.long 0xd51c1140 /* msr cptr_el2, x0 */ |
|||
.long 0xd2810000 /* mov x0, #0x800 */ |
|||
.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ |
|||
.long 0xd5181000 /* msr sctlr_el1, x0 */ |
|||
.long 0x910003e0 /* mov x0, sp */ |
|||
.long 0xd51c4100 /* msr sp_el1, x0 */ |
|||
.long 0xd53ec000 /* mrs x0, vbar_el3 */ |
|||
.long 0xd518c000 /* msr vbar_el1, x0 */ |
|||
.long 0xd2803a60 /* mov x0, #0x1d3 */ |
|||
.long 0xd51e4000 /* msr spsr_el3, x0 */ |
|||
.long 0x10000500 /* adr x0, 1d008158 <el1_mode> */ |
|||
.long 0xd51e4020 /* msr elr_el3, x0 */ |
|||
.long 0xd69f03e0 /* eret */ |
|||
|
|||
el2_mode: |
|||
.long 0xd53cc9a0 /* mrs x0, s3_4_c12_c9_5 - ICC_SRE_EL2 */ |
|||
.long 0xb2400c00 /* orr x0, x0, #0xf */ |
|||
.long 0xd51cc9a0 /* msr s3_4_c12_c9_5, x0 */ |
|||
.long 0xd5033fdf /* isb */ |
|||
.long 0xd538cca0 /* mrs x0, s3_0_c12_c12_5 - ICC_SRE_EL1 */ |
|||
.long 0xb2400000 /* orr x0, x0, #0x1 */ |
|||
.long 0xd518cca0 /* msr s3_0_c12_c12_5, x0 */ |
|||
.long 0xd5033fdf /* isb */ |
|||
.long 0xd53ce100 /* mrs x0, cnthctl_el2 */ |
|||
.long 0xb2400400 /* orr x0, x0, #0x3 */ |
|||
.long 0xd51ce100 /* msr cnthctl_el2, x0 */ |
|||
.long 0xd51ce07f /* msr cntvoff_el2, xzr */ |
|||
.long 0xd5380000 /* mrs x0, midr_el1 */ |
|||
.long 0xd53800a1 /* mrs x1, mpidr_el1 */ |
|||
.long 0xd51c0000 /* msr vpidr_el2, x0 */ |
|||
.long 0xd51c00a1 /* msr vmpidr_el2, x1 */ |
|||
.long 0xd2867fe0 /* mov x0, #0x33ff */ |
|||
.long 0xd51c1140 /* msr cptr_el2, x0 */ |
|||
.long 0xd51c117f /* msr hstr_el2, xzr */ |
|||
.long 0xd2a00600 /* mov x0, #0x300000 */ |
|||
.long 0xd5181040 /* msr cpacr_el1, x0 */ |
|||
.long 0xd2800000 /* mov x0, #0x0 */ |
|||
.long 0xb2630000 /* orr x0, x0, #0x20000000 */ |
|||
.long 0xd51c1100 /* msr hcr_el2, x0 */ |
|||
.long 0xd53c1100 /* mrs x0, hcr_el2 */ |
|||
.long 0xd2810000 /* mov x0, #0x800 */ |
|||
.long 0xf2a61a00 /* movk x0, #0x30d0, lsl #16 */ |
|||
.long 0xd5181000 /* msr sctlr_el1, x0 */ |
|||
.long 0x910003e0 /* mov x0, sp */ |
|||
.long 0xd51c4100 /* msr sp_el1, x0 */ |
|||
.long 0xd53cc000 /* mrs x0, vbar_el2 */ |
|||
.long 0xd518c000 /* msr vbar_el1, x0 */ |
|||
.long 0xd2803a60 /* mov x0, #0x1d3 */ |
|||
.long 0xd51c4000 /* msr spsr_el2, x0 */ |
|||
.long 0x10000060 /* adr x0, 1d008158 <el1_mode> */ |
|||
.long 0xd51c4020 /* msr elr_el2, x0 */ |
|||
.long 0xd69f03e0 /* eret */ |
|||
el1_mode: |
|||
#endif |
|||
|
|||
.global Reset_Handler |
|||
Reset_Handler: |
|||
cpsid i /* Mask interrupts */ |
|||
|
|||
/* set VBAR to the system_vectors address in linker script */ |
|||
ldr r0, =system_vectors |
|||
mcr p15, 0, r0, c12, c0, 0 |
|||
|
|||
/* from ARMv8 */ |
|||
/* Check for HYP mode */ |
|||
mrs r0, cpsr_all |
|||
and r0, r0, #0x1F |
|||
mov r8, #0x1A |
|||
cmp r0, r8 |
|||
beq overHyped |
|||
b continue |
|||
|
|||
overHyped: /* Get out of HYP mode */ |
|||
adr r1, continue |
|||
msr ELR_hyp, r1 |
|||
mrs r1, cpsr_all |
|||
and r1, r1, #0x1f ;@ CPSR_MODE_MASK |
|||
orr r1, r1, #0x13 ;@ CPSR_MODE_SUPERVISOR |
|||
msr SPSR_hyp, r1 |
|||
eret |
|||
|
|||
continue: |
|||
cps MODE_SVC |
|||
|
|||
disable_cache_mmu: |
|||
@ Disable MMU |
|||
MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data |
|||
BIC r1, r1, #0x1 |
|||
MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data |
|||
@ Disable L1 Caches |
|||
MRC p15, 0, r1, c1, c0, 0 @ Read Control Register configuration data |
|||
BIC r1, r1, #(0x1 << 12) @ Disable I Cache |
|||
BIC r1, r1, #(0x1 << 2) @ Disable D Cache |
|||
MCR p15, 0, r1, c1, c0, 0 @ Write Control Register configuration data |
|||
|
|||
/* disable the data alignment check */ |
|||
mrc p15, 0, r1, c1, c0, 0 |
|||
bic r1, #(1<<1) |
|||
mcr p15, 0, r1, c1, c0, 0 |
|||
|
|||
/* FIQ stack */ |
|||
/* Current Program Status Register, |
|||
change cpsr without affacting the |
|||
condition flags */ |
|||
msr cpsr_c, MODE_FIQ /* switch the processor to FIQ mode */ |
|||
ldr r1, =_fiq_stack_start /* load start address into R1 */ |
|||
ldr sp, =_fiq_stack_end /* load the end address of the FIQ stack into SP */ |
|||
movw r0, #0xFEFE |
|||
movt r0, #0xFEFE /* corresponds to loading x << 16 | y into r0 */ |
|||
|
|||
/* This is the loop that actually fills the stack with 0xFEFEFEFE */ |
|||
fiq_loop: |
|||
cmp r1, sp /* compares the value in R1 to the value in SP */ |
|||
strlt r0, [r1], #4 /* If R1 is less than SP, |
|||
the value in R0 will be written to the |
|||
address stored in R1, |
|||
and R1 gets increased by 4 */ |
|||
blt fiq_loop /* the loop continues as long as R1 is less than SP */ |
|||
|
|||
/* IRQ stack */ |
|||
msr cpsr_c, MODE_IRQ |
|||
ldr r1, =_irq_stack_start |
|||
ldr sp, =_irq_stack_end |
|||
|
|||
/* fill irq stack */ |
|||
irq_loop: |
|||
cmp r1, sp |
|||
strlt r0, [r1], #4 |
|||
blt irq_loop |
|||
|
|||
/* Supervisor mode */ |
|||
msr cpsr_c, MODE_SVC |
|||
ldr r1, =_stack_start |
|||
ldr sp, =_stack_end |
|||
|
|||
/* fill the supervisor mode stack */ |
|||
stack_loop: |
|||
cmp r1, sp |
|||
strlt r0, [r1], #4 |
|||
blt stack_loop |
|||
|
|||
/* Start copying data */ |
|||
ldr r0, =_text_end /* section address has been defined in ld script */ |
|||
ldr r1, =_data_start |
|||
ldr r2, =_data_end |
|||
|
|||
/* loop continues over the entirety of .data in ROM */ |
|||
data_loop: |
|||
cmp r1, r2 |
|||
ldrlt r3, [r0], #4 /* t load 4 bytes of data from ROM into R3 */ |
|||
strlt r3, [r1], #4 |
|||
blt data_loop |
|||
|
|||
/* Initialize .bss */ |
|||
clear_bss: |
|||
mov r0, #0 |
|||
ldr r1, =_bss_start |
|||
ldr r2, =_bss_end |
|||
|
|||
/* loop over memory between the addresses _bss_start and _bss_end */ |
|||
/* there is no ROM address, and zeros just take up space */ |
|||
bss_loop: |
|||
cmp r1, r2 |
|||
strlt r0, [r1], #4 |
|||
blt bss_loop |
|||
|
|||
#ifdef CONFIG_USE_CACHE |
|||
init_cache_mmu: |
|||
ldr r0, =platform_mem_desc |
|||
ldr r1, =platform_mem_desc_size |
|||
ldr r1, [r1] |
|||
bl InitMMUTable |
|||
bl InitCache |
|||
#endif |
|||
|
|||
start_up: |
|||
cpsie i /* enable irq */ |
|||
b c_startup /* jump to C startup code */ |
|||
b Abort_Exception |
|||
@ -1,83 +0,0 @@ |
|||
#include "sdkconfig.h" |
|||
|
|||
/* allocatable and executable */ |
|||
.section .vector_table, "ax" |
|||
|
|||
.balign 2048 |
|||
.global system_vectors |
|||
system_vectors: |
|||
b Reset_Handler |
|||
b Undef_Handler /* 0x4 Undefined Instruction */ |
|||
b SWI_Handler /* 0x8 Software Interrupt */ |
|||
b Pref_Handler /* 0xC Prefetch Abort */ |
|||
b Databt_Handler /* 0x10 Data Abort */ |
|||
b . /* 0x14 Reserved */ |
|||
b IRQ_Handler /* 0x18 IRQ */ |
|||
b Fiq_Handler /* 0x1C FIQ */ |
|||
|
|||
.global Abort_Exception |
|||
Abort_Exception: |
|||
swi 0xFF |
|||
|
|||
.align 4 |
|||
.arm |
|||
.weak IRQ_Handler |
|||
.type IRQ_Handler, %function |
|||
.global IRQ_Handler |
|||
IRQ_Handler: /* 0x18 IRQ */ |
|||
push {lr} /* Save return address+4 */ |
|||
push {r0-r3, r12} /* Push caller save registers */ |
|||
|
|||
mrs r0, spsr /* Save SPRS to allow interrupt reentry */ |
|||
push {r0} |
|||
|
|||
/* Get GIC base address MRC P15, 4, r1, C15, C0, 0 */ |
|||
//<! get iar |
|||
mrc p15, 0, r0, c12, c12, 0 |
|||
isb |
|||
|
|||
push {r0, r1} |
|||
|
|||
cps #0x13 /* Change to Supervisor mode to allow interrupt reentry */ |
|||
|
|||
push {lr} /* Save Supervisor lr */ |
|||
|
|||
ldr r2, =SystemIrqHandler |
|||
blx r2 /* b irq_debug Call SystemIrqHandler with param GCC */ |
|||
|
|||
pop {lr} |
|||
|
|||
cps #0x12 /* Back to IRQ mode */ |
|||
|
|||
pop {r0, r1} |
|||
|
|||
pop {r0} |
|||
msr spsr_cxsf, r0 |
|||
|
|||
pop {r0-r3, r12} |
|||
pop {lr} |
|||
subs pc, lr, #4 |
|||
|
|||
.global Fiq_Handler |
|||
Fiq_Handler: /* 0x18 IRQ */ |
|||
b Abort_Exception |
|||
|
|||
.global Undef_Handler |
|||
Undef_Handler: /* 0x4 Undefined Instruction */ |
|||
b Abort_Exception |
|||
|
|||
.align 2 |
|||
.arm |
|||
.weak SWI_Handler |
|||
.type SWI_Handler, %function |
|||
.global SWI_Handler |
|||
SWI_Handler: /* 0x8 Software Interrupt */ |
|||
b Abort_Exception |
|||
|
|||
.global Pref_Handler |
|||
Pref_Handler: /* 0xC Prefetch Abort */ |
|||
b Abort_Exception |
|||
|
|||
.global Databt_Handler |
|||
Databt_Handler: /* 0x10 Data Abort */ |
|||
b Abort_Exception |
|||
@ -1,115 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-21 14:11:09 |
|||
* @LastEditTime: 2021-06-24 13:41:24 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "parameters.h" |
|||
#include "generic_timer.h" |
|||
#include "aarch32.h" |
|||
#include "ft_debug.h" |
|||
|
|||
//#define ENABLE_A32GT_DEBUG
|
|||
#define A32GT_DEBUG_TAG "A32GT" |
|||
#ifdef ENABLE_A32GT_DEBUG |
|||
#define A32GT_ERROR(format, ...) FT_DEBUG_PRINT_E(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) |
|||
#define A32GT_DEBUG_I(format, ...) FT_DEBUG_PRINT_I(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) |
|||
#define A32GT_DEBUG_W(format, ...) FT_DEBUG_PRINT_W(A32GT_DEBUG_TAG, format, ##__VA_ARGS__) |
|||
#else |
|||
#define A32GT_ERROR(format, ...) |
|||
#define A32GT_DEBUG_I(format, ...) |
|||
#define A32GT_DEBUG_W(format, ...) |
|||
#endif |
|||
|
|||
#define AARCH32_CNTP_CTL_ENABLE_MASK (1ul << 0) |
|||
#define AARCH32_CNTP_CTL_INTERRUPT_MASK (1ul << 1) |
|||
|
|||
void Aarch32TimerStart(void) |
|||
{ |
|||
u32 ctrl = aarch32_cntp_ctl_get(); |
|||
|
|||
if (!(ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) |
|||
{ |
|||
ctrl |= AARCH32_CNTP_CTL_ENABLE_MASK; |
|||
aarch32_cntp_ctl_set(ctrl); |
|||
} |
|||
|
|||
A32GT_DEBUG_I("ctrl: 0x%x", aarch32_cntp_ctl_get()); |
|||
} |
|||
|
|||
void Aarch32TimerStop(void) |
|||
{ |
|||
u32 ctrl = aarch32_cntp_ctl_get(); |
|||
if ((ctrl & AARCH32_CNTP_CTL_ENABLE_MASK)) |
|||
{ |
|||
ctrl &= ~AARCH32_CNTP_CTL_ENABLE_MASK; |
|||
aarch32_cntp_ctl_set(ctrl); |
|||
} |
|||
} |
|||
|
|||
void Aarch32TimerInterruptEnable(void) |
|||
{ |
|||
u32 ctrl = aarch32_cntp_ctl_get(); |
|||
if (ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK) |
|||
{ |
|||
ctrl &= ~AARCH32_CNTP_CTL_INTERRUPT_MASK; |
|||
aarch32_cntp_ctl_set(ctrl); |
|||
} |
|||
A32GT_DEBUG_I("i mask: 0x%x", aarch32_cntp_ctl_get()); |
|||
} |
|||
|
|||
void Aarch32TimerInterruptDisable(void) |
|||
{ |
|||
u64 ctrl = aarch32_cntp_ctl_get(); |
|||
if (!(ctrl & AARCH32_CNTP_CTL_INTERRUPT_MASK)) |
|||
{ |
|||
ctrl |= AARCH32_CNTP_CTL_INTERRUPT_MASK; |
|||
aarch32_cntp_ctl_set(ctrl); |
|||
} |
|||
} |
|||
|
|||
u32 Aarch32TimerFrequecy(void) |
|||
{ |
|||
u32 rate = aarch32_cntfrq_get(); |
|||
return (rate != 0) ? rate : 1000000; |
|||
} |
|||
|
|||
u64 Aarch32TimerRead(void) |
|||
{ |
|||
return aarch32_cntpct_get(); |
|||
} |
|||
|
|||
void Aarch32TimerCompare(u32 interval) |
|||
{ |
|||
aarch32_cntp_tval_set(interval); |
|||
} |
|||
|
|||
void Aarch32Delay(u32 ms) |
|||
{ |
|||
u64 current = Aarch32TimerRead(); |
|||
u64 condition = current + GENERIC_TIMER_CLK_FREQ_KHZ * ms; |
|||
|
|||
while (condition > current) |
|||
{ |
|||
current = Aarch32TimerRead(); |
|||
} |
|||
} |
|||
|
|||
void Aarch32Udelay(u32 us) |
|||
{ |
|||
u64 current = Aarch32TimerRead(); |
|||
u64 condition = current + GENERIC_TIMER_CLK_FREQ_MHZ * us; |
|||
|
|||
while (condition > current) |
|||
{ |
|||
current = Aarch32TimerRead(); |
|||
} |
|||
} |
|||
@ -1,39 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-21 14:10:59 |
|||
* @LastEditTime: 2021-06-24 13:26:56 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H |
|||
#define BSP_ARCH_ARMV8_AARCH32_GENERIC_TIMER_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
void Aarch32TimerStart(void); |
|||
void Aarch32TimerStop(void); |
|||
void Aarch32TimerInterruptEnable(void); |
|||
void Aarch32TimerInterruptDisable(void); |
|||
u32 Aarch32TimerFrequecy(void); |
|||
u64 Aarch32TimerRead(void); |
|||
void Aarch32TimerCompare(u32 interval); |
|||
void Aarch32Delay(u32 ms); |
|||
void Aarch32Udelay(u32 us); |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,188 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 09:20:24 |
|||
* @LastEditTime: 2021-06-29 10:09:30 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include <stdio.h> |
|||
#include "ft_types.h" |
|||
#include "mmu.h" |
|||
#include "cp15.h" |
|||
|
|||
/* dump 2nd level page table */ |
|||
void Dump2ndPageTable(u32 *ptb) |
|||
{ |
|||
int i; |
|||
int fcnt = 0; |
|||
|
|||
for (i = 0; i < 256; i++) |
|||
{ |
|||
u32 pte2 = ptb[i]; |
|||
if ((pte2 & 0x3) == 0) |
|||
{ |
|||
if (fcnt == 0) |
|||
printf(" "); |
|||
printf("%04x: ", i); |
|||
fcnt++; |
|||
if (fcnt == 16) |
|||
{ |
|||
printf("fault\n"); |
|||
fcnt = 0; |
|||
} |
|||
continue; |
|||
} |
|||
if (fcnt != 0) |
|||
{ |
|||
printf("fault\n"); |
|||
fcnt = 0; |
|||
} |
|||
|
|||
printf(" %04x: %x: ", i, pte2); |
|||
if ((pte2 & 0x3) == 0x1) |
|||
{ |
|||
printf("L,ap:%x,xn:%d,texcb:%02x\n", |
|||
((pte2 >> 7) | (pte2 >> 4))& 0xf, |
|||
(pte2 >> 15) & 0x1, |
|||
((pte2 >> 10) | (pte2 >> 2)) & 0x1f); |
|||
} |
|||
else |
|||
{ |
|||
printf("S,ap:%x,xn:%d,texcb:%02x\n", |
|||
((pte2 >> 7) | (pte2 >> 4))& 0xf, pte2 & 0x1, |
|||
((pte2 >> 4) | (pte2 >> 2)) & 0x1f); |
|||
} |
|||
} |
|||
} |
|||
|
|||
void DumpPageTable(u32 *ptb) |
|||
{ |
|||
int i; |
|||
int fcnt = 0; |
|||
|
|||
printf("page table@%p\n", ptb); |
|||
for (i = 0; i < 1024*4; i++) |
|||
{ |
|||
u32 pte1 = ptb[i]; |
|||
if ((pte1 & 0x3) == 0) |
|||
{ |
|||
printf("%03x: ", i); |
|||
fcnt++; |
|||
if (fcnt == 16) |
|||
{ |
|||
printf("fault\n"); |
|||
fcnt = 0; |
|||
} |
|||
continue; |
|||
} |
|||
if (fcnt != 0) |
|||
{ |
|||
printf("fault\n"); |
|||
fcnt = 0; |
|||
} |
|||
|
|||
printf("%03x: %08x: ", i, pte1); |
|||
if ((pte1 & 0x3) == 0x3) |
|||
{ |
|||
printf("LPAE\n"); |
|||
} |
|||
else if ((pte1 & 0x3) == 0x1) |
|||
{ |
|||
printf("pte,ns:%d,domain:%d\n", |
|||
(pte1 >> 3) & 0x1, (pte1 >> 5) & 0xf); |
|||
/*
|
|||
*rt_hw_cpu_dump_page_table_2nd((void*)((pte1 & 0xfffffc000) |
|||
* - 0x80000000 + 0xC0000000)); |
|||
*/ |
|||
} |
|||
else if (pte1 & (1 << 18)) |
|||
{ |
|||
printf("super section,ns:%d,ap:%x,xn:%d,texcb:%02x\n", |
|||
(pte1 >> 19) & 0x1, |
|||
((pte1 >> 13) | (pte1 >> 10))& 0xf, |
|||
(pte1 >> 4) & 0x1, |
|||
((pte1 >> 10) | (pte1 >> 2)) & 0x1f); |
|||
} |
|||
else |
|||
{ |
|||
printf("section,ns:%d,ap:%x," |
|||
"xn:%d,texcb:%02x,domain:%d\n", |
|||
(pte1 >> 19) & 0x1, |
|||
((pte1 >> 13) | (pte1 >> 10))& 0xf, |
|||
(pte1 >> 4) & 0x1, |
|||
(((pte1 & (0x7 << 12)) >> 10) | |
|||
((pte1 & 0x0c) >> 2)) & 0x1f, |
|||
(pte1 >> 5) & 0xf); |
|||
} |
|||
} |
|||
} |
|||
|
|||
/* level1 page table, each entry for 1MB memory. */ |
|||
static volatile unsigned long MMUTable[4*1024] __attribute__((aligned(16*1024))); |
|||
void SetMMUTable(u32 vaddrStart, |
|||
u32 vaddrEnd, |
|||
u32 paddrStart, |
|||
u32 attr) |
|||
{ |
|||
volatile u32 *pTT; |
|||
volatile int i, nSec; |
|||
pTT = (u32 *)MMUTable + (vaddrStart >> 20); |
|||
nSec = (vaddrEnd >> 20) - (vaddrStart >> 20); |
|||
for(i = 0; i <= nSec; i++) |
|||
{ |
|||
*pTT = attr | (((paddrStart >> 20) + i) << 20); |
|||
pTT++; |
|||
} |
|||
} |
|||
|
|||
unsigned long SetDomainReg(unsigned long domain_val) |
|||
{ |
|||
unsigned long old_domain; |
|||
|
|||
asm volatile ("mrc p15, 0, %0, c3, c0\n" : "=r" (old_domain)); |
|||
asm volatile ("mcr p15, 0, %0, c3, c0\n" : :"r" (domain_val) : "memory"); |
|||
|
|||
return old_domain; |
|||
} |
|||
|
|||
void InitMMUTable(struct mem_desc *mdesc, u32 size) |
|||
{ |
|||
/* set page table */ |
|||
for(; size > 0; size--) |
|||
{ |
|||
SetMMUTable(mdesc->vaddr_start, mdesc->vaddr_end, |
|||
mdesc->paddr_start, mdesc->attr); |
|||
mdesc++; |
|||
} |
|||
} |
|||
|
|||
void InitMMU(void) |
|||
{ |
|||
#ifdef CONFIG_USE_MMU |
|||
cpu_mmu_disable(); |
|||
/*rt_hw_cpu_dump_page_table(MMUTable);*/ |
|||
SetDomainReg(0x55555555); |
|||
cpu_tlb_set(MMUTable); |
|||
cpu_mmu_enable(); |
|||
#endif |
|||
} |
|||
|
|||
void InitCache(void) |
|||
{ |
|||
cpu_dcache_clean_flush(); |
|||
cpu_icache_flush(); |
|||
cpu_dcache_disable(); |
|||
cpu_icache_disable(); |
|||
|
|||
InitMMU(); |
|||
|
|||
cpu_icache_enable(); |
|||
cpu_dcache_enable(); |
|||
} |
|||
@ -1,53 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 09:20:31 |
|||
* @LastEditTime: 2021-07-01 17:25:19 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_AARCH32_MMU_H |
|||
#define BSP_ARCH_AARCH32_MMU_H |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
#define DESC_SEC (0x2) |
|||
#define MEMWBWA ((1 << 12) | (3 << 2)) /* write back, write allocate */ |
|||
#define MEMWB (3 << 2) /* write back, no write allocate */ |
|||
#define MEMWT (2 << 2) /* write through, no write allocate */ |
|||
#define SHAREDEVICE (1 << 2) /* shared device */ |
|||
#define STRONGORDER (0 << 2) /* strong ordered */ |
|||
#define XN (1 << 4) /* eXecute Never */ |
|||
#define AP_RW (3 << 10) /* supervisor=RW, user=RW */ |
|||
#define AP_RO (2 << 10) /* supervisor=RW, user=RO */ |
|||
#define SHARED (1 << 16) /* shareable */ |
|||
|
|||
#define DOMAIN_FAULT (0x0) |
|||
#define DOMAIN_CHK (0x1) |
|||
#define DOMAIN_NOTCHK (0x3) |
|||
#define DOMAIN0 (0x0 << 5) |
|||
#define DOMAIN1 (0x1 << 5) |
|||
|
|||
#define DOMAIN0_ATTR (DOMAIN_CHK << 0) |
|||
#define DOMAIN1_ATTR (DOMAIN_FAULT << 2) |
|||
|
|||
/* device mapping type */ |
|||
#define DEVICE_MEM (SHARED | AP_RW | DOMAIN0 | SHAREDEVICE | DESC_SEC | XN) |
|||
/* normal memory mapping type */ |
|||
#define NORMAL_MEM (SHARED | AP_RW | DOMAIN0 | MEMWBWA | DESC_SEC) |
|||
|
|||
struct mem_desc |
|||
{ |
|||
u32 vaddr_start; |
|||
u32 vaddr_end; |
|||
u32 paddr_start; |
|||
u32 attr; |
|||
}; |
|||
|
|||
#endif |
|||
@ -1,32 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 13:19:37 |
|||
* @LastEditTime: 2021-07-01 17:21:03 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include "early_uart.h" |
|||
|
|||
void OutByte(s8 byte) |
|||
{ |
|||
|
|||
while ((FtIn32(0x2800d018) & 0x20) == 0x20) |
|||
{ |
|||
} |
|||
|
|||
FtOut32(0x2800d000, (u32)byte); |
|||
} |
|||
|
|||
char GetByte(void) |
|||
{ |
|||
while ((FtIn32(0x2800d018) & 0x10) == 0x10) |
|||
; |
|||
|
|||
return (char)FtIn32(0x2800d000); |
|||
} |
|||
@ -1,31 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 13:19:37 |
|||
* @LastEditTime: 2021-06-25 16:26:47 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H |
|||
#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
#include "ft_types.h" |
|||
#include "ft_io.h" |
|||
|
|||
void OutByte(s8 byte); |
|||
char GetByte(void); |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,39 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 15:13:47 |
|||
* @LastEditTime: 2021-07-01 17:34:02 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "parameters.h" |
|||
#include "mmu.h" |
|||
|
|||
#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) |
|||
|
|||
struct mem_desc platform_mem_desc[] = { |
|||
{0X00, |
|||
0x40000000, |
|||
0X00, |
|||
DEVICE_MEM}, |
|||
{0x40000000, |
|||
0x10000000, |
|||
0x40000000, |
|||
DEVICE_MEM}, |
|||
{0x50000000, |
|||
0x30000000, |
|||
0x50000000, |
|||
DEVICE_MEM}, |
|||
{0x80000000, |
|||
0x80000000, |
|||
0x80000000, |
|||
DDR_MEM}, |
|||
}; |
|||
|
|||
const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); |
|||
@ -1,89 +0,0 @@ |
|||
#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H |
|||
#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_FT2004_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
/* Device register address */ |
|||
#define FT_DEV_BASE_ADDR 0x28000000 |
|||
#define FT_DEV_END_ADDR 0x2FFFFFFF |
|||
|
|||
/* PCI */ |
|||
#define FT_PCI_CONFIG_BASEADDR 0x40000000 |
|||
#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 |
|||
|
|||
#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 |
|||
#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 |
|||
|
|||
#define FT_PCI_MEM32_BASEADDR 0x58000000 |
|||
#define FT_PCI_MEM32_REG_LENGTH 0x27000000 |
|||
|
|||
// timer
|
|||
|
|||
#define GENERIC_TIMER_CLK_FREQ 2000000 |
|||
#define GENERIC_TIMER_CLK_FREQ_KHZ 2000 |
|||
#define GENERIC_TIMER_CLK_FREQ_MHZ 48 |
|||
#define GENERIC_TIMER_NS_IRQ_NUM 30 |
|||
#define GENERIC_TIMER_NS_CLK_FREQ 2000000 |
|||
#define COUNTS_PER_SECOND GENERIC_TIMER_NS_CLK_FREQ |
|||
|
|||
// UART
|
|||
|
|||
#define FT_UART_NUM 4 |
|||
#define FT_UART_REG_LENGTH 0x18000 |
|||
|
|||
#define FT_UART0_ID 0 |
|||
#define FT_UART0_IRQ_NUM (85 + 30) |
|||
#define FT_UART0_BASE_ADDR 0x2800c000 |
|||
#define FT_UART0_CLK_FREQ_HZ 100000000 |
|||
|
|||
#define FT_UART1_ID 1 |
|||
#define FT_UART1_IRQ_NUM (86 + 30) |
|||
#define FT_UART1_BASE_ADDR 0x2800d000 |
|||
#define FT_UART1_CLK_FREQ_HZ 100000000 |
|||
|
|||
#define FT_UART2_ID 2 |
|||
#define FT_UART2_IRQ_NUM (87 + 30) |
|||
#define FT_UART2_BASE_ADDR 0x2800e000 |
|||
#define FT_UART2_CLK_FREQ_HZ 100000000 |
|||
|
|||
#define FT_UART3_BASE_ADDR 0x2800f000 |
|||
#define FT_UART3_ID 3 |
|||
#define FT_UART3_IRQ_NUM (88 + 30) |
|||
#define FT_UART3_CLK_FREQ_HZ 100000000 |
|||
|
|||
#define FT_STDOUT_base_address FT_UART1_BASE_ADDR |
|||
#define FT_STDIN_base_address FT_UART1_BASE_ADDR |
|||
|
|||
/****** GIC v3 *****/ |
|||
#define FT_GICV3_INSTANCES_NUM 1U |
|||
#define GICV3_REG_LENGTH 0x00009000 |
|||
|
|||
/*
|
|||
* The maximum priority value that can be used in the GIC. |
|||
*/ |
|||
#define GICV3_MAX_INTR_PRIO_VAL 240U |
|||
#define GICV3_INTR_PRIO_MASK 0x000000f0U |
|||
|
|||
#define ARM_GIC_NR_IRQS 160 |
|||
#define ARM_GIC_IRQ_START 0 |
|||
|
|||
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ |
|||
#define SGI_INT_MAX 16 |
|||
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ |
|||
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ |
|||
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ |
|||
|
|||
#define GICV3_BASEADDRESS 0x30800000U |
|||
#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) |
|||
#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) |
|||
|
|||
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,32 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 13:19:37 |
|||
* @LastEditTime: 2021-06-25 16:26:59 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include "early_uart.h" |
|||
|
|||
void OutByte(s8 byte) |
|||
{ |
|||
|
|||
while ((FtIn32(0x28001018) & 0x20) == 0x20) |
|||
{ |
|||
} |
|||
|
|||
FtOut32(0x28001000, (u32)byte); |
|||
} |
|||
|
|||
char GetByte(void) |
|||
{ |
|||
while ((FtIn32(0x28001018) & 0x10) == 0x10) |
|||
; |
|||
|
|||
return (char)FtIn32(0x28001000); |
|||
} |
|||
@ -1,31 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 13:19:37 |
|||
* @LastEditTime: 2021-06-25 16:26:47 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#ifndef BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H |
|||
#define BSP_ARCH_ARMV8_AARCH64_PLATFORM_UART_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
#include "ft_types.h" |
|||
#include "ft_io.h" |
|||
|
|||
void OutByte(s8 byte); |
|||
char GetByte(void); |
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,59 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 15:13:47 |
|||
* @LastEditTime: 2021-06-29 15:14:59 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "parameters.h" |
|||
#include "mmu.h" |
|||
|
|||
#define DDR_MEM (SHARED | AP_RW | DOMAIN0 | MEMWT | DESC_SEC) |
|||
|
|||
struct mem_desc platform_mem_desc[] = { |
|||
{0x80000000, |
|||
0x80000000 + 0x7f000000, |
|||
0x80000000, |
|||
DDR_MEM}, |
|||
{0, //< QSPI
|
|||
0x1FFFFFFF, |
|||
0, |
|||
DEVICE_MEM}, |
|||
{0x20000000, //<! LPC
|
|||
0x27FFFFFF, |
|||
0x20000000, |
|||
DEVICE_MEM}, |
|||
{FT_DEV_BASE_ADDR, //<! Device register
|
|||
FT_DEV_END_ADDR, |
|||
FT_DEV_BASE_ADDR, |
|||
DEVICE_MEM}, |
|||
{0x30000000, //<! debug
|
|||
0x39FFFFFF, |
|||
0x30000000, |
|||
DEVICE_MEM}, |
|||
{0x3A000000, //<! Internal register space in the on-chip network
|
|||
0x3AFFFFFF, |
|||
0x3A000000, |
|||
DEVICE_MEM}, |
|||
{FT_PCI_CONFIG_BASEADDR, |
|||
FT_PCI_CONFIG_BASEADDR + FT_PCI_CONFIG_REG_LENGTH, |
|||
FT_PCI_CONFIG_BASEADDR, |
|||
DEVICE_MEM}, |
|||
{FT_PCI_IO_CONFIG_BASEADDR, |
|||
FT_PCI_IO_CONFIG_BASEADDR + FT_PCI_IO_CONFIG_REG_LENGTH, |
|||
FT_PCI_IO_CONFIG_BASEADDR, |
|||
DEVICE_MEM}, |
|||
{FT_PCI_MEM32_BASEADDR, |
|||
FT_PCI_MEM32_BASEADDR + FT_PCI_MEM32_REG_LENGTH, |
|||
FT_PCI_MEM32_BASEADDR, |
|||
DEVICE_MEM}, |
|||
}; |
|||
|
|||
const u32 platform_mem_desc_size = sizeof(platform_mem_desc) / sizeof(platform_mem_desc[0]); |
|||
@ -1,103 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-15 15:15:14 |
|||
* @LastEditTime: 2021-06-29 15:16:15 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H |
|||
#define BSP_ARCH_ARMV8_AARCH32_FT2004_PARAMETER_H |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
/* Device register address */ |
|||
#define FT_DEV_BASE_ADDR 0x28000000 |
|||
#define FT_DEV_END_ADDR 0x2FFFFFFF |
|||
|
|||
/* PCI */ |
|||
#define FT_PCI_CONFIG_BASEADDR 0x40000000 |
|||
#define FT_PCI_CONFIG_REG_LENGTH 0x10000000 |
|||
|
|||
#define FT_PCI_IO_CONFIG_BASEADDR 0x50000000 |
|||
#define FT_PCI_IO_CONFIG_REG_LENGTH 0x08000000 |
|||
|
|||
#define FT_PCI_MEM32_BASEADDR 0x58000000 |
|||
#define FT_PCI_MEM32_REG_LENGTH 0x27000000 |
|||
|
|||
|
|||
|
|||
#define GENERIC_TIMER_CLK_FREQ 48000000 |
|||
#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ |
|||
|
|||
// Gic
|
|||
#define ARM_GIC_NR_IRQS 160 |
|||
#define ARM_GIC_IRQ_START 0 |
|||
|
|||
/****** GIC v3 *****/ |
|||
#define FT_GICV3_INSTANCES_NUM 1U |
|||
#define GICV3_REG_LENGTH 0x00009000 |
|||
|
|||
/*
|
|||
* The maximum priority value that can be used in the GIC. |
|||
*/ |
|||
#define GICV3_MAX_INTR_PRIO_VAL 240U |
|||
#define GICV3_INTR_PRIO_MASK 0x000000f0U |
|||
|
|||
#define ARM_GIC_IPI_COUNT 16 /* MPCore IPI count */ |
|||
#define SGI_INT_MAX 16 |
|||
#define SPI_START_INT_NUM 32 /* SPI start at ID32 */ |
|||
#define PPI_START_INT_NUM 16 /* PPI start at ID16 */ |
|||
#define GIC_INT_MAX_NUM 1020 /* GIC max interrupts count */ |
|||
|
|||
#define GICV3_BASEADDRESS 0x29900000U |
|||
#define GICV3_DISTRIBUTOR_BASEADDRESS (GICV3_BASEADDRESS + 0) |
|||
#define GICV3_RD_BASEADDRESS (GICV3_BASEADDRESS + 0x80000U) |
|||
|
|||
#define FT_GICV3_VECTORTABLE_NUM GIC_INT_MAX_NUM |
|||
|
|||
// Timer
|
|||
#define GENERIC_TIMER_CLK_FREQ 48000000 |
|||
#define GENERIC_TIMER_CLK_FREQ_KHZ 48000 |
|||
#define GENERIC_TIMER_CLK_FREQ_MHZ 48 |
|||
#define COUNTS_PER_SECOND GENERIC_TIMER_CLK_FREQ |
|||
|
|||
#define GEN_TIMER_VIRTUAL_IRQN 27 /**< Virtual Timer Interrupt */ |
|||
#define GEN_TIMER_VIRTUAL_NOSECURE_IRQN 28 |
|||
#define GEN_TIMER_PHYSICAL_IRQn 29 |
|||
#define GEN_TIMER_PHYSICAL_NOSECURE_IRQN 30 /**< Secure Physical Timer Interrupt */ |
|||
|
|||
// UART
|
|||
#define FT_UART_NUM 4 |
|||
#define FT_UART_REG_LENGTH 0x18000 |
|||
|
|||
#define FT_UART0_ID 0 |
|||
#define FT_UART0_IRQ_NUM 38 |
|||
#define FT_UART0_BASE_ADDR 0x28000000 |
|||
#define FT_UART0_CLK_FREQ_HZ 48000000 |
|||
|
|||
#define FT_UART1_ID 1 |
|||
#define FT_UART1_IRQ_NUM 39 |
|||
#define FT_UART1_BASE_ADDR 0x28001000 |
|||
#define FT_UART1_CLK_FREQ_HZ 48000000 |
|||
|
|||
#define FT_UART2_ID 2 |
|||
#define FT_UART2_IRQ_NUM 40 |
|||
#define FT_UART2_BASE_ADDR 0x28002000 |
|||
#define FT_UART2_CLK_FREQ_HZ 48000000 |
|||
|
|||
#define FT_UART3_ID 3 |
|||
#define FT_UART3_IRQ_NUM 41 |
|||
#define FT_UART3_BASE_ADDR 0x28003000 |
|||
#define FT_UART3_CLK_FREQ_HZ 48000000 |
|||
|
|||
#define FT_STDOUT_base_address FT_UART1_BASE_ADDR |
|||
#define FT_STDIN_base_address FT_UART1_BASE_ADDR |
|||
|
|||
#endif |
|||
@ -1,50 +0,0 @@ |
|||
/* Copyright (c) 2009 - 2015 ARM LIMITED
|
|||
Copyright (c) 2016, Freescale Semiconductor, Inc. |
|||
|
|||
Redistribution and use in source and binary forms, with or without |
|||
modification, are permitted provided that the following conditions are met: |
|||
- Redistributions of source code must retain the above copyright |
|||
notice, this list of conditions and the following disclaimer. |
|||
- Redistributions in binary form must reproduce the above copyright |
|||
notice, this list of conditions and the following disclaimer in the |
|||
documentation and/or other materials provided with the distribution. |
|||
- Neither the name of ARM nor the names of its contributors may be used |
|||
to endorse or promote products derived from this software without |
|||
specific prior written permission. |
|||
* |
|||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
|||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
|||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
|||
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
|||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
|||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
|||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
|||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
|||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
|||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
|||
POSSIBILITY OF SUCH DAMAGE. |
|||
---------------------------------------------------------------------------*/ |
|||
|
|||
|
|||
#if defined ( __ICCARM__ ) |
|||
#pragma system_include /* treat file as system include file for MISRA check */ |
|||
#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) |
|||
#pragma clang system_header /* treat file as system include file */ |
|||
#endif |
|||
|
|||
#ifndef __CORE_CA_H |
|||
#define __CORE_CA_H |
|||
|
|||
/*------------------ GNU Compiler ----------------------*/ |
|||
#if defined ( __GNUC__ ) |
|||
#include "cortexa_gcc.h" |
|||
|
|||
/*------------------ ICC Compiler ----------------------*/ |
|||
#elif defined ( __ICCARM__ ) |
|||
#include "cortexa_iar.h" |
|||
|
|||
#endif |
|||
|
|||
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ |
|||
|
|||
#endif /* __CORE_CA_H */ |
|||
File diff suppressed because it is too large
@ -1,85 +0,0 @@ |
|||
/*
|
|||
* Copyright (c) 2016, Freescale Semiconductor, Inc. |
|||
* All rights reserved. |
|||
* |
|||
* Redistribution and use in source and binary forms, with or without modification, |
|||
* are permitted provided that the following conditions are met: |
|||
* |
|||
* o Redistributions of source code must retain the above copyright notice, this list |
|||
* of conditions and the following disclaimer. |
|||
* |
|||
* o Redistributions in binary form must reproduce the above copyright notice, this |
|||
* list of conditions and the following disclaimer in the documentation and/or |
|||
* other materials provided with the distribution. |
|||
* |
|||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its |
|||
* contributors may be used to endorse or promote products derived from this |
|||
* software without specific prior written permission. |
|||
* |
|||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND |
|||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED |
|||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
|||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR |
|||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
|||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
|||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
|||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
|||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
|||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
|||
*/ |
|||
|
|||
#ifndef __CORTEXA_GCC_H |
|||
#define __CORTEXA_GCC_H |
|||
|
|||
#include "cmsis_gcc.h" |
|||
|
|||
#define __STRINGIFY(x) #x |
|||
|
|||
#define __MCR(coproc, opcode_1, src, CRn, CRm, opcode_2) \ |
|||
__ASM volatile ("MCR " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ |
|||
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ |
|||
__STRINGIFY(opcode_2) \ |
|||
: : "r" (src) ) |
|||
|
|||
#define __MRC(coproc, opcode_1, CRn, CRm, opcode_2) \ |
|||
({ \ |
|||
uint32_t __dst; \ |
|||
__ASM volatile ("MRC " __STRINGIFY(p##coproc) ", " __STRINGIFY(opcode_1) ", " \ |
|||
"%0, " __STRINGIFY(c##CRn) ", " __STRINGIFY(c##CRm) ", " \ |
|||
__STRINGIFY(opcode_2) \ |
|||
: "=r" (__dst) ); \ |
|||
__dst; \ |
|||
}) |
|||
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_APSR(uint32_t apsr) |
|||
{ |
|||
__ASM volatile ("MSR apsr, %0" : : "r" (apsr) : "cc"); |
|||
} |
|||
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CPSR(void) |
|||
{ |
|||
uint32_t result; |
|||
|
|||
__ASM volatile ("MRS %0, cpsr" : "=r" (result) ); |
|||
return(result); |
|||
} |
|||
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CPSR(uint32_t cpsr) |
|||
{ |
|||
__ASM volatile ("MSR cpsr, %0" : : "r" (cpsr) : "cc"); |
|||
} |
|||
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPEXC(void) |
|||
{ |
|||
uint32_t result; |
|||
|
|||
__ASM volatile ("VMRS %0, fpexc" : "=r" (result) ); |
|||
return result; |
|||
} |
|||
|
|||
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPEXC(uint32_t fpexc) |
|||
{ |
|||
__ASM volatile ("VMSR fpexc, %0" : : "r" (fpexc)); |
|||
} |
|||
|
|||
#endif /* __CORTEXA_GCC_H */ |
|||
@ -1,34 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 16:07:31 |
|||
* @LastEditTime: 2021-06-29 11:48:58 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#include "early_uart.h" |
|||
|
|||
volatile unsigned int *const UART0DR = (unsigned int *)0x10009000u; |
|||
volatile unsigned int *const UART0FR = (unsigned int *)0x10009018u; |
|||
|
|||
void OutByte(s8 byte) |
|||
{ |
|||
while ((*UART0FR) & (1 << 5)) |
|||
{ |
|||
} |
|||
*UART0DR = byte; /* Transmit char */ |
|||
} |
|||
|
|||
char GetByte(void) |
|||
{ |
|||
while ((*UART0FR) & (1 << 4)) |
|||
{ |
|||
|
|||
} |
|||
return *UART0DR & 0xff; |
|||
} |
|||
@ -1,32 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-17 13:19:37 |
|||
* @LastEditTime: 2021-06-29 11:20:07 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H |
|||
#define BSP_ARCH_ARMV8_AARCH32_PLATFORM_UART_H |
|||
|
|||
#ifdef __cplusplus |
|||
extern "C" |
|||
{ |
|||
#endif |
|||
|
|||
#include "ft_types.h" |
|||
#include "ft_io.h" |
|||
|
|||
void OutByte(s8 byte); |
|||
char GetByte(void); |
|||
|
|||
#ifdef __cplusplus |
|||
} |
|||
#endif |
|||
|
|||
#endif // !
|
|||
@ -1,29 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-29 10:06:01 |
|||
* @LastEditTime: 2021-06-30 18:32:05 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "sdkconfig.h" |
|||
#include "parameters.h" |
|||
#ifdef CONFIG_USE_MMU |
|||
#include "mmu.h" |
|||
#endif |
|||
|
|||
#ifdef CONFIG_USE_MMU |
|||
struct mem_desc platform_mem_desc[] = { |
|||
{0x10000000, 0x50000000, 0x10000000, DEVICE_MEM}, |
|||
{0x60000000, 0xe0000000, 0x60000000, NORMAL_MEM} |
|||
}; |
|||
|
|||
const u32 platform_mem_desc_size = |
|||
sizeof(platform_mem_desc)/sizeof(platform_mem_desc[0]); |
|||
#endif |
|||
@ -1,26 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2021 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-06-30 18:28:14 |
|||
* @LastEditTime: 2021-06-30 18:33:11 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
#ifndef BSP_ARCH_ARMV8_AARCH32_QEMU_PARAMETER_H |
|||
#define BSP_ARCH_ARMV8_AARCH32_QEMU_PARAMETER_H |
|||
|
|||
// Timer
|
|||
#define GENERIC_TIMER_CLK_FREQ 24000000 |
|||
#define GENERIC_TIMER_CLK_FREQ_KHZ 24000 |
|||
#define GENERIC_TIMER_CLK_FREQ_MHZ 24 |
|||
|
|||
// Gic
|
|||
#define ARM_GIC_NR_IRQS 160 |
|||
#define ARM_GIC_IRQ_START 0 |
|||
|
|||
#endif |
|||
@ -1,313 +0,0 @@ |
|||
/*
|
|||
* Reference: ARM® Architecture Reference Manual ARMv8, for ARMv8-A architecture profile |
|||
*/ |
|||
#include <stdint.h> |
|||
#include "aarch64.h" |
|||
|
|||
/* CurrentEL, Current Exception Level
|
|||
EL, bits [3:2] |
|||
Current exception level. Possible values of this field are: |
|||
00 EL0 |
|||
01 EL1 |
|||
10 EL2 |
|||
11 EL3 |
|||
*/ |
|||
u32 raw_read_current_el(void) |
|||
{ |
|||
u32 current_el; |
|||
|
|||
__asm__ __volatile__("mrs %0, CurrentEL\n\t" |
|||
: "=r"(current_el) |
|||
: |
|||
: "memory"); |
|||
return current_el; |
|||
} |
|||
|
|||
u32 get_current_el(void) |
|||
{ |
|||
u32 current_el = raw_read_current_el(); |
|||
return ((current_el >> CURRENT_EL_SHIFT) & CURRENT_EL_MASK); |
|||
} |
|||
|
|||
u64 get_hcr_el2(void) |
|||
{ |
|||
u64 hcr_el2; |
|||
__asm__ __volatile__("mrs %0, hcr_el2\n\t" |
|||
: "=r"(hcr_el2) |
|||
: |
|||
: "memory"); |
|||
return hcr_el2; |
|||
} |
|||
|
|||
u32 get_esr_el1(void) |
|||
{ |
|||
u32 esr_el1; |
|||
__asm__ __volatile__("mrs %0, ESR_EL1\n\t" |
|||
: "=r"(esr_el1) |
|||
: |
|||
: "memory"); |
|||
return esr_el1; |
|||
} |
|||
|
|||
/* DAIF, Interrupt Mask Bits
|
|||
Allows access to the interrupt mask bits. |
|||
|
|||
D, bit [9]: Debug exceptions. |
|||
A, bit [8]: SError (System Error) mask bit. |
|||
I, bit [7]: IRQ mask bit. |
|||
F, bit [6]: FIQ mask bit. |
|||
value: |
|||
0 Exception not masked. |
|||
1 Exception masked. |
|||
*/ |
|||
u32 raw_read_daif(void) |
|||
{ |
|||
u32 daif; |
|||
|
|||
__asm__ __volatile__("mrs %0, DAIF\n\t" |
|||
: "=r"(daif) |
|||
: |
|||
: "memory"); |
|||
return daif; |
|||
} |
|||
|
|||
void raw_write_daif(u32 daif) |
|||
{ |
|||
__asm__ __volatile__("msr DAIF, %0\n\t" |
|||
: |
|||
: "r"(daif) |
|||
: "memory"); |
|||
} |
|||
|
|||
void enable_debug_exceptions(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFClr, %0\n\t" |
|||
: |
|||
: "i"(DAIF_DBG_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
void enable_serror_exceptions(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFClr, %0\n\t" |
|||
: |
|||
: "i"(DAIF_ABT_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
void disable_debug_exceptions(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFSet, %0\n\t" |
|||
: |
|||
: "i"(DAIF_DBG_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
void disable_serror_exceptions(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFSet, %0\n\t" |
|||
: |
|||
: "i"(DAIF_ABT_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
void disable_irq(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFSet, %0\n\t" |
|||
: |
|||
: "i"(DAIF_IRQ_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
void disable_fiq(void) |
|||
{ |
|||
__asm__ __volatile__("msr DAIFSet, %0\n\t" |
|||
: |
|||
: "i"(DAIF_FIQ_BIT) |
|||
: "memory"); |
|||
} |
|||
|
|||
/* SPSR_EL1, Saved Program Status Register (EL1)
|
|||
Holds the saved processor state when an exception is taken to EL1. |
|||
*/ |
|||
u32 raw_read_spsr_el1(void) |
|||
{ |
|||
u32 spsr_el1; |
|||
|
|||
__asm__ __volatile__("mrs %0, SPSR_EL1\n\t" |
|||
: "=r"(spsr_el1) |
|||
: |
|||
: "memory"); |
|||
return spsr_el1; |
|||
} |
|||
|
|||
void raw_write_spsr_el1(u32 spsr_el1) |
|||
{ |
|||
__asm__ __volatile__("msr SPSR_EL1, %0\n\t" |
|||
: |
|||
: "r"(spsr_el1) |
|||
: "memory"); |
|||
} |
|||
|
|||
/*
|
|||
ISR_EL1, Interrupt Status Register |
|||
Shows whether an IRQ, FIQ, or SError interrupt is pending. |
|||
*/ |
|||
u32 raw_read_isr_el1(void) |
|||
{ |
|||
u32 isr_el1; |
|||
|
|||
__asm__ __volatile__("mrs %0, ISR_EL1\n\t" |
|||
: "=r"(isr_el1) |
|||
: |
|||
: "memory"); |
|||
return isr_el1; |
|||
} |
|||
|
|||
/*
|
|||
RVBAR_EL1, Reset Vector Base Address Register (if EL2 and EL3 not implemented) |
|||
If EL1 is the highest exception level implemented, contains the |
|||
IMPLEMENTATION DEFINED address that execution starts from after reset when |
|||
executing in AArch64 state. |
|||
*/ |
|||
uint64_t raw_read_rvbar_el1(void) |
|||
{ |
|||
uint64_t rvbar_el1; |
|||
|
|||
__asm__ __volatile__("mrs %0, RVBAR_EL1\n\t" |
|||
: "=r"(rvbar_el1) |
|||
: |
|||
: "memory"); |
|||
return rvbar_el1; |
|||
} |
|||
|
|||
void raw_write_rvbar_el1(uint64_t rvbar_el1) |
|||
{ |
|||
__asm__ __volatile__("msr RVBAR_EL1, %0\n\t" |
|||
: |
|||
: "r"(rvbar_el1) |
|||
: "memory"); |
|||
} |
|||
|
|||
/* VBAR_EL1, Vector Base Address Register (EL1)
|
|||
Holds the exception base address for any exception that is taken to EL1. |
|||
*/ |
|||
uint64_t raw_read_vbar_el1(void) |
|||
{ |
|||
uint64_t vbar_el1; |
|||
|
|||
__asm__ __volatile__("mrs %0, VBAR_EL1\n\t" |
|||
: "=r"(vbar_el1) |
|||
: |
|||
: "memory"); |
|||
return vbar_el1; |
|||
} |
|||
|
|||
void raw_write_vbar_el1(uint64_t vbar_el1) |
|||
{ |
|||
__asm__ __volatile__("msr VBAR_EL1, %0\n\t" |
|||
: |
|||
: "r"(vbar_el1) |
|||
: "memory"); |
|||
} |
|||
|
|||
/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register
|
|||
Control register for the virtual timer. |
|||
|
|||
ISTATUS, bit [2]: The status of the timer interrupt. |
|||
IMASK, bit [1]: Timer interrupt mask bit. |
|||
ENABLE, bit [0]: Enables the timer. |
|||
*/ |
|||
u32 raw_read_cntv_ctl(void) |
|||
{ |
|||
u32 cntv_ctl; |
|||
|
|||
__asm__ __volatile__("mrs %0, CNTV_CTL_EL0\n\t" |
|||
: "=r"(cntv_ctl) |
|||
: |
|||
: "memory"); |
|||
return cntv_ctl; |
|||
} |
|||
|
|||
void disable_cntv(void) |
|||
{ |
|||
u32 cntv_ctl; |
|||
|
|||
cntv_ctl = raw_read_cntv_ctl(); |
|||
cntv_ctl &= ~CNTV_CTL_ENABLE; |
|||
__asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" |
|||
: |
|||
: "r"(cntv_ctl) |
|||
: "memory"); |
|||
} |
|||
|
|||
void enable_cntv(void) |
|||
{ |
|||
u32 cntv_ctl; |
|||
|
|||
cntv_ctl = raw_read_cntv_ctl(); |
|||
cntv_ctl |= CNTV_CTL_ENABLE; |
|||
__asm__ __volatile__("msr CNTV_CTL_EL0, %0\n\t" |
|||
: |
|||
: "r"(cntv_ctl) |
|||
: "memory"); |
|||
} |
|||
|
|||
/*
|
|||
CNTFRQ_EL0, Counter-timer Frequency register |
|||
Holds the clock frequency of the system counter. |
|||
*/ |
|||
u32 raw_read_cntfrq_el0(void) |
|||
{ |
|||
u32 cntfrq_el0; |
|||
|
|||
__asm__ __volatile__("mrs %0, CNTFRQ_EL0\n\t" |
|||
: "=r"(cntfrq_el0) |
|||
: |
|||
: "memory"); |
|||
return cntfrq_el0; |
|||
} |
|||
|
|||
void raw_write_cntfrq_el0(u32 cntfrq_el0) |
|||
{ |
|||
__asm__ __volatile__("msr CNTFRQ_EL0, %0\n\t" |
|||
: |
|||
: "r"(cntfrq_el0) |
|||
: "memory"); |
|||
} |
|||
|
|||
/* CNTVCT_EL0, Counter-timer Virtual Count register
|
|||
Holds the 64-bit virtual count value. |
|||
*/ |
|||
uint64_t raw_read_cntvct_el0(void) |
|||
{ |
|||
uint64_t cntvct_el0; |
|||
|
|||
__asm__ __volatile__("mrs %0, CNTVCT_EL0\n\t" |
|||
: "=r"(cntvct_el0) |
|||
: |
|||
: "memory"); |
|||
return cntvct_el0; |
|||
} |
|||
|
|||
/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register
|
|||
Holds the compare value for the virtual timer. |
|||
*/ |
|||
uint64_t raw_read_cntv_cval_el0(void) |
|||
{ |
|||
uint64_t cntv_cval_el0; |
|||
|
|||
__asm__ __volatile__("mrs %0, CNTV_CVAL_EL0\n\t" |
|||
: "=r"(cntv_cval_el0) |
|||
: |
|||
: "memory"); |
|||
return cntv_cval_el0; |
|||
} |
|||
|
|||
void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0) |
|||
{ |
|||
__asm__ __volatile__("msr CNTV_CVAL_EL0, %0\n\t" |
|||
: |
|||
: "r"(cntv_cval_el0) |
|||
: "memory"); |
|||
} |
|||
@ -1,236 +0,0 @@ |
|||
|
|||
|
|||
#ifndef BSP_ARCH_ARMV8 |
|||
#define BSP_ARCH_ARMV8 |
|||
|
|||
#include <stdint.h> |
|||
#include "ft_types.h" |
|||
|
|||
/* CurrentEL, Current Exception Level */ |
|||
#define CURRENT_EL_MASK 0x3 |
|||
#define CURRENT_EL_SHIFT 2 |
|||
|
|||
/* DAIF, Interrupt Mask Bits */ |
|||
#define DAIF_DBG_BIT (1 << 3) /* Debug mask bit */ |
|||
#define DAIF_ABT_BIT (1 << 2) /* Asynchronous abort mask bit */ |
|||
#define DAIF_IRQ_BIT (1 << 1) /* IRQ mask bit */ |
|||
#define DAIF_FIQ_BIT (1 << 0) /* FIQ mask bit */ |
|||
|
|||
/*
|
|||
* Interrupt flags |
|||
*/ |
|||
#define AARCH64_DAIF_FIQ (1) /* FIQ */ |
|||
#define AARCH64_DAIF_IRQ (2) /* IRQ */ |
|||
|
|||
/* Timer */ |
|||
#define CNTV_CTL_ENABLE (1 << 0) /* Enables the timer */ |
|||
#define CNTV_CTL_IMASK (1 << 1) /* Timer interrupt mask bit */ |
|||
#define CNTV_CTL_ISTATUS (1 << 2) /* The status of the timer interrupt. This bit is read-only */ |
|||
|
|||
//
|
|||
// AArch64 SPSR
|
|||
//
|
|||
#define AARCH64_SPSR_EL3h 0b1101 |
|||
#define AARCH64_SPSR_EL3t 0b1100 |
|||
#define AARCH64_SPSR_EL2h 0b1001 |
|||
#define AARCH64_SPSR_EL2t 0b1000 |
|||
#define AARCH64_SPSR_EL1h 0b0101 |
|||
#define AARCH64_SPSR_EL1t 0b0100 |
|||
#define AARCH64_SPSR_EL0t 0b0000 |
|||
#define AARCH64_SPSR_RW (1 << 4) |
|||
#define AARCH64_SPSR_F (1 << 6) |
|||
#define AARCH64_SPSR_I (1 << 7) |
|||
#define AARCH64_SPSR_A (1 << 8) |
|||
#define AARCH64_SPSR_D (1 << 9) |
|||
#define AARCH64_SPSR_IL (1 << 20) |
|||
#define AARCH64_SPSR_SS (1 << 21) |
|||
#define AARCH64_SPSR_V (1 << 28) |
|||
#define AARCH64_SPSR_C (1 << 29) |
|||
#define AARCH64_SPSR_Z (1 << 30) |
|||
#define AARCH64_SPSR_N (1 << 31) |
|||
|
|||
//
|
|||
// Multiprocessor Affinity Register
|
|||
//
|
|||
#define MPIDR_EL1_AFF3_LSB 32 |
|||
#define MPIDR_EL1_U (1 << 30) |
|||
#define MPIDR_EL1_MT (1 << 24) |
|||
#define MPIDR_EL1_AFF2_LSB 16 |
|||
#define MPIDR_EL1_AFF1_LSB 8 |
|||
#define MPIDR_EL1_AFF0_LSB 0 |
|||
#define MPIDR_EL1_AFF_WIDTH 8 |
|||
|
|||
//
|
|||
// Data Cache Zero ID Register
|
|||
//
|
|||
#define DCZID_EL0_BS_LSB 0 |
|||
#define DCZID_EL0_BS_WIDTH 4 |
|||
#define DCZID_EL0_DZP_LSB 5 |
|||
#define DCZID_EL0_DZP (1 << 5) |
|||
|
|||
//
|
|||
// System Control Register
|
|||
//
|
|||
#define SCTLR_EL1_UCI (1 << 26) |
|||
#define SCTLR_ELx_EE (1 << 25) |
|||
#define SCTLR_EL1_E0E (1 << 24) |
|||
#define SCTLR_ELx_WXN (1 << 19) |
|||
#define SCTLR_EL1_nTWE (1 << 18) |
|||
#define SCTLR_EL1_nTWI (1 << 16) |
|||
#define SCTLR_EL1_UCT (1 << 15) |
|||
#define SCTLR_EL1_DZE (1 << 14) |
|||
#define SCTLR_ELx_I (1 << 12) |
|||
#define SCTLR_EL1_UMA (1 << 9) |
|||
#define SCTLR_EL1_SED (1 << 8) |
|||
#define SCTLR_EL1_ITD (1 << 7) |
|||
#define SCTLR_EL1_THEE (1 << 6) |
|||
#define SCTLR_EL1_CP15BEN (1 << 5) |
|||
#define SCTLR_EL1_SA0 (1 << 4) |
|||
#define SCTLR_ELx_SA (1 << 3) |
|||
#define SCTLR_ELx_C (1 << 2) |
|||
#define SCTLR_ELx_A (1 << 1) |
|||
#define SCTLR_ELx_M (1 << 0) |
|||
|
|||
//
|
|||
// Architectural Feature Access Control Register
|
|||
//
|
|||
#define CPACR_EL1_TTA (1 << 28) |
|||
#define CPACR_EL1_FPEN (3 << 20) |
|||
|
|||
//
|
|||
// Architectural Feature Trap Register
|
|||
//
|
|||
#define CPTR_ELx_TCPAC (1 << 31) |
|||
#define CPTR_ELx_TTA (1 << 20) |
|||
#define CPTR_ELx_TFP (1 << 10) |
|||
|
|||
//
|
|||
// Secure Configuration Register
|
|||
//
|
|||
#define SCR_EL3_TWE (1 << 13) |
|||
#define SCR_EL3_TWI (1 << 12) |
|||
#define SCR_EL3_ST (1 << 11) |
|||
#define SCR_EL3_RW (1 << 10) |
|||
#define SCR_EL3_SIF (1 << 9) |
|||
#define SCR_EL3_HCE (1 << 8) |
|||
#define SCR_EL3_SMD (1 << 7) |
|||
#define SCR_EL3_EA (1 << 3) |
|||
#define SCR_EL3_FIQ (1 << 2) |
|||
#define SCR_EL3_IRQ (1 << 1) |
|||
#define SCR_EL3_NS (1 << 0) |
|||
|
|||
//
|
|||
// Hypervisor Configuration Register
|
|||
//
|
|||
#define HCR_EL2_ID (1 << 33) |
|||
#define HCR_EL2_CD (1 << 32) |
|||
#define HCR_EL2_RW (1 << 31) |
|||
#define HCR_EL2_TRVM (1 << 30) |
|||
#define HCR_EL2_HVC (1 << 29) |
|||
#define HCR_EL2_TDZ (1 << 28) |
|||
|
|||
#define INTERRUPT_ENABLE() __asm__ __volatile__("msr daifclr, #2" :: \ |
|||
: "memory") |
|||
|
|||
#define INTERRUPT_DISABLE() __asm__ __volatile__("msr daifset, #2" :: \ |
|||
: "memory") |
|||
|
|||
#define MODE_EL_SHIFT (0x2) |
|||
#define MODE_EL_MASK (0x3) |
|||
|
|||
#define MODE_EL3 (0x3) |
|||
#define MODE_EL2 (0x2) |
|||
#define MODE_EL1 (0x1) |
|||
#define MODE_EL0 (0x0) |
|||
|
|||
#define GET_EL(_mode) (((_mode) >> MODE_EL_SHIFT) & MODE_EL_MASK) |
|||
|
|||
/* memory synchronization operations */ |
|||
|
|||
/* Instruction Synchronization Barrier */ |
|||
#define ISB() __asm__ __volatile__("isb sy") |
|||
|
|||
/* Data Synchronization Barrier */ |
|||
#define DSB() __asm__ __volatile__("dsb sy") |
|||
|
|||
/* Data Memory Barrier */ |
|||
#define DMB() __asm__ __volatile__("dmb sy") |
|||
|
|||
/* Wait For Interrupt */ |
|||
#define wfi() asm volatile("wfi" \ |
|||
: \ |
|||
: \ |
|||
: "memory") |
|||
|
|||
/* Count leading zeroes (clz) */ |
|||
#define clz(arg) ( \ |
|||
{ \ |
|||
uint32_t rval; \ |
|||
__asm__ __volatile__( \ |
|||
"clz %0,%1" \ |
|||
: "=r"(rval) \ |
|||
: "r"(arg)); \ |
|||
rval; \ |
|||
}) |
|||
|
|||
#define MTCPDC(reg, val) __asm__ __volatile__("dc " #reg ",%0" \ |
|||
: \ |
|||
: "r"(val)) |
|||
#define MTCPIC(reg, val) __asm__ __volatile__("ic " #reg ",%0" \ |
|||
: \ |
|||
: "r"(val)) |
|||
|
|||
#define MTCPICALL(reg) __asm__ __volatile__("ic " #reg) |
|||
#define MTCPTLBI(reg) __asm__ __volatile__("tlbi " #reg) |
|||
#define MTCPAT(reg, val) __asm__ __volatile__("at " #reg ",%0" \ |
|||
: \ |
|||
: "r"(val)) |
|||
|
|||
#define AARCH64_READ_SYSREG(reg) ( \ |
|||
{ \ |
|||
uint64_t val; \ |
|||
__asm__ __volatile__("mrs %0," #reg \ |
|||
: "=r"(val)); \ |
|||
val; \ |
|||
}) |
|||
#define AARCH64_WRITE_SYSREG(reg, val) __asm__ __volatile__("msr " #reg ", %0\n\tdsb sy\n\tisb" ::"r"(val)); |
|||
|
|||
/* PSTATE and special purpose register access functions */ |
|||
uint32_t raw_read_current_el(void); |
|||
uint32_t get_current_el(void); |
|||
uint32_t raw_read_daif(void); |
|||
void raw_write_daif(uint32_t daif); |
|||
void enable_debug_exceptions(void); |
|||
void enable_serror_exceptions(void); |
|||
void enable_irq(void); |
|||
void enable_fiq(void); |
|||
void disable_debug_exceptions(void); |
|||
void disable_serror_exceptions(void); |
|||
void disable_irq(void); |
|||
void disable_fiq(void); |
|||
/* SPSR_EL1, Saved Program Status Register (EL1) */ |
|||
uint32_t raw_read_spsr_el1(void); |
|||
void raw_write_spsr_el1(uint32_t spsr_el1); |
|||
/* ISR_EL1, Interrupt Status Register */ |
|||
uint32_t raw_read_isr_el1(void); |
|||
uint64_t raw_read_rvbar_el1(void); |
|||
void raw_write_rvbar_el1(uint64_t rvbar_el1); |
|||
uint64_t raw_read_vbar_el1(void); |
|||
void raw_write_vbar_el1(uint64_t vbar_el1); |
|||
|
|||
/* CNTV_CTL_EL0, Counter-timer Virtual Timer Control register */ |
|||
uint32_t raw_read_cntv_ctl(void); |
|||
void disable_cntv(void); |
|||
void enable_cntv(void); |
|||
/* CNTFRQ_EL0, Counter-timer Frequency register */ |
|||
uint32_t raw_read_cntfrq_el0(void); |
|||
void raw_write_cntfrq_el0(uint32_t cntfrq_el0); |
|||
/* CNTVCT_EL0, Counter-timer Virtual Count register */ |
|||
uint64_t raw_read_cntvct_el0(void); |
|||
/* CNTV_CVAL_EL0, Counter-timer Virtual Timer CompareValue register */ |
|||
uint64_t raw_read_cntv_cval_el0(void); |
|||
void raw_write_cntv_cval_el0(uint64_t cntv_cval_el0); |
|||
|
|||
u64 get_hcr_el2(void); |
|||
u32 get_esr_el1(void); |
|||
#endif // V8_SYSTEM_H
|
|||
@ -1,106 +0,0 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0 */ |
|||
/*
|
|||
* Copyright (c) 2015, Linaro Limited |
|||
*/ |
|||
#ifndef __LINUX_ARM_SMCCC_H |
|||
#define __LINUX_ARM_SMCCC_H |
|||
|
|||
/*
|
|||
* This file provides common defines for ARM SMC Calling Convention as |
|||
* specified in |
|||
* http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html
|
|||
*/ |
|||
|
|||
#define ARM_SMCCC_STD_CALL 0 |
|||
#define ARM_SMCCC_FAST_CALL 1 |
|||
#define ARM_SMCCC_TYPE_SHIFT 31 |
|||
|
|||
#define ARM_SMCCC_SMC_32 0 |
|||
#define ARM_SMCCC_SMC_64 1 |
|||
#define ARM_SMCCC_CALL_CONV_SHIFT 30 |
|||
|
|||
#define ARM_SMCCC_OWNER_MASK 0x3F |
|||
#define ARM_SMCCC_OWNER_SHIFT 24 |
|||
|
|||
#define ARM_SMCCC_FUNC_MASK 0xFFFF |
|||
|
|||
#define ARM_SMCCC_IS_FAST_CALL(smc_val) \ |
|||
((smc_val) & (ARM_SMCCC_FAST_CALL << ARM_SMCCC_TYPE_SHIFT)) |
|||
#define ARM_SMCCC_IS_64(smc_val) \ |
|||
((smc_val) & (ARM_SMCCC_SMC_64 << ARM_SMCCC_CALL_CONV_SHIFT)) |
|||
#define ARM_SMCCC_FUNC_NUM(smc_val) ((smc_val)&ARM_SMCCC_FUNC_MASK) |
|||
#define ARM_SMCCC_OWNER_NUM(smc_val) \ |
|||
(((smc_val) >> ARM_SMCCC_OWNER_SHIFT) & ARM_SMCCC_OWNER_MASK) |
|||
|
|||
#define ARM_SMCCC_CALL_VAL(type, calling_convention, owner, func_num) \ |
|||
(((type) << ARM_SMCCC_TYPE_SHIFT) | \ |
|||
((calling_convention) << ARM_SMCCC_CALL_CONV_SHIFT) | \ |
|||
(((owner)&ARM_SMCCC_OWNER_MASK) << ARM_SMCCC_OWNER_SHIFT) | \ |
|||
((func_num)&ARM_SMCCC_FUNC_MASK)) |
|||
|
|||
#define ARM_SMCCC_OWNER_ARCH 0 |
|||
#define ARM_SMCCC_OWNER_CPU 1 |
|||
#define ARM_SMCCC_OWNER_SIP 2 |
|||
#define ARM_SMCCC_OWNER_OEM 3 |
|||
#define ARM_SMCCC_OWNER_STANDARD 4 |
|||
#define ARM_SMCCC_OWNER_TRUSTED_APP 48 |
|||
#define ARM_SMCCC_OWNER_TRUSTED_APP_END 49 |
|||
#define ARM_SMCCC_OWNER_TRUSTED_OS 50 |
|||
#define ARM_SMCCC_OWNER_TRUSTED_OS_END 63 |
|||
|
|||
#define ARM_SMCCC_QUIRK_NONE 0 |
|||
#define ARM_SMCCC_QUIRK_QCOM_A6 1 /* Save/restore register a6 */ |
|||
|
|||
#ifndef __ASSEMBLY__ |
|||
|
|||
#include <stdio.h> |
|||
/**
|
|||
* struct arm_smccc_res - Result from SMC/HVC call |
|||
* @a0-a3 result values from registers 0 to 3 |
|||
*/ |
|||
struct arm_smccc_res |
|||
{ |
|||
unsigned long a0; |
|||
unsigned long a1; |
|||
unsigned long a2; |
|||
unsigned long a3; |
|||
}; |
|||
|
|||
/**
|
|||
* struct arm_smccc_quirk - Contains quirk information |
|||
* @id: quirk identification |
|||
* @state: quirk specific information |
|||
* @a6: Qualcomm quirk entry for returning post-smc call contents of a6 |
|||
*/ |
|||
struct arm_smccc_quirk |
|||
{ |
|||
int id; |
|||
union |
|||
{ |
|||
unsigned long a6; |
|||
} state; |
|||
}; |
|||
|
|||
/**
|
|||
* __arm_smccc_smc() - make SMC calls |
|||
* @a0-a7: arguments passed in registers 0 to 7 |
|||
* @res: result values from registers 0 to 3 |
|||
* @quirk: points to an arm_smccc_quirk, or NULL when no quirks are required. |
|||
* |
|||
* This function is used to make SMC calls following SMC Calling Convention. |
|||
* The content of the supplied param are copied to registers 0 to 7 prior |
|||
* to the SMC instruction. The return values are updated with the content |
|||
* from register 0 to 3 on return from the SMC instruction. An optional |
|||
* quirk structure provides vendor specific behavior. |
|||
*/ |
|||
void __arm_smccc_smc(unsigned long a0, unsigned long a1, |
|||
unsigned long a2, unsigned long a3, unsigned long a4, |
|||
unsigned long a5, unsigned long a6, unsigned long a7, |
|||
struct arm_smccc_res *res, struct arm_smccc_quirk *quirk); |
|||
|
|||
#define arm_smccc_smc(...) __arm_smccc_smc(__VA_ARGS__, NULL) |
|||
|
|||
#define arm_smccc_smc_quirk(...) __arm_smccc_smc(__VA_ARGS__) |
|||
|
|||
#endif /*__ASSEMBLY__*/ |
|||
#endif /*__LINUX_ARM_SMCCC_H*/ |
|||
@ -1,193 +0,0 @@ |
|||
// SPDX-License-Identifier: GPL-2.0+
|
|||
/*
|
|||
* (C) Copyright 2013 |
|||
* David Feng <fenghua@phytium.com.cn> |
|||
* |
|||
* (C) Copyright 2016 |
|||
* Alexander Graf <agraf@suse.de> |
|||
*/ |
|||
|
|||
#include <stdint.h> |
|||
#include <stdio.h> |
|||
#include <stdbool.h> |
|||
#include <aarch64.h> |
|||
#include <kernel.h> |
|||
#include "ft_io.h" |
|||
#include "cache.h" |
|||
|
|||
extern int AsmInvaliDateL3dcache(); |
|||
extern void __asm_invalidate_dcache_all(); |
|||
extern void __asm_invalidate_dcache_range(uint64_t start, uint64_t end); |
|||
extern void __asm_flush_dcache_all(); |
|||
extern void __asm_flush_dcache_range(uint64_t start, uint64_t end); |
|||
extern void __asm_invalidate_icache_all(); |
|||
extern void __asm_invalidate_l3_icache(); |
|||
extern void __asm_invalidate_tlb_all(); |
|||
|
|||
/* FLUSH L3 CASHE */ |
|||
#ifdef CONFIG_USE_L3CACHE |
|||
#define HNF_BASE (unsigned long)(0x3A200000) |
|||
#define HNF_COUNT 0x8 |
|||
#define HNF_PSTATE_REQ (HNF_BASE + 0x10) |
|||
#define HNF_PSTATE_STAT (HNF_BASE + 0x18) |
|||
#define HNF_PSTATE_OFF 0x0 |
|||
#define HNF_PSTATE_SFONLY 0x1 |
|||
#define HNF_PSTATE_HALF 0x2 |
|||
#define HNF_PSTATE_FULL 0x3 |
|||
#define HNF_STRIDE 0x10000 |
|||
#endif |
|||
|
|||
int AsmFlushL3Dcache(void) |
|||
{ |
|||
|
|||
#ifdef CONFIG_USE_L3CACHE |
|||
int i, pstate; |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); |
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
{ |
|||
do |
|||
{ |
|||
pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); |
|||
} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
|||
} |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); |
|||
|
|||
#endif |
|||
return 0; |
|||
} |
|||
|
|||
int AsmInvaliDateL3dcache(void) |
|||
{ |
|||
#ifdef CONFIG_USE_L3CACHE |
|||
int i, pstate; |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
{ |
|||
do |
|||
{ |
|||
pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); |
|||
} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
|||
} |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); |
|||
#endif |
|||
return 0; |
|||
} |
|||
|
|||
void DcacheEnable(void) |
|||
{ |
|||
uint64_t reg; |
|||
|
|||
reg = AARCH64_READ_SYSREG(sctlr_el1); |
|||
|
|||
if (!(reg & SCTLR_ELx_C)) |
|||
{ |
|||
DcacheInvalidate(); |
|||
__asm_invalidate_tlb_all(); |
|||
reg |= SCTLR_ELx_C; |
|||
AARCH64_WRITE_SYSREG(sctlr_el1, reg); |
|||
} |
|||
} |
|||
|
|||
void DcacheDisable(void) |
|||
{ |
|||
uint64_t reg; |
|||
reg = AARCH64_READ_SYSREG(sctlr_el1); |
|||
|
|||
if (!(reg & SCTLR_ELx_C)) |
|||
return; |
|||
|
|||
reg &= (~SCTLR_ELx_C); |
|||
AARCH64_WRITE_SYSREG(sctlr_el1, reg); |
|||
INTERRUPT_DISABLE(); |
|||
|
|||
__asm_flush_dcache_all(); |
|||
|
|||
#ifdef CONFIG_USE_L3CACHE |
|||
int i, pstate; |
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_SFONLY); |
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
{ |
|||
do |
|||
{ |
|||
pstate = FtIn64(HNF_PSTATE_STAT + i * HNF_STRIDE); |
|||
} while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); |
|||
} |
|||
|
|||
for (i = 0; i < HNF_COUNT; i++) |
|||
FtOut64(HNF_PSTATE_REQ + i * HNF_STRIDE, HNF_PSTATE_FULL); |
|||
#endif |
|||
|
|||
__asm_invalidate_tlb_all(); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
|
|||
void DcacheInvalidate(void) |
|||
{ |
|||
INTERRUPT_DISABLE(); |
|||
__asm_invalidate_dcache_all(); |
|||
AsmInvaliDateL3dcache(); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
|
|||
void DcacheInvalidateRange(intptr adr, intptr len) |
|||
{ |
|||
INTERRUPT_DISABLE(); |
|||
__asm_invalidate_dcache_range(adr, adr + len); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
|
|||
void DcacheFlush(void) |
|||
{ |
|||
INTERRUPT_DISABLE(); |
|||
__asm_flush_dcache_all(); |
|||
AsmFlushL3Dcache(); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
|
|||
void DcacheFlushRange(intptr adr, intptr len) |
|||
{ |
|||
INTERRUPT_DISABLE(); |
|||
__asm_flush_dcache_range(adr, adr + len); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
|
|||
void IcacheEnable(void) |
|||
{ |
|||
uint64_t reg; |
|||
|
|||
reg = AARCH64_READ_SYSREG(sctlr_el1); |
|||
|
|||
if (!(reg & SCTLR_ELx_I)) |
|||
{ |
|||
IcacheInvalidate(); |
|||
reg |= SCTLR_ELx_I; |
|||
AARCH64_WRITE_SYSREG(sctlr_el1, reg); |
|||
} |
|||
} |
|||
|
|||
void IcacheDisable(void) |
|||
{ |
|||
uint64_t reg; |
|||
|
|||
reg = AARCH64_READ_SYSREG(sctlr_el1); |
|||
reg &= ~SCTLR_ELx_I; |
|||
AARCH64_WRITE_SYSREG(sctlr_el1, reg); |
|||
} |
|||
|
|||
void IcacheInvalidate(void) |
|||
{ |
|||
INTERRUPT_DISABLE(); |
|||
__asm_invalidate_icache_all(); |
|||
__asm_invalidate_l3_icache(); |
|||
INTERRUPT_ENABLE(); |
|||
} |
|||
@ -1,56 +0,0 @@ |
|||
#ifndef BSP_ARCH_AARCH64_CACHE_H |
|||
#define BSP_ARCH_AARCH64_CACHE_H |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
/**************************************************************
|
|||
* |
|||
* MMU Define |
|||
* |
|||
* *************************************************************/ |
|||
|
|||
/* Memory type */ |
|||
#define NORM_NONCACHE 0x401 /* normal non-cacheable */ |
|||
#define STRONG_ORDERED 0x409 /* stronly ordered (Device-nGnRnE) */ |
|||
#define DEVICE_MEMORY 0x40D /* device memory (Device-nGnRE) */ |
|||
#define RESERVED 0X00 /* reserved memory */ |
|||
|
|||
/* normal write-through cacheable inner shareable */ |
|||
#define NORM_WT_CACHE 0x711 |
|||
|
|||
/* normal write back cacheable inner-shareable */ |
|||
#define NORM_WB_CACHE 0x705 |
|||
|
|||
/*
|
|||
* shareability arrtibute only applicable to |
|||
* normal cacheable memory |
|||
*/ |
|||
#define INNER_SHAREABLE (0x3 << 8) |
|||
#define OUTER_SHAREABLE (0x2 << 8) |
|||
#define NON_SHAREABLE (~(0x3 << 8)) |
|||
|
|||
/* execution type */ |
|||
#define EXECUTE_NEVER ((0x1 << 53) | (0x1 << 54)) |
|||
|
|||
/* secure type */ |
|||
#define NON_SECURE (0x1 << 5) |
|||
|
|||
/**************************************************************
|
|||
* |
|||
* Cache Define |
|||
* |
|||
* *************************************************************/ |
|||
|
|||
/************************** Function Prototypes ******************************/ |
|||
void DcacheEnable(void); |
|||
void DcacheDisable(void); |
|||
void DcacheInvalidate(void); |
|||
void DcacheInvalidateRange(intptr adr, intptr len); |
|||
void DcacheFlush(void); |
|||
void DcacheFlushRange(intptr adr, intptr len); |
|||
|
|||
void IcacheEnable(void); |
|||
void IcacheDisable(void); |
|||
void IcacheInvalidate(void); |
|||
|
|||
#endif |
|||
@ -1,32 +0,0 @@ |
|||
#include "exception.h" |
|||
#include "ft_types.h" |
|||
#include <stdio.h> |
|||
|
|||
_WEAK void SystemIrqHandler(exception_frame *exc) |
|||
{ |
|||
} |
|||
|
|||
_WEAK void SerrHandle(exception_frame *exc) |
|||
{ |
|||
while (1) |
|||
{ |
|||
} |
|||
} |
|||
|
|||
_WEAK void common_trap_handler(exception_frame *exc) |
|||
{ |
|||
printf("exc_type %x \r\n ", exc->exc_type); |
|||
if ((exc->exc_type & 0xff) == AARCH64_EXC_SYNC_SPX) |
|||
{ |
|||
printf("AARCH64_EXC_SYNC_SPX)\r\n"); |
|||
SerrHandle(exc); |
|||
} |
|||
|
|||
if ((exc->exc_type & 0xff) == AARCH64_EXC_IRQ_SPX) |
|||
{ |
|||
printf("AARCH64_EXC_IRQ_SPX)\r\n"); |
|||
SystemIrqHandler(exc); |
|||
} |
|||
|
|||
return; |
|||
} |
|||
@ -1,106 +0,0 @@ |
|||
/* -*- mode: asm; coding:utf-8 -*- */ |
|||
/************************************************************************/ |
|||
/* OS kernel sample */ |
|||
/* Copyright 2014 Takeharu KATO */ |
|||
/* */ |
|||
/************************************************************************/ |
|||
|
|||
#if !defined(_EXCEPTION_H) |
|||
#define _EXCEPTION_H |
|||
|
|||
/* Vector Table
|
|||
* see 5.1.1 Setting up a vector table in |
|||
* Application Note Bare-metal Boot Code for ARMv8-A Processors Version 1.0 |
|||
*/ |
|||
|
|||
/*
|
|||
* AArch64 exception types |
|||
*/ |
|||
/* Current EL with SP0 */ |
|||
#define AARCH64_EXC_SYNC_SP0 (0x1) /* Synchronous */ |
|||
#define AARCH64_EXC_IRQ_SP0 (0x2) /* IRQ/vIRQ */ |
|||
#define AARCH64_EXC_FIQ_SP0 (0x3) /* FIQ/vFIQ */ |
|||
#define AARCH64_EXC_SERR_SP0 (0x4) /* SError/vSError */ |
|||
/* Current EL with SPx */ |
|||
#define AARCH64_EXC_SYNC_SPX (0x11) |
|||
#define AARCH64_EXC_IRQ_SPX (0x12) |
|||
#define AARCH64_EXC_FIQ_SPX (0x13) |
|||
#define AARCH64_EXC_SERR_SPX (0x14) |
|||
/* Lower EL using AArch64 */ |
|||
#define AARCH64_EXC_SYNC_AARCH64 (0x21) |
|||
#define AARCH64_EXC_IRQ_AARCH64 (0x22) |
|||
#define AARCH64_EXC_FIQ_AARCH64 (0x23) |
|||
#define AARCH64_EXC_SERR_AARCH64 (0x24) |
|||
/* Lower EL using AArch32 */ |
|||
#define AARCH64_EXC_SYNC_AARCH32 (0x31) |
|||
#define AARCH64_EXC_IRQ_AARCH32 (0x32) |
|||
#define AARCH64_EXC_FIQ_AARCH32 (0x33) |
|||
#define AARCH64_EXC_SERR_AARCH32 (0x34) |
|||
|
|||
#if defined(ASM_FILE) |
|||
#define vector_table_align .align 11 /* Vector tables must be placed at a 2KB-aligned address */ |
|||
#define vector_entry_align .align 7 /* Each entry is 128B in size*/ |
|||
#define text_align .align 2 /* Text alignment */ |
|||
#endif /* ASM_FILE */ |
|||
|
|||
/*
|
|||
* exception_frame offset definitions |
|||
*/ |
|||
#define EXC_FRAME_SIZE (288) /* sizeof(struct _exception_frame) */ |
|||
#define EXC_EXC_TYPE_OFFSET (0) /* __asm_offsetof(struct _exception_frame, exc_type) */ |
|||
#define EXC_EXC_ESR_OFFSET (8) /* __asm_offsetof(struct _exception_frame, exc_esr) */ |
|||
#define EXC_EXC_SP_OFFSET (16) /* __asm_offsetof(struct _exception_frame, exc_sp) */ |
|||
#define EXC_EXC_ELR_OFFSET (24) /* __asm_offsetof(struct _exception_frame, exc_elr) */ |
|||
#define EXC_EXC_SPSR_OFFSET (32) /* __asm_offsetof(struct _exception_frame, exc_spsr) */ |
|||
|
|||
/*
|
|||
* IRQ |
|||
*/ |
|||
#define IRQ_FOUND (0) |
|||
#define IRQ_NOT_FOUND (1) |
|||
|
|||
#if !defined(ASM_FILE) |
|||
#include <stdint.h> |
|||
typedef struct _exception_frame |
|||
{ |
|||
uint64_t exc_type; |
|||
uint64_t exc_esr; |
|||
uint64_t exc_sp; |
|||
uint64_t exc_elr; |
|||
uint64_t exc_spsr; |
|||
uint64_t x0; |
|||
uint64_t x1; |
|||
uint64_t x2; |
|||
uint64_t x3; |
|||
uint64_t x4; |
|||
uint64_t x5; |
|||
uint64_t x6; |
|||
uint64_t x7; |
|||
uint64_t x8; |
|||
uint64_t x9; |
|||
uint64_t x10; |
|||
uint64_t x11; |
|||
uint64_t x12; |
|||
uint64_t x13; |
|||
uint64_t x14; |
|||
uint64_t x15; |
|||
uint64_t x16; |
|||
uint64_t x17; |
|||
uint64_t x18; |
|||
uint64_t x19; |
|||
uint64_t x20; |
|||
uint64_t x21; |
|||
uint64_t x22; |
|||
uint64_t x23; |
|||
uint64_t x24; |
|||
uint64_t x25; |
|||
uint64_t x26; |
|||
uint64_t x27; |
|||
uint64_t x28; |
|||
uint64_t x29; |
|||
uint64_t x30; |
|||
} exception_frame; |
|||
|
|||
void common_trap_handler(exception_frame *_exc); |
|||
#endif /* !ASM_FILE */ |
|||
#endif /* _EXCEPTION_H */ |
|||
@ -1,35 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2020 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-05-28 08:48:36 |
|||
* @LastEditTime: 2021-07-01 17:39:58 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#include "fsleep.h" |
|||
#include "generic_timer.h" |
|||
#include "parameters.h" |
|||
#include "ft_types.h" |
|||
#include <stdio.h> |
|||
|
|||
u32 fsleep_seconds(u32 seconds) |
|||
{ |
|||
u64 end_time; |
|||
u64 cur_time; |
|||
GenericTimerStart(); |
|||
cur_time = GenericTimerRead(); |
|||
end_time = cur_time + ((u64)seconds * GenericTimerFrequecy()); |
|||
printf("%d \r\n", GenericTimerFrequecy()); |
|||
do |
|||
{ |
|||
cur_time = GenericTimerRead(); |
|||
} while (cur_time < end_time); |
|||
|
|||
return 0; |
|||
} |
|||
@ -1,22 +0,0 @@ |
|||
/*
|
|||
* @ : Copyright (c) 2020 Phytium Information Technology, Inc. |
|||
* |
|||
* SPDX-License-Identifier: Apache-2.0. |
|||
* |
|||
* @Date: 2021-05-28 08:48:40 |
|||
* @LastEditTime: 2021-05-28 09:28:55 |
|||
* @Description: This files is for |
|||
* |
|||
* @Modify History: |
|||
* Ver Who Date Changes |
|||
* ----- ------ -------- -------------------------------------- |
|||
*/ |
|||
|
|||
#ifndef _BSP_ARCH_ARMV8_FSLEEP_H |
|||
#define _BSP_ARCH_ARMV8_FSLEEP_H |
|||
|
|||
#include "ft_types.h" |
|||
|
|||
u32 fsleep_seconds(u32 seconds); |
|||
|
|||
#endif // !
|
|||
@ -1,80 +0,0 @@ |
|||
#include "ft_types.h" |
|||
#include "ft_io.h" |
|||
#include "aarch64.h" |
|||
#include <stdio.h> |
|||
|
|||
extern void OutByte(s8 byte); |
|||
|
|||
u32 raw_read_cpacr_el1(void) |
|||
{ |
|||
u32 cpacr_el1; |
|||
|
|||
__asm__ __volatile__("mrs %0, cpacr_el1\n\t" |
|||
: "=r"(cpacr_el1) |
|||
: |
|||
: "memory"); |
|||
|
|||
return cpacr_el1; |
|||
} |
|||
|
|||
void reg_check(void) |
|||
{ |
|||
printf("cpacr_el1 %x \r\n", raw_read_cpacr_el1()); |
|||
while (1) |
|||
{ |
|||
/* code */ |
|||
} |
|||
} |
|||
|
|||
void hcr_el2_printf(void) |
|||
{ |
|||
printf("hcr_el2 %x \r\n", get_hcr_el2()); |
|||
while (1) |
|||
{ |
|||
/* code */ |
|||
} |
|||
} |
|||
|
|||
void print_xregs(u64 x0, u64 x1, u64 x2) |
|||
{ |
|||
printf("x0 %x \r\n", x0); |
|||
printf("x1 %x \r\n", x1); |
|||
printf("x2 %x \r\n", x2); |
|||
} |
|||
|
|||
void asm_pos_print(void) |
|||
{ |
|||
OutByte('2'); |
|||
OutByte('3'); |
|||
OutByte('3'); |
|||
OutByte('\n'); |
|||
} |
|||
|
|||
void asnyc_error_print(void) |
|||
{ |
|||
OutByte('a'); |
|||
OutByte('s'); |
|||
OutByte('s'); |
|||
OutByte('e'); |
|||
OutByte('\n'); |
|||
|
|||
while (1) |
|||
{ |
|||
/* code */ |
|||
} |
|||
} |
|||
|
|||
void check_error_print(void) |
|||
{ |
|||
OutByte('c'); |
|||
OutByte('h'); |
|||
OutByte('e'); |
|||
OutByte('c'); |
|||
OutByte('k'); |
|||
OutByte('\n'); |
|||
|
|||
while (1) |
|||
{ |
|||
/* code */ |
|||
} |
|||
} |
|||
@ -1,264 +0,0 @@ |
|||
/* SPDX-License-Identifier: GPL-2.0+ */ |
|||
/* |
|||
* (C) Copyright 2013 |
|||
* David Feng <fenghua@phytium.com.cn> |
|||
* |
|||
* This file is based on sample code from ARMv8 ARM. |
|||
*/ |
|||
|
|||
#include <linkage.h> |
|||
#include <macro.h> |
|||
|
|||
/* |
|||
* void __asm_dcache_level(level) |
|||
* |
|||
* flush or invalidate one level cache. |
|||
* |
|||
* x0: cache level |
|||
* x1: 0 clean & invalidate, 1 invalidate only |
|||
* x2~x9: clobbered |
|||
*/ |
|||
.pushsection .text.__asm_dcache_level, "ax" |
|||
ENTRY(__asm_dcache_level) |
|||
lsl x12, x0, #1 |
|||
msr csselr_el1, x12 /* select cache level */ |
|||
isb /* sync change of cssidr_el1 */ |
|||
mrs x6, ccsidr_el1 /* read the new cssidr_el1 */ |
|||
and x2, x6, #7 /* x2 <- log2(cache line size)-4 */ |
|||
add x2, x2, #4 /* x2 <- log2(cache line size) */ |
|||
mov x3, #0x3ff |
|||
and x3, x3, x6, lsr #3 /* x3 <- max number of #ways */ |
|||
clz w5, w3 /* bit position of #ways */ |
|||
mov x4, #0x7fff |
|||
and x4, x4, x6, lsr #13 /* x4 <- max number of #sets */ |
|||
/* x12 <- cache level << 1 */ |
|||
/* x2 <- line length offset */ |
|||
/* x3 <- number of cache ways - 1 */ |
|||
/* x4 <- number of cache sets - 1 */ |
|||
/* x5 <- bit position of #ways */ |
|||
|
|||
loop_set: |
|||
mov x6, x3 /* x6 <- working copy of #ways */ |
|||
loop_way: |
|||
lsl x7, x6, x5 |
|||
orr x9, x12, x7 /* map way and level to cisw value */ |
|||
lsl x7, x4, x2 |
|||
orr x9, x9, x7 /* map set number to cisw value */ |
|||
tbz w1, #0, 1f |
|||
dc isw, x9 |
|||
b 2f |
|||
1: dc cisw, x9 /* clean & invalidate by set/way */ |
|||
2: subs x6, x6, #1 /* decrement the way */ |
|||
b.ge loop_way |
|||
subs x4, x4, #1 /* decrement the set */ |
|||
b.ge loop_set |
|||
|
|||
ret |
|||
ENDPROC(__asm_dcache_level) |
|||
.popsection |
|||
|
|||
/* |
|||
* void __asm_flush_dcache_all(int invalidate_only) |
|||
* |
|||
* x0: 0 clean & invalidate, 1 invalidate only |
|||
* |
|||
* flush or invalidate all data cache by SET/WAY. |
|||
*/ |
|||
.pushsection .text.__asm_dcache_all, "ax" |
|||
ENTRY(__asm_dcache_all) |
|||
mov x1, x0 |
|||
dsb sy |
|||
mrs x10, clidr_el1 /* read clidr_el1 */ |
|||
lsr x11, x10, #24 |
|||
and x11, x11, #0x7 /* x11 <- loc */ |
|||
cbz x11, finished /* if loc is 0, exit */ |
|||
mov x15, lr |
|||
mov x0, #0 /* start flush at cache level 0 */ |
|||
/* x0 <- cache level */ |
|||
/* x10 <- clidr_el1 */ |
|||
/* x11 <- loc */ |
|||
/* x15 <- return address */ |
|||
|
|||
loop_level: |
|||
lsl x12, x0, #1 |
|||
add x12, x12, x0 /* x0 <- tripled cache level */ |
|||
lsr x12, x10, x12 |
|||
and x12, x12, #7 /* x12 <- cache type */ |
|||
cmp x12, #2 |
|||
b.lt skip /* skip if no cache or icache */ |
|||
bl __asm_dcache_level /* x1 = 0 flush, 1 invalidate */ |
|||
skip: |
|||
add x0, x0, #1 /* increment cache level */ |
|||
cmp x11, x0 |
|||
b.gt loop_level |
|||
|
|||
mov x0, #0 |
|||
msr csselr_el1, x0 /* restore csselr_el1 */ |
|||
dsb sy |
|||
isb |
|||
mov lr, x15 |
|||
|
|||
finished: |
|||
ret |
|||
ENDPROC(__asm_dcache_all) |
|||
.popsection |
|||
|
|||
.pushsection .text.__asm_flush_dcache_all, "ax" |
|||
ENTRY(__asm_flush_dcache_all) |
|||
mov x0, #0 |
|||
b __asm_dcache_all |
|||
ENDPROC(__asm_flush_dcache_all) |
|||
.popsection |
|||
|
|||
.pushsection .text.__asm_invalidate_dcache_all, "ax" |
|||
ENTRY(__asm_invalidate_dcache_all) |
|||
mov x0, #0x1 |
|||
b __asm_dcache_all |
|||
ENDPROC(__asm_invalidate_dcache_all) |
|||
.popsection |
|||
|
|||
/* |
|||
* void __asm_flush_dcache_range(start, end) |
|||
* |
|||
* clean & invalidate data cache in the range |
|||
* |
|||
* x0: start address |
|||
* x1: end address |
|||
*/ |
|||
.pushsection .text.__asm_flush_dcache_range, "ax" |
|||
ENTRY(__asm_flush_dcache_range) |
|||
mrs x3, ctr_el0 |
|||
lsr x3, x3, #16 |
|||
and x3, x3, #0xf |
|||
mov x2, #4 |
|||
lsl x2, x2, x3 /* cache line size */ |
|||
|
|||
/* x2 <- minimal cache line size in cache system */ |
|||
sub x3, x2, #1 |
|||
bic x0, x0, x3 |
|||
1: dc civac, x0 /* clean & invalidate data or unified cache */ |
|||
add x0, x0, x2 |
|||
cmp x0, x1 |
|||
b.lo 1b |
|||
dsb sy |
|||
ret |
|||
ENDPROC(__asm_flush_dcache_range) |
|||
.popsection |
|||
/* |
|||
* void __asm_invalidate_dcache_range(start, end) |
|||
* |
|||
* invalidate data cache in the range |
|||
* |
|||
* x0: start address |
|||
* x1: end address |
|||
*/ |
|||
.pushsection .text.__asm_invalidate_dcache_range, "ax" |
|||
ENTRY(__asm_invalidate_dcache_range) |
|||
mrs x3, ctr_el0 |
|||
ubfm x3, x3, #16, #19 |
|||
mov x2, #4 |
|||
lsl x2, x2, x3 /* cache line size */ |
|||
|
|||
/* x2 <- minimal cache line size in cache system */ |
|||
sub x3, x2, #1 |
|||
bic x0, x0, x3 |
|||
1: dc ivac, x0 /* invalidate data or unified cache */ |
|||
add x0, x0, x2 |
|||
cmp x0, x1 |
|||
b.lo 1b |
|||
dsb sy |
|||
ret |
|||
ENDPROC(__asm_invalidate_dcache_range) |
|||
.popsection |
|||
|
|||
/* |
|||
* void __asm_invalidate_icache_all(void) |
|||
* |
|||
* invalidate all tlb entries. |
|||
*/ |
|||
.pushsection .text.__asm_invalidate_icache_all, "ax" |
|||
ENTRY(__asm_invalidate_icache_all) |
|||
ic ialluis |
|||
isb sy |
|||
ret |
|||
ENDPROC(__asm_invalidate_icache_all) |
|||
.popsection |
|||
|
|||
.pushsection .text.AsmInvaliDateL3dcache, "ax" |
|||
ENTRY(AsmInvaliDateL3dcache) |
|||
mov x0, #0 /* return status as success */ |
|||
ret |
|||
ENDPROC(AsmInvaliDateL3dcache) |
|||
.weak AsmInvaliDateL3dcache |
|||
.popsection |
|||
|
|||
.pushsection .text.AsmFlushL3Dcache, "ax" |
|||
ENTRY(AsmFlushL3Dcache) |
|||
mov x0, #0 /* return status as success */ |
|||
ret |
|||
ENDPROC(AsmFlushL3Dcache) |
|||
.weak AsmFlushL3Dcache |
|||
.popsection |
|||
|
|||
.pushsection .text.__asm_invalidate_l3_icache, "ax" |
|||
ENTRY(__asm_invalidate_l3_icache) |
|||
mov x0, #0 /* return status as success */ |
|||
ret |
|||
ENDPROC(__asm_invalidate_l3_icache) |
|||
.weak __asm_invalidate_l3_icache |
|||
.popsection |
|||
|
|||
/* |
|||
* void __asm_switch_ttbr(ulong new_ttbr) |
|||
* |
|||
* Safely switches to a new page table. |
|||
*/ |
|||
.pushsection .text.__asm_switch_ttbr, "ax" |
|||
ENTRY(__asm_switch_ttbr) |
|||
/* x2 = SCTLR (alive throghout the function) */ |
|||
switch_el x4, 3f, 2f, 1f |
|||
3: mrs x2, sctlr_el3 |
|||
b 0f |
|||
2: mrs x2, sctlr_el2 |
|||
b 0f |
|||
1: mrs x2, sctlr_el1 |
|||
0: |
|||
|
|||
/* Unset CR_M | CR_C | CR_I from SCTLR to disable all caches */ |
|||
movn x1, #(1<<0 | 1<<2 | 1<<12) |
|||
and x1, x2, x1 |
|||
switch_el x4, 3f, 2f, 1f |
|||
3: msr sctlr_el3, x1 |
|||
b 0f |
|||
2: msr sctlr_el2, x1 |
|||
b 0f |
|||
1: msr sctlr_el1, x1 |
|||
0: isb |
|||
|
|||
/* This call only clobbers x30 (lr) and x9 (unused) */ |
|||
mov x3, x30 |
|||
bl __asm_invalidate_tlb_all |
|||
|
|||
/* From here on we're running safely with caches disabled */ |
|||
|
|||
/* Set TTBR to our first argument */ |
|||
switch_el x4, 3f, 2f, 1f |
|||
3: msr ttbr0_el3, x0 |
|||
b 0f |
|||
2: msr ttbr0_el2, x0 |
|||
b 0f |
|||
1: msr ttbr0_el1, x0 |
|||
0: isb |
|||
|
|||
/* Restore original SCTLR and thus enable caches again */ |
|||
switch_el x4, 3f, 2f, 1f |
|||
3: msr sctlr_el3, x2 |
|||
b 0f |
|||
2: msr sctlr_el2, x2 |
|||
b 0f |
|||
1: msr sctlr_el1, x2 |
|||
0: isb |
|||
|
|||
ret x3 |
|||
ENDPROC(__asm_switch_ttbr) |
|||
.popsection |
|||
@ -1,26 +0,0 @@ |
|||
.macro SMCCC instr |
|||
\instr #0 |
|||
ldr x4, [sp] |
|||
stp x0, x1, [x4, #0] |
|||
stp x2, x3, [x4, #16] |
|||
ldr x4, [sp, #8] |
|||
cbz x4, 1f /* no quirk structure */ |
|||
ldr x9, [x4, #0] |
|||
cmp x9, #1 |
|||
b.ne 1f |
|||
str x6, [x4, 4] |
|||
1: ret |
|||
.endm SMCCC instr |
|||
|
|||
/* |
|||
* void arm_smccc_smc(unsigned long a0, unsigned long a1, unsigned long a2, |
|||
* unsigned long a3, unsigned long a4, unsigned long a5, |
|||
* unsigned long a6, unsigned long a7, struct arm_smccc_res *res, |
|||
* struct arm_smccc_quirk *quirk) |
|||
*/ |
|||
.globl __arm_smccc_smc |
|||
.type __arm_smccc_smc, "function" |
|||
.cfi_startproc |
|||
__arm_smccc_smc: |
|||
SMCCC smc |
|||
.cfi_endproc |
|||
@ -1,142 +0,0 @@ |
|||
/* |
|||
* Branch according to exception level |
|||
*/ |
|||
#include "macro.h" |
|||
#include "sdkconfig.h" |
|||
|
|||
.section StartUp, "ax" |
|||
.section .vectors |
|||
.globl _boot |
|||
.global _boot |
|||
.type _boot, "function" |
|||
_boot: |
|||
mrs x0, CurrentEL |
|||
cmp x0, 0xc |
|||
b.eq el3_entry |
|||
cmp x0, 0x8 |
|||
b.eq el2_entry |
|||
cmp x0, 0x4 |
|||
b.eq el1_entry |
|||
bne hang |
|||
el3_entry: |
|||
// initialize sctlr_el2 and hcr_el2 to save values before entering el2. |
|||
msr sctlr_el2, xzr |
|||
msr hcr_el2, xzr |
|||
// determine the el2 execution state. |
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mrs x0, scr_el3 |
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orr x0, x0, #(1<<10) // rw el2 execution state is aarch64. |
|||
orr x0, x0, #(1<<0) // ns el1 is non-secure world. |
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msr scr_el3, x0 |
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mov x0, #0b01001 // daif=0000 |
|||
msr spsr_el3, x0 // m[4:0]=01001 el2h must match scr_el3.rw |
|||
// determine el2 entry. |
|||
adr x0, el2_entry // el2_entry points to the first instruction of |
|||
msr elr_el3, x0 // el2 code. |
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eret |
|||
el2_entry: |
|||
// initialize the sctlr_el1 register before entering el1. |
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msr sctlr_el1, xzr |
|||
mrs x0, hcr_el2 |
|||
orr x0, x0, #(1<<31) // rw=1 el1 execution state is aarch64. |
|||
msr hcr_el2, x0 |
|||
mov x0, #0b00101 // daif=0000 |
|||
msr spsr_el2, x0 // m[4:0]=00101 el1h must match hcr_el2.rw. |
|||
adr x0, el1_entry // el1_entry points to the first instruction of |
|||
msr elr_el2, x0 // el1 code. |
|||
eret |
|||
el1_entry: |
|||
adr x0, _vector_table |
|||
msr vbar_el1, x0 |
|||
mov x0, #3 << 20 |
|||
msr cpacr_el1, x0 /* Enable FP/SIMD */ |
|||
/* check CPU ID = 0x0, or jump to hang */ |
|||
mrs x0, mpidr_el1 |
|||
and x0, x0, #3 |
|||
cmp x0, #0 |
|||
bne hang |
|||
|
|||
master_cpu: |
|||
mov x1,#0x0 |
|||
orr x1, x1, #(1 << 18) // ; Set WFE non trapping |
|||
orr x1, x1, #(1 << 17) // ; Set WFI non trapping |
|||
orr x1, x1, #(1 << 5) // ; Set CP15 barrier enabled |
|||
msr SCTLR_EL1, x1 |
|||
isb |
|||
|
|||
msr DAIFclr, 0xF |
|||
/* configure stack */ |
|||
adrp x0, stack_top // Address of 4KB page at a PC-relative offset |
|||
magic_label: // Why do we need this label to let GDB step continually? |
|||
mov sp, x0 // sp = stack_top (align with 4KB page) |
|||
|
|||
/* Start copying data */ |
|||
ldr x0, =_rom_end |
|||
ldr x1, =__data_start |
|||
ldr x2, =__data_end |
|||
|
|||
data_loop: |
|||
cmp x1, x2 |
|||
ldp x10, x11, [x0], #16 /* copy from source address [x1] */ |
|||
stp x10, x11, [x1], #16 /* copy to target address [x0] */ |
|||
blt data_loop |
|||
|
|||
/* clear bss. */ |
|||
ldr x1, =__bss_start__ /* A 64-bit general-purpose register named X0 to X30 */ |
|||
ldr w2, =__bss_size /* A 32-bit general-purpose register named W0 to W30 */ |
|||
1: cbz w2, 2f /* Compare and Branch on Zero */ |
|||
str xzr, [x1], #8 |
|||
sub w2, w2, #1 |
|||
cbnz w2, 1b |
|||
|
|||
#ifdef CONFIG_USE_LIBC |
|||
// Set up _fini and fini_array to be called at exit |
|||
ldr x0, =__libc_fini_array |
|||
bl atexit |
|||
// Call preinit_array, _init and init_array |
|||
bl __libc_init_array |
|||
#endif |
|||
|
|||
#ifdef CONFIG_USE_CACHE |
|||
TLBI VMALLE1 //; TLBI VMALLE1, TLB Invalidate by VMID, All at stage 1, EL1 |
|||
ic IALLU //; Invalidate I cache to PoU |
|||
|
|||
#ifdef CONFIG_USE_MMU |
|||
bl MmuInit |
|||
#endif |
|||
bl DcacheInvalidate |
|||
|
|||
// Enable caches and the MMU. |
|||
MRS X0, SCTLR_EL1 |
|||
ORR X0, X0, #(0x1 << 2) // The C bit (data cache). |
|||
ORR X0, X0, #(0x1 << 12) // The I bit (instruction cache). |
|||
#ifdef CONFIG_USE_MMU |
|||
ORR X0, X0, #0x1 // The M bit (MMU). |
|||
#endif |
|||
MSR SCTLR_EL1, X0 |
|||
DSB SY |
|||
ISB |
|||
|
|||
dsb ish // ensure all previous stores have completed before invalidating |
|||
ic ialluis // I cache invalidate all inner shareable to PoU (which includes secondary cores) |
|||
dsb ish // ensure completion on inner shareable domain (which includes secondary cores) |
|||
isb |
|||
|
|||
#endif |
|||
|
|||
#ifdef CONFIG_USE_LIBC |
|||
// Set up the standard file handles |
|||
bl initialise_monitor_handles |
|||
#endif |
|||
2: |
|||
bl main |
|||
|
|||
hang: |
|||
wfi |
|||
b hang |
|||
|
|||
|
|||
|
|||
|
|||
|
|||
|
|||
# ========================================= |
|||
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Reference in new issue