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160 lines
5.7 KiB
160 lines
5.7 KiB
/*
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* Copyright : (C) 2024 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgpio_table.c
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* Date: 2023-11-6 10:33:28
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* LastEditTime: 2023-11-6 10:33:28
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* Description: This file is for GPIO pin definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2024/5/9 init commit
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*/
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#include "fparameters.h"
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#include "fgpio.h"
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#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \
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{ \
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.id = FGPIO_ID(_ctrl, _pin), \
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.ctrl = _ctrl, \
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.port = _port, \
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.pin = _pin, \
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.base_addr = _base, \
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.irq_num = _irq, \
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.cap = _cap \
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}
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#define FGPIO_PIN_CONFIG_0(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN)
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#define FGPIO_PIN_CONFIG_1(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN)
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#define FGPIO_PIN_CONFIG_2(pin, irq) FGPIO_PIN_CONFIG(FGPIO2_BASE_ADDR, FGPIO_CTRL_2, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL)
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#define FGPIO_PIN_CONFIG_3(pin, irq) FGPIO_PIN_CONFIG(FGPIO3_BASE_ADDR, FGPIO_CTRL_3, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL)
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const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
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{
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/* GPIO-0, IRQ 128 ~ 143 */
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_0, 128U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_1, 129U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_2, 130U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_3, 131U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_4, 132U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_5, 133U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_6, 134U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_7, 135U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_8, 136U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_9, 137U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_10, 138U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_11, 139U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_12, 140U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_13, 141U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_14, 142U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_15, 143U),
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/* GPIO-1, IRQ 144 ~ 159 */
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_0, 144U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_1, 145U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_2, 146U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_3, 147U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_4, 148U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_5, 149U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_6, 150U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_7, 151U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_8, 152U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_9, 153U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_10, 154U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_11, 155U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_12, 156U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_13, 157U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_14, 158U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_15, 159U),
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/* GPIO-2, IRQ 160 */
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_0, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_1, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_2, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_3, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_4, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_5, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_6, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_7, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_8, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_9, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_10, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_11, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_12, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_13, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_14, 160U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_15, 160U),
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/* GPIO-3 IRQ 161 */
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_0, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_1, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_2, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_3, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_4, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_5, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_6, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_7, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_8, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_9, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_10, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_11, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_12, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_13, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_14, 161U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_15, 161U)
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};
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#define FGPIO_INTR_MAP_CONFIG(_base) \
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{ \
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.base_addr = _base, \
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.irq_cbs = {NULL}, \
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.irq_cb_params = {NULL},\
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}
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FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] =
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{
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/* GPIO 0 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR),
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/* GPIO 1 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR),
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/* GPIO 2 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO2_BASE_ADDR),
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/* GPIO 3 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO3_BASE_ADDR)
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};
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const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num)
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{
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u32 index;
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const FGpioConfig *ptr = NULL;
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for (index = 0; index < FGPIO_NUM; index++)
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{
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/* 如果引脚单独上报中断，返回对应引脚的配置
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如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置
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如果引脚不支持中断，返回 NULL */
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if (fgpio_cfg_tbl[index].irq_num == irq_num)
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{
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ptr = &fgpio_cfg_tbl[index];
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break;
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}
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}
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return ptr;
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}
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