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203 lines
7.6 KiB
203 lines
7.6 KiB
/*
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* Copyright : (C) 2024 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fgpio_table.c
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* Date: 2023-11-6 10:33:28
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* LastEditTime: 2023-11-6 10:33:28
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* Description: This file is for GPIO pin definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2024/5/9 init commit
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*/
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#include "fparameters.h"
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#include "fgpio.h"
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#define FGPIO_PIN_CONFIG(_base, _ctrl, _port, _pin, _irq, _cap) \
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{ \
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.id = FGPIO_ID(_ctrl, _pin), \
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.ctrl = _ctrl, \
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.port = _port, \
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.pin = _pin, \
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.base_addr = _base, \
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.irq_num = _irq, \
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.cap = _cap \
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}
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#define FGPIO_PIN_CONFIG_0(pin, irq) FGPIO_PIN_CONFIG(FGPIO0_BASE_ADDR, FGPIO_CTRL_0, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN)
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#define FGPIO_PIN_CONFIG_1(pin, irq) FGPIO_PIN_CONFIG(FGPIO1_BASE_ADDR, FGPIO_CTRL_1, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN)
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#define FGPIO_PIN_CONFIG_2(pin, irq) FGPIO_PIN_CONFIG(FGPIO2_BASE_ADDR, FGPIO_CTRL_2, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_PIN)
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#define FGPIO_PIN_CONFIG_3(pin, irq) FGPIO_PIN_CONFIG(FGPIO3_BASE_ADDR, FGPIO_CTRL_3, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL)
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#define FGPIO_PIN_CONFIG_4(pin, irq) FGPIO_PIN_CONFIG(FGPIO4_BASE_ADDR, FGPIO_CTRL_4, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL)
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#define FGPIO_PIN_CONFIG_5(pin, irq) FGPIO_PIN_CONFIG(FGPIO5_BASE_ADDR, FGPIO_CTRL_5, FGPIO_PORT_A, (pin), (irq), FGPIO_CAP_IRQ_BY_CTRL)
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const FGpioConfig fgpio_cfg_tbl[FGPIO_NUM] =
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{
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/* GPIO 0, IRQ 140 ~ 155 */
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_0, 140U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_1, 141U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_2, 142U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_3, 143U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_4, 144U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_5, 145U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_6, 146U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_7, 147U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_8, 148U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_9, 149U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_10, 150U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_11, 151U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_12, 152U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_13, 153U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_14, 154U),
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FGPIO_PIN_CONFIG_0(FGPIO_PIN_15, 155U),
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/* GPIO 1, IRQ 156 ~ 171 */
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_0, 156U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_1, 157U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_2, 158U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_3, 159U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_4, 160U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_5, 161U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_6, 162U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_7, 163U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_8, 164U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_9, 165U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_10, 166U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_11, 167U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_12, 168U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_13, 169U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_14, 170U),
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FGPIO_PIN_CONFIG_1(FGPIO_PIN_15, 171U),
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/* GPIO 2, IRQ 172 ~ 187 */
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_0, 172U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_1, 173U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_2, 174U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_3, 175U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_4, 176U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_5, 177U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_6, 178U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_7, 179U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_8, 180U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_9, 181U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_10, 182U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_11, 183U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_12, 184U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_13, 185U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_14, 186U),
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FGPIO_PIN_CONFIG_2(FGPIO_PIN_15, 187U),
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/* GPIO 3, IRQ 188 */
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_0, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_1, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_2, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_3, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_4, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_5, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_6, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_7, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_8, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_9, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_10, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_11, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_12, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_13, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_14, 188U),
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FGPIO_PIN_CONFIG_3(FGPIO_PIN_15, 188U),
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/* GPIO 4, IRQ 189 */
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_0, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_1, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_2, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_3, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_4, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_5, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_6, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_7, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_8, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_9, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_10, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_11, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_12, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_13, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_14, 189U),
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FGPIO_PIN_CONFIG_4(FGPIO_PIN_15, 189U),
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/* GPIO 5, IRQ 190 */
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_0, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_1, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_2, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_3, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_4, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_5, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_6, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_7, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_8, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_9, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_10, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_11, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_12, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_13, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_14, 190U),
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FGPIO_PIN_CONFIG_5(FGPIO_PIN_15, 190U)
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};
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#define FGPIO_INTR_MAP_CONFIG(_base) \
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{ \
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.base_addr = _base, \
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.irq_cbs = {NULL}, \
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.irq_cb_params = {NULL},\
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}
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FGpioIntrMap fgpio_intr_map[FGPIO_CTRL_NUM] =
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{
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/* GPIO 0 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO0_BASE_ADDR),
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/* GPIO 1 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO1_BASE_ADDR),
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/* GPIO 2 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO2_BASE_ADDR),
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/* GPIO 3 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO3_BASE_ADDR),
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/* GPIO 4 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO4_BASE_ADDR),
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/* GPIO 5 IRQ Map */
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FGPIO_INTR_MAP_CONFIG(FGPIO5_BASE_ADDR)
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};
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const FGpioConfig *FGpioLookupConfigByIrqNum(s32 irq_num)
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{
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u32 index;
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const FGpioConfig *ptr = NULL;
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for (index = 0; index < FGPIO_NUM; index++)
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{
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/* 如果引脚单独上报中断，返回对应引脚的配置
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如果引脚通过控制器统一上报中断，共用中断号，返回使用该中断号的第一个引脚的配置
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如果引脚不支持中断，返回 NULL */
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if (fgpio_cfg_tbl[index].irq_num == irq_num)
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{
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ptr = &fgpio_cfg_tbl[index];
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break;
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}
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}
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return ptr;
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}
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