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349 lines
8.0 KiB
349 lines
8.0 KiB
8 months ago
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/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __NAND_H
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#define __NAND_H
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#include <asm/io.h>
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#define nandc_writel(v, offs) writel((v), (offs) + nandc_base)
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#define nandc_readl(offs) readl((offs) + nandc_base)
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#define NANDC_READ 0
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#define NANDC_WRITE 1
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#define RK3326_NANDC_VER 0x56393030
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/* INT ID */
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enum NANDC_IRQ_NUM_T {
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NC_IRQ_DMA = 0,
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NC_IRQ_FRDY,
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NC_IRQ_BCHERR,
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NC_IRQ_BCHFAIL,
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NC_IRQ_LLP
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};
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enum ENUM_NANDC_BCH_CFG {
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NC_BCH_70 = 0,
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NC_BCH_24,
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NC_BCH_40,
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NC_BCH_60,
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};
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union FM_CTL_T {
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u32 d32;
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struct {
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unsigned cs : 8; /* bits[0:7] */
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unsigned wp : 1; /* bits[8] */
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unsigned rdy : 1; /* bits[9] */
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unsigned fifo_empty : 1; /* bits[10] */
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unsigned reserved11 : 1; /* bits[11] */
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unsigned dwidth : 1; /* bits[12] */
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unsigned tm : 1; /* bits[13] */
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unsigned onficlk_en : 1; /* bits[14] */
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unsigned toggle_en : 1; /* bits[15] */
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unsigned flash_abort_en : 1; /* bits[16] */
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unsigned flash_abort_clear : 1; /* bits[17] */
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unsigned reserved18_23 : 6; /* bits[18:23] */
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unsigned read_delay : 3; /* bits[24:26] */
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unsigned reserved27_31 : 5; /* bits[27:31] */
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} V6;
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struct {
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unsigned cs : 8;
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unsigned wp : 1;
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unsigned frdy : 1;
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unsigned fifo_empth_flash : 1;
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unsigned reserved11_12 : 2;
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unsigned tm : 1;
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unsigned syn_clken : 1;
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unsigned syn_mode : 1;
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unsigned flash_abort_en : 1;
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unsigned flash_abort_clear : 1;
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unsigned sif_read_delay : 3;
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unsigned io_mux : 3;
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unsigned reserved24_31 : 8;
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} V9;
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};
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union FM_WAIT_T {
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u32 d32;
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struct {
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unsigned csrw : 5;
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unsigned rwpw : 6;
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unsigned rdy : 1;
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unsigned rwcs : 6;
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unsigned reserved18_23 : 6;
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unsigned fmw_dly : 6;
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unsigned fmw_dly_en : 1;
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unsigned reserved31_31 : 1;
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} V6;
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struct {
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unsigned rwcs : 5;
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unsigned rwpw : 6;
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unsigned hard_rdy : 1;
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unsigned csrw : 6;
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unsigned wait_frdy_dly : 5;
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unsigned reserved23_23 : 1;
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unsigned fmw_dly : 6;
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unsigned fmw_dly_en : 1;
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unsigned reserved31_31 : 1;
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} V9;
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};
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union FL_CTL_T {
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u32 d32;
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struct {
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unsigned rst : 1;
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unsigned rdn : 1;
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unsigned start : 1;
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unsigned dma : 1;
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unsigned st_addr : 1;
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unsigned tr_count : 2;
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unsigned rdy_ignore : 1;
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/* unsigned int_clr : 1; */
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/* unsigned int_en : 1; */
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unsigned reserved8_9 : 2;
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unsigned cor_en : 1;
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unsigned lba_en : 1;
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unsigned spare_size : 7;
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unsigned reserved19 : 1;
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unsigned tr_rdy : 1;
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unsigned page_size : 1;
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unsigned page_num : 6;
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unsigned low_power : 1;
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unsigned async_tog_mix : 1;
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unsigned reserved30_31 : 2;
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} V6;
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struct {
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unsigned flash_rst : 1;
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unsigned flash_rdn : 1;
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unsigned flash_st : 1;
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unsigned bypass : 1;
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unsigned st_addr : 1;
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unsigned tr_count : 2;
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unsigned flash_st_mod : 1;
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unsigned not_tran_data : 1;
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unsigned tran_seed : 1;
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unsigned cor_able : 1;
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unsigned lba_en : 1;
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unsigned lba_spare_sel : 1;
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unsigned reserved13_18 : 6;
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unsigned bchst_trans : 1;
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unsigned tr_rdy : 1;
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unsigned page_size : 1;
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unsigned page_num : 6;
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unsigned low_power : 1;
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unsigned async_tog_mix : 1;
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unsigned bypass_fifo_mode : 1;
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unsigned reserved31_31 : 1;
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} V9;
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};
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union BCH_CTL_T {
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u32 d32;
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struct {
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unsigned rst : 1;
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unsigned reserved : 1;
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unsigned addr_not_care : 1;
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unsigned power_down : 1;
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unsigned bch_mode : 1; /* 0-16bit/1KB, 1-24bit/1KB */
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unsigned region : 3;
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unsigned addr : 8;
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unsigned bchpage : 1;
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unsigned reserved17 : 1;
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unsigned bch_mode1 : 1;
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unsigned thres : 8;
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unsigned reserved27_31 : 5;
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} V6;
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struct {
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unsigned bchrst : 1;
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unsigned wcnt_clear : 1;
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unsigned reserved2 : 1;
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unsigned bchepd : 1;
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unsigned reserved4_15 : 12;
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unsigned bchpage : 1;
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unsigned bchthre : 8;
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unsigned bchmode : 3;
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unsigned reserved28_31 : 4;
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} V9;
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};
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union BCH_ST_T {
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u32 d32;
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struct {
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unsigned errf0 : 1;
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unsigned done0 : 1;
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unsigned fail0 : 1;
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unsigned err_bits0 : 5;
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unsigned err_bits_low0 : 5;
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unsigned errf1 : 1;
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unsigned done1 : 1;
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unsigned fail1 : 1;
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unsigned err_bits1 : 5;
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unsigned err_bits_low1 : 5;
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unsigned rdy : 1;
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/* unsigned cnt : 1; */
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unsigned err_bits0_5 : 1;
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unsigned err_bits_low0_5 : 1;
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unsigned err_bits1_5 : 1;
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unsigned err_bits_low1_5 : 1;
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unsigned reserved31_31 : 1;
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} V6;
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struct {
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unsigned errf0 : 1;
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unsigned done0 : 1;
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unsigned fail0 : 1;
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unsigned err_bits0 : 7;
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unsigned all_f_flag0 : 1;
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unsigned reserved11_15 : 5;
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unsigned errf1 : 1;
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unsigned done1 : 1;
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unsigned fail1 : 1;
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unsigned err_bits1 : 7;
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unsigned all_f_flag1 : 1;
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unsigned reserved27_30 : 4;
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unsigned bch_ready_flag: 1;
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} V9;
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};
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union MTRANS_CFG_T {
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u32 d32;
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struct {
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unsigned ahb_wr_st : 1;
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unsigned ahb_wr : 1;
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unsigned bus_mode : 1;
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unsigned hsize : 3;
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unsigned burst : 3;
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unsigned incr_num : 5;
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unsigned fl_pwd : 1;
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unsigned ahb_rst : 1;
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unsigned reserved16_31 : 16;
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} V6;
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struct {
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unsigned ahb_wr_st : 1;
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unsigned ahb_wr : 1;
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unsigned bus_mode : 1;
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unsigned hsize : 3;
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unsigned burst : 3;
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unsigned incr_num : 5;
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unsigned fl_pwd : 1;
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unsigned ahb_rst : 1;
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unsigned redundance_size : 11;
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unsigned reserved27_31 : 5;
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} V9;
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};
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union MTRANS_STAT_T {
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u32 d32;
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struct {
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unsigned bus_err : 16;
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unsigned mtrans_cnt : 5;
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unsigned reserved21_31 : 11;
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} V6;
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struct {
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unsigned bus_err : 16;
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unsigned mtrans_cnt : 6;
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unsigned reserved22_31 : 10;
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} V9;
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};
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/* NANDC Registers */
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#define NANDC_FMCTL 0x0
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#define NANDC_FMWAIT 0x4
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#define NANDC_FLCTL 0x8
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#define NANDC_BCHCTL 0xc
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#define NANDC_MTRANS_CFG 0x10
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#define NANDC_MTRANS_SADDR0 0x14
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#define NANDC_MTRANS_SADDR1 0x18
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#define NANDC_MTRANS_STAT 0x1c
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#define NANDC_DLL_CTL_REG0 0x130
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#define NANDC_DLL_CTL_REG1 0x134
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#define NANDC_DLL_OBS_REG0 0x138
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#define NANDC_RANDMZ_CFG 0x150
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#define NANDC_EBI_EN 0x154
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#define NANDC_FMWAIT_SYN 0x158
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#define NANDC_MTRANS_STAT2 0x15c
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#define NANDC_NANDC_VER 0x160
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#define NANDC_LLP_CTL 0x164
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#define NANDC_LLP_STAT 0x168
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#define NANDC_INTEN 0x16c
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#define NANDC_INTCLR 0x170
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#define NANDC_INTST 0x174
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#define NANDC_SPARE0 0x200
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#define NANDC_SPARE1 0x230
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#define NANDC_BCHST(i) ({ \
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u32 x = (i); \
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4 * x + x < 8 ? 0x20 : 0x520; })
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#define NANDC_CHIP_DATA(id) (0x800 + (id) * 0x100)
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#define NANDC_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4)
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#define NANDC_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8)
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#define NANDC_V9_FMCTL 0x0
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#define NANDC_V9_FMWAIT 0x4
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#define NANDC_V9_FLCTL 0x10
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#define NANDC_V9_BCHCTL 0x20
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#define NANDC_V9_MTRANS_CFG 0x30
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#define NANDC_V9_MTRANS_SADDR0 0x34
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#define NANDC_V9_MTRANS_SADDR1 0x38
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#define NANDC_V9_MTRANS_STAT 0x40
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#define NANDC_V9_MTRANS_STAT2 0x44
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#define NANDC_V9_NANDC_VER 0x80
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#define NANDC_V9_INTEN 0x120
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#define NANDC_V9_INTCLR 0x124
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#define NANDC_V9_INTST 0x128
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#define NANDC_V9_SPARE0 0x200
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#define NANDC_V9_SPARE1 0x204
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#define NANDC_V9_RANDMZ_CFG 0x208
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#define NANDC_V9_BCHST(i) (0x150 + (i) * 4)
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#define NANDC_V9_CHIP_DATA(id) (0x800 + (id) * 0x100)
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#define NANDC_V9_CHIP_ADDR(id) (0x800 + (id) * 0x100 + 0x4)
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#define NANDC_V9_CHIP_CMD(id) (0x800 + (id) * 0x100 + 0x8)
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struct MASTER_INFO_T {
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u32 *page_buf; /* [DATA_LEN]; */
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u32 *spare_buf; /* [DATA_LEN / (1024/128)]; */
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u32 *page_vir; /* page_buf_vir_addr */
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u32 *spare_vir; /* spare_buf_vir_addr */
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u32 page_phy; /* page_buf_phy_addr */
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u32 spare_phy; /* spare_buf_phy_addr*/
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u32 mapped;
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u32 cnt;
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};
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struct CHIP_MAP_INFO_T {
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u32 *nandc_addr;
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u32 chip_num;
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};
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unsigned long rknandc_dma_map_single(unsigned long ptr,
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int size,
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int dir);
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void rknandc_dma_unmap_single(unsigned long ptr,
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int size,
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int dir);
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void nandc_init(void __iomem *nandc_addr);
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void nandc_flash_cs(u8 chip_sel);
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void nandc_flash_de_cs(u8 chip_sel);
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u32 nandc_wait_flash_ready(u8 chip_sel);
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u32 nandc_delayns(u32 count);
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u32 nandc_xfer_data(u8 chip_sel,
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u8 dir,
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u8 sector_count,
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u32 *p_data,
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u32 *p_spare);
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void nandc_randmz_sel(u8 chip_sel, u32 randmz_seed);
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void nandc_bch_sel(u8 bits);
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void nandc_read_not_case_busy_en(u8 en);
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void nandc_time_cfg(u32 ns);
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void nandc_clean_irq(void);
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u8 nandc_get_version(void);
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#endif
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