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73 lines
2.0 KiB
73 lines
2.0 KiB
/*
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* Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef __FLASH_COM_H
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#define __FLASH_COM_H
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#include "typedef.h"
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#define NAND_ERROR INVALID_UINT32
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#define NAND_OK 0
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#define NAND_STS_OK 0 /* bit 0 ecc error or ok */
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#define NAND_STS_REFRESH 256 /* need refresh */
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#define NAND_STS_EMPTY 512 /* page is not proged */
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#define NAND_STS_ECC_ERR NAND_ERROR
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#define NAND_IDB_START 64 /* 32 KB*/
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#define NAND_IDB_SIZE 512 /* 256 KB*/
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#define NAND_IDB_END (NAND_IDB_START + NAND_IDB_SIZE - 1)
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#define DEFAULT_IDB_RESERVED_BLOCK 8
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#define FULL_SLC 0
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#define SLC 1
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#define NAND_FLASH_MLC_PAGE_TAG 0xFFFF
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#define MAX_FLASH_PAGE_SIZE 0x1000 /* 4KB */
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#define PAGE_ADDR_BITS 0
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#define PAGE_ADDR_MASK ((1u << 11) - 1)
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#define BLOCK_ADDR_BITS 11
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#define BLOCK_ADDR_MASK ((1u << 14) - 1)
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#define DIE_ADDR_BITS 25
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#define DIE_ADDR_MASK ((1u << 3) - 1)
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#define FLAG_ADDR_BITS 28
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#define FLAG_ADDR_MASK ((1u << 4) - 1)
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#define PHY_BLK_DIE_ADDR_BITS 14
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struct nand_req {
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u32 status;
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u32 page_addr; /* 31:28 flag, 27:25: die, 24:11 block, 10:0 page */
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u32 *p_data;
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u32 *p_spare;
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u32 lpa;
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};
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struct nand_phy_info {
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u16 nand_type; /* SLC,MLC,TLC */
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u16 die_num; /* number of LUNs */
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u16 plane_per_die;
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u16 blk_per_plane;
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u16 blk_per_die;
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u16 page_per_blk; /* in MLC mode */
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u16 page_per_slc_blk; /* in SLC mode */
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u16 sec_per_page; /* physical page data size */
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u16 sec_per_blk; /* physical page data size */
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u16 byte_per_sec; /* size of logical sectors */
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u16 reserved_blk; /* reserved for boot loader in die 0*/
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u8 ecc_bits;
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};
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struct nand_ops {
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s32 (*get_bad_blk_list)(u16 *table, u32 die);
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u32 (*erase_blk)(u8 cs, u32 page_addr);
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u32 (*prog_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare);
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u32 (*read_page)(u8 cs, u32 page_addr, u32 *data, u32 *spare);
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void (*bch_sel)(u8 bits);
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void (*set_sec_num)(u8 num);
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};
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#endif
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